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TW200725734A - Plasma etching method and making method of semiconductor - Google Patents

Plasma etching method and making method of semiconductor

Info

Publication number
TW200725734A
TW200725734A TW095143594A TW95143594A TW200725734A TW 200725734 A TW200725734 A TW 200725734A TW 095143594 A TW095143594 A TW 095143594A TW 95143594 A TW95143594 A TW 95143594A TW 200725734 A TW200725734 A TW 200725734A
Authority
TW
Taiwan
Prior art keywords
film
plasma etching
etching
semiconductor
hole
Prior art date
Application number
TW095143594A
Other languages
Chinese (zh)
Other versions
TWI412075B (en
Inventor
Kensuke Taniguchi
Yasuhiko Fukino
Original Assignee
Tokyo Electron Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Electron Ltd filed Critical Tokyo Electron Ltd
Publication of TW200725734A publication Critical patent/TW200725734A/en
Application granted granted Critical
Publication of TWI412075B publication Critical patent/TWI412075B/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Chemical & Material Sciences (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Inorganic Chemistry (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)
  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

The invention provides etching method for handling large-sized glass substrate. The silicon nitride film can be acquired on the source and drain electrodes with high melting point metal material by selective etching. The solving means is using CF4 and O2 as handling gases to pass through inactivation film 108 and gate insulation film 103 by executing plasma etching process. The hole 111 at gate electrode 102 and the hole 112 passing through inactivation film 108 at drain electrode 107 are formed at one time. The gate insulation film 103 relative to the Mo layer 107c of the surface of drain electrode 107 is etching with high selective ratio.
TW095143594A 2005-11-25 2006-11-24 Plasma etching method and manufacturing method of semiconductor TWI412075B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005340542A JP4936709B2 (en) 2005-11-25 2005-11-25 Plasma etching method and semiconductor device manufacturing method

Publications (2)

Publication Number Publication Date
TW200725734A true TW200725734A (en) 2007-07-01
TWI412075B TWI412075B (en) 2013-10-11

Family

ID=38112583

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095143594A TWI412075B (en) 2005-11-25 2006-11-24 Plasma etching method and manufacturing method of semiconductor

Country Status (4)

Country Link
JP (1) JP4936709B2 (en)
KR (1) KR100835023B1 (en)
CN (1) CN100492601C (en)
TW (1) TWI412075B (en)

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CN101866876B (en) * 2009-04-14 2012-05-09 中芯国际集成电路制造(上海)有限公司 Process for manufacturing contact hole
JP5310409B2 (en) * 2009-09-04 2013-10-09 東京エレクトロン株式会社 Plasma etching method
JP5299245B2 (en) * 2009-12-03 2013-09-25 カシオ計算機株式会社 Method for dry etching insulating film on molybdenum metal film and method for manufacturing thin film transistor panel
CN102651317B (en) * 2011-12-28 2015-06-03 京东方科技集团股份有限公司 Surface treatment method of metal oxide and preparation method of thin film transistor
US8940647B2 (en) 2011-12-28 2015-01-27 Boe Technology Group Co., Ltd. Method for surface treatment on a metal oxide and method for preparing a thin film transistor
CN102751241B (en) * 2012-06-29 2014-05-21 京东方科技集团股份有限公司 Method for manufacturing array substrate via hole and array substrate manufacturing process
CN103489786B (en) * 2013-09-18 2015-11-25 京东方科技集团股份有限公司 A kind of manufacture method of array base palte
JP6207947B2 (en) * 2013-09-24 2017-10-04 東京エレクトロン株式会社 Method for plasma processing a workpiece
KR102188067B1 (en) * 2014-05-27 2020-12-07 엘지디스플레이 주식회사 Thin Film Transistor Array Substrate and Method for Manufacturing the Same
KR102635447B1 (en) 2018-06-25 2024-02-08 삼성디스플레이 주식회사 Method for manufacturing organic light emitting display
JP7061941B2 (en) * 2018-08-06 2022-05-02 東京エレクトロン株式会社 Etching method and manufacturing method of semiconductor device

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US2003A (en) * 1841-03-12 Improvement in horizontal windivhlls
DE2658448C3 (en) * 1976-12-23 1979-09-20 Deutsche Itt Industries Gmbh, 7800 Freiburg Process for etching a layer of silicon nitride applied to a semiconductor body in a gas plasma
JPH01187872A (en) * 1988-01-14 1989-07-27 Fujitsu Ltd Manufacture of semiconductor device
JPH09148429A (en) * 1995-11-17 1997-06-06 Sony Corp Manufacture of semiconductor device
JP3362093B2 (en) * 1995-12-11 2003-01-07 株式会社日立製作所 How to remove etching damage
WO1997026585A1 (en) * 1996-01-18 1997-07-24 Hitachi, Ltd. Liquid crystal display device and method for manufacturing the same
US6303045B1 (en) * 1997-03-20 2001-10-16 Lam Research Corporation Methods and apparatus for etching a nitride layer in a variable-gap plasma processing chamber
US5786276A (en) * 1997-03-31 1998-07-28 Applied Materials, Inc. Selective plasma etching of silicon nitride in presence of silicon or silicon oxides using mixture of CH3F or CH2F2 and CF4 and O2
JP3587683B2 (en) * 1997-05-27 2004-11-10 三菱電機株式会社 Active matrix substrate, method for forming contact hole in the substrate, and liquid crystal display device using the substrate
KR19990021368A (en) * 1997-08-30 1999-03-25 김영환 Method of manufacturing fine contact of semiconductor device
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US6060400A (en) * 1998-03-26 2000-05-09 The Research Foundation Of State University Of New York Highly selective chemical dry etching of silicon nitride over silicon and silicon dioxide
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JP4060125B2 (en) * 2002-05-30 2008-03-12 シャープ株式会社 Substrate for liquid crystal display device, liquid crystal display device including the same, and manufacturing method thereof
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Also Published As

Publication number Publication date
JP2007149852A (en) 2007-06-14
KR100835023B1 (en) 2008-06-03
KR20070055384A (en) 2007-05-30
CN100492601C (en) 2009-05-27
TWI412075B (en) 2013-10-11
CN1971856A (en) 2007-05-30
JP4936709B2 (en) 2012-05-23

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