TW200540743A - Low noise data output driving circuit and method - Google Patents

Abstract

A low noise data output driving circuit comprising a data comparison circuit, a data inversion judgement circuit, and a data inversion signal generating circuit, and a data inversion circuit is provided. The data comparison circuit receives a plurality of values of data bits in the order of a first and a second period and generates a set of data change signals. The data change signals are corresponding to the number of data bits that have different value in the first and second period. The data inversion judgement circuit generates a data change voltage according to the data change signals and then generates a judgement signal by comparing the data change voltage with a reference voltage. The data inversion signal generating circuit generates a first and a second inversion signal for the values of data bits in the first and a second period, wherein the second inversion signal is generated according to the judgement signal and the first inversion signal. The data inversion circuit selectively outputs one of the value or the complement value of each data bit in the second period according to the second inversion signal.

Description

200540743 V. Description of the invention (1) Technology of the invention The present invention relates to a data output driving circuit, and more particularly to a low-noise data output driving circuit and a data inversion judgment circuit therein. In recent years, the liquid crystal display technology has gradually been widely used in daily life, such as liquid crystal televisions (LCD TVs), notebook computers (Noteb 00k) or desktop computers (LCD), And liquid crystal projector (LCD projector), etc., among them, the liquid crystal projector is one of the technologies indispensable for large-scale display. Since the liquid crystal display panel used by a liquid crystal projector must take into account the projected image resolution (res 〇 丨 ut 丨 〇n), most of them will use a monocrystalline evening reflection type liquid crystal panel with a relatively high resolution, and The spar night reflection type liquid crystal panel belongs to a non-direct view type reflection type liquid crystal display. A general monocrystalline silicon reflective liquid crystal panel is a liquid crystal display element structured on a silicon substrate. Since the monocrystalline evening liquid crystal display panel uses a metal-Oxide-Semiconductor transistor (MOS transistor) as an active element, these active elements can be provided with reflective electrodes that are electrically coupled to the active elements. Drive the liquid crystal to achieve the purpose of display. Because the monocrystalline silicon reflective LCD panel is structured on a silicon substrate, it is small in size and has a high resolution. 'It is in line with the ever-decreasing volume requirements of LCD projectors. In the driving circuit of LCD panels,' in order to reduce data transmission, Time, since 200540743

The problem of electromagnetic interference (EM I) caused by too many data lines with potential changes in the busbar is usually applied to the data output driving circuit to reduce the noise generated during data transmission. As shown in Fig. 1, it is a kind of conventional method that can reduce electromagnetic interference = transmission diagram. A transmitting end transmits a different value of each data bit% in a plurality of data periods to a receiving end 120 in order through a bus. The bus 100 includes data lines DLQ to DLn and a control line CL. Among them, the transmitting end 110 will selectively transmit a generation on the data line DLrDLn in each data cycle, and one of the original value of the data bit% ~ Dn or its complement signal to reduce the potential occurrence in each data cycle. Number of changing data lines f. In addition, in order to enable the receiving end 12 () to correctly obtain the value of the shell material bits DG ~ Dn from the data line DLq ~, the transmitting end 110 will trigger ( assert) the data inversion signal INV (on the control line CL), and in the data period in which the signal representing the original value is transmitted, the transmitting end 11 will de-assert the data inversion signal INV (on the control line CL) on). , ° ~. As shown in FIG. 2, it is a conventional low-noise data output driving circuit. This low-noise data output driving circuit is located at the transmission end 110 of FIG. 1 and is used to drive the output of the transmission end. data. In the figure, the D-type flip-flops 2 1 0G ~ 2 1 0n respectively receive the original value of data bitization ~ κ at the input end and send it to the output end after one data period, which means that at every data period In the input and output ends of the D-type flip-flops 21Q ~ 21n, the values of the material bits DQ ~ Dn in the current data cycle and the previous data cycle are respectively set. The input and output terminals of D-type flip-flop 21 〇Q ~ 21 0n are connected to mutually exclusive

12850twf.ptd Page 11 200540743 V. Description of the invention (3) Or gate 2 2 1G ~ 2 2 ln. Therefore, in each data cycle, if the value of any data bit D0 ~ Dn is different from the value in the previous data cycle, the exclusive OR gate 221G ~ 221n will trigger the relative data change signal CG ~ Cn; otherwise, the relative data change signal will be de-asserted. 〇The data inversion judgment circuit 2 30 will judge the value and the previous data cycle through the decoding logic based on the data change signal CG ~ Cn. Whether the number of data bits with a medium value is not greater than or below a preset number, and then respectively trigger (assert) or de-assert-a judgment signal J. When the judgment signal J is asserted and the data inversion signal INV of the previous data cycle is in an idle state (de-asserted), or the Hungarian break signal J is de-asserted and the data of the previous data cycle When the inversion signal INV is asserted, the data inversion signal generating circuit 260 will assert the data inversion signal INV; when the judgment signal J is asserted and the data inversion signal of the previous data cycle is asserted When INV is also in the de_asserted state, or the judgment signal j is de-asserted and the data inversion signal INV in the previous data period is also in the de-asserted state, the data inversion signal generating circuit 260 will idle the data inversion signal INv. The delay circuit 240 is used to enable the values of the data bits% ~ w in each data cycle and the relative data inversion signal INV to be transmitted to the data inversion circuit 250 simultaneously. Therefore, the delay circuit 240 is generally composed of a plurality of D-type flip-flops connected in series, and the number thereof corresponds to the delay time caused by the data inversion decision path 230.

200540743 V. Description of the invention (4) Finally, when the data inversion signal INV is idle or triggered, all the received values are directly transferred to the bus 1 0 0 or they are respectively transferred. The complement is output to the bus i 00. However, because the data inversion judgment circuit 230 is usually composed of many logic gates, the time delay caused by it will cause the delay circuit 2 40 to be composed of D-type flip-flops, which increases the circuit area. It can be reduced to drive the material. It can be reduced to drive the material inversion. In the first data change, there is an unexpected change with the reference circuit number and the material inversion value. The ratio of the potential of the second signal to the value of the digital signal is one of the choices of the first material to reverse a data signal. The method of the present invention can meet the needs of the fast path, and other purposes include data comparison circuits and reception in the data cycle. The data bits of this group of signals are compared with each other to generate a second period signal. Among them, the signal is reversed and selectively rotated out. The purpose is to quickly judge the lower crystal. Corresponds to the number. Material changes should be judged in the second capital. Each source provides a face-to-face supply and data circuit of the interrupted chip. The material level is inverse potential of the first data, the signal level is broken, the material level is reversed, the material level is reversed, and the low noise data inversion product is compared with the cost. Power and information. The data inverse data generation number is based on the data output signal in the second week according to the conversion circuit. Therefore, the data transmission circuit and the data circuit sequentially generate a set of material cycles in the middle of the cycle. According to the number in the second period

200540743 V. Description of the invention (5) The present invention further provides a method for driving low-noise data output, including the following steps: sequentially receiving the values of multiple data bits in the first and second cycles = generating a set of data change signals , This set of signals corresponds to the number of data bits with different values in the first and second data periods; according to the data change # said a relative data change potential is generated, and the data change potential is compared with a reference $ bit to generate a corresponding Judgment signal; generates a first and a second data reversal signal for each value of the i level in the first and second cycles. The first inversion f signal is based on the judgment signal and the first data reversal signal. Generate 'selectively outputs one of the value or the complement of each data bit in the second period according to the second data inversion signal. In order to make the above and other objects, features, and advantages of the present invention more obvious and easier to understand, the present invention will be described in detail with the preferred embodiments and the accompanying drawings as follows: It is a schematic diagram of a hybrid Λ shell material output driving circuit according to a preferred embodiment of the present invention. In the figure, the D-type flip-flop 3 i 00 times ^ receives the original values of the data bits D0 ~ Dn at the input end, and sends it to the output end after a period of two; The input of D-type flip-flop 31 〇G ~ 31 〇n and the second tone = 1 don't connect to the mutually exclusive OR gate 3 2 1q ~ 3 2 ln. Therefore, if the value of any one of the data bits Dq ~ Dn in each of the two oblique data is different from the value in the previous one, they are mutually exclusive OR gates 321 ~ 321. It will trigger 3 =) one of the 5 pairs of data change signals C0 ~ Cn; otherwise, the relative signal, t, will be deasserted. The conversion unit 3 3 1 in the two inversion judgment circuit 3 3 〇 will change the data

12850twf.ptd Page 14 200540743 V. Description of the invention (6) The signal CQ ~ Cn is changed to a corresponding data change potential v〇ut. The magnitude of the 'data change potential V 0 u t corresponds to the number of data change signals asserted. The comparison unit 332 compares the data change potential Vout with a reference potential Vref. When the data change potential Vout is greater than the reference potential Vref, the comparison unit 332 triggers the judgment signal J; otherwise, the judgment signal j is left idle. The data inversion generating circuit 360 is used to generate a data inversion signal j NV for the data bit value in each data cycle. Among them, when the judgment signal J is asserted and the data inversion #INV of the previous data cycle is de-asserted, or the judgment signal J is de-asserted and the previous data cycle When the data inversion signal INV is asserted, the data inversion signal generating circuit 36 0 will assert the data inversion signal INV; when the judgment signal j is asserted and the data in the previous data cycle is asserted When the inversion signal INV is also asserted, or when the judgment signal j is de-asserted and the data inversion signal of the previous data period 丨 NV is also in the de-asserted state, the data is inverted The rotation signal generating circuit 36 will idle the data inversion signal INV. The delay circuit 3 4 0 is used to enable the value of data bits ~ κ in each data cycle and the relative data inversion signal 丨 NV to be transmitted to the data inversion circuit 3 50 simultaneously. Therefore, the delay circuit 34 is generally composed of a plurality of D-type flip-flops connected in series, and the number thereof corresponds to the delay time caused by the data inversion judgment circuit 330. Finally, the data inversion circuit 350 will be idle at the data inversion signal INV

200540743 V. Description of the invention (7) or when triggering ’output all received values directly or output their complements respectively. Please refer to FIG. 4, which is a circuit diagram of the conversion unit mi in FIG. 3. The conversion unit 331 includes a load 4 30 (such as a resistor), a current source 41 OO ~ 410n, and a switch 420G ~ 4 20n. One ends of the switches 420Q ~ 420n are respectively coupled to the current source 4100 ~ 410n, and the other ends are commonly coupled to the load 43. Each switch 4200 ~ 4200n will be closed when its relative data change signal Cq ~ is triggered, and opened when it is idle. Since the number of data change signals in the trigger state is equal to the number of data bits that have undergone a value change, the data change potential Vout on the load 430 corresponds to the number of data bits that have undergone a value change. For example, when the current of the current source 410 () ~ 41011 is 21 and the size of the load 430 is 1 ?, the data change potential v0ut generated on the load 4 30 is equal to 2IxNxR. Among them, the value of N is between 0 and n + 1, and is equal to the number of data bits in which the value changes. That is, when there are a large number of data bits with different values in two consecutive data periods, the data change signals CG ~ Cn generated by the data comparison circuit 32 will cause more current to flow through the load 430. Please refer to FIG. 5, which is a circuit diagram of the comparison unit 332 in FIG. 3. The comparison unit 332 includes a comparator 510 and a reference potential generating circuit 520. The two ends of the comparator 510 respectively receive the data change potential and the reference potential Vref, so as to compare the data change potential Vout with the reference potential vref, and generate a judgment signal J. The reference potential generating circuit 52 0 outputs a reference potential V r e f. For example, when the aforementioned η is 2 3, that is, the data transmitted in one data period is 24 bits, the data change potential ν 〇 u t will be between 0 and 4 8 I R. Therefore, if you want to determine whether the number of data bits changed

12850twf.ptd Page 16 200540743 V. Description of the invention (8) If more than half (more than 12 bits), the reference potential Vref can be set between 2Ixl2xR and 2Ixl3xR (such as 25IR). Please refer to FIG. 6, which is the reference potential generating circuit 520 in FIG. 5. The current source 6100 ~ 61 (1 and the load 630 whose value is 1 ^. In this way, the reference potential generating circuit 52 can generate the reference potential Vref whose value is mxIxR. For example, the aforementioned reference potential is to be generated

When Vref = 25IR, the value of m is 25. As shown in FIG. 7, it is a data inversion signal generating circuit 360 in FIG. 3, which includes two d-type flip-flops 71, 720 and a mutex OR gate 730. The D-type flip-flops 71 and 72 use a clock signal CLk in common, and receive the judgment signal j and the output signal INV of the exclusive OR gate 730 respectively. Are the outputs of D-type flip-flops 710 and 720 connected to a mutex or a gate, respectively? Two of the three ingress. 'When the judgment signal J is "1" (trigger) and the data inversion signal I NV of the previous data cycle is "0" (idle), or the judgment signal j is "〇" (idle) and the data of the previous data period When the data inversion signal I NV is “1” (trigger) ^ The data inversion signal generating circuit 360 will output a data inversion signal INV whose value is r 1 ”(trigger); when the judgment signal J is“ 1 ”(trigger) ) And the data inversion signal I NV of the previous data cycle is also "1" (trigger), or the judgment signal J is "0" (idle) and the data inversion signal INV of the previous data cycle is also "〇" "" (Idle), the data inversion signal generating circuit 36 will output 0 to 0 and output a data inversion signal INV whose value is "0" (idle). In the above-mentioned embodiment, the data inversion judgment circuit 33 can generate a data inversion signal faster than a conventional circuit using decoding logic.

200540743 V. Description of the invention (9) INV, so it can reduce the number of D-type flip-flops that need to be connected in series in the delay circuit 340, and even remove the delay circuit 340, thereby reducing the circuit area and manufacturing cost. In addition, please refer to FIG. 8, FIG. 9, and FIG. 10. FIG. 8, FIG. 9, and FIG. 10 are metal oxide semiconductor (MOS) transistors to implement the actual circuits of FIG. 4, FIG. 5, and FIG. 6, respectively. Among them, the “current mirror” method is used to achieve the required current source, and the data change potential is generated.

Vref reference current source ref is the same current source. In addition, the reference potential generating circuit in FIG. 10 also adds the same switches as those in FIG. 8 below the current source, except that this switch has a β channel ^, s conversion unit has a comparison; 2 =: ”so that it can be The circuit matches and compares well with the circuit of Fig. 8-5. Although the present invention has a better life-span, followed by the descent of the road, the A bega case has been uncovered as above. The lack is not intended to limit the present invention. Anyone familiar with this The artist Ai Fei is used within the scope, and can be used as an excuse from the spirit of the present invention. The attached appendix suffices ^ changes and 'decoration'. Therefore, the scope of the protection of the present invention is defined by the patent scope 200540743 Brief description of the diagram Figure 1 is a diagram showing Xi Zhixi ’s intention. Ding ^ knows a kind of data transmission diagram that can reduce electromagnetic interference Figure 2 shows Xi Jiang σ > _ h a low noise data output drive circuit It is expected that the output of the driver system is as follows: a schematic diagram of a low noise output drive circuit according to a preferred embodiment of the present invention. FIG. 4 is a circuit diagram of a conversion unit according to a preferred embodiment of the present invention. Shows that according to the invention Comparative unit circuit of the example FIG. 6 shows a reference potential generating circuit according to a preferred embodiment of the present invention. FIG. 7 shows a circuit diagram of a data inversion signal generating circuit according to a preferred embodiment of the present invention. s) Transistor to implement the actual circuit of the conversion unit. Figure 9 shows the actual circuit using a metal oxide semiconductor (M0s) transistor to achieve the comparison unit. Figure 10 shows the application of a metal oxide semiconductor (M0s) transistor To realize the actual circuit of the reference potential generating circuit. [Schematic description:] 11 〇 Transmitting end 1 2 0 Receiving end 210 ～ 2lOn, 310 ～ 310n, 710, 72 0 D type flip-flop

12850twf.ptd Page 19 200540743 Brief description of drawings 22 1Q ~ 221n, 32 1G ~ 32 1n, 73 0 Mutual exclusion or gate 23 0, 33 0 Data inversion judgment circuit 24 0, 34 0 Delay circuit 2 5 0, 3 5 0 data inversion circuit 2 6 0, 3 6 0 data inversion signal generating circuit 3 2 0 data comparison circuit 331 conversion unit 3 3 2 comparison unit 41 0Q ~ 410n, 61 0. ~ 61 0m Current source 43 0, 63 0 Load 5 1 0 Comparator 520 Reference potential generation circuit

12850twf.ptd Page 20

Claims (1)

200540743 VI. Scope of patent application '---- 1 · A low-noise data output driving circuit, including: Data: :: ί: 4, sequentially receiving multiple beacon bits in a first and second cycle A set of data change signals are generated by the numerical values, and the pot material change signals correspond to the following: one is rough, the other is 丄 °, and the number of data m has different numbers in the period. A data inversion judging circuit, according to the relative data change of the set of data ... a relative judgment signal is generated by comparing the data change potential with U =; less> a data inversion signal generating circuit, which are the first The values of the data bits in a sum generate a first-time-one β / " eight middle w first shell material inversion signal is generated based on the judgment data inversion signal; and Gang Ying and the first One output? According to the second data inversion signal, the value of the two in the second cycle and the complement are selectively: 2. As described in item 丨 of the scope of patent application. Circuit, in which the data comparison circuit includes: a complex flip-flop driven by a singularity, and one of the data bits of each flip-flop is provided with the complex mutex or the gate at the first and the first, respectively; , Each mutually exclusive or heard = and one of the input first input data change signals respectively connected to one of the flip-flops. ^ ^ ′ And output these 3. The j-supply primary j circuit as described in item 1 of the scope of the patent application, wherein the data reversal judgment circuit includes a low-miscellaneous shellfish wheel driving a load; ^ 12850twf.ptd Page 21 200540743 A plurality of current sources; and a plurality of switches, each of which is coupled to the negative and the other end to one of the current sources, and the change signal selectively ^ executes the open relationships according to the data Change the potential. Only when the load is turned on and off, the 4th circuit of the scope of the patent application, such as the 3rd circuit in the patent application 4, where the low-noise lean output driver described in the test # 9 is lost, loses 1 (2) A reference current flows through a reference load and “Electrical > IL” is obtained by mapping to obtain one of the reference current source maps of the current sources. 5 · Low as described in item 4 of Shen Qing's patent scope Noise data output driving circuit 'The data inversion judgment circuit further includes a comparator, which receives the reference potential and the data change potential to generate the judgment signal. 6 ·-A method for driving low noise data output, including the following steps: A set of data change signals are generated by sequentially receiving values of a plurality of data bits in a first and second period, wherein the set of data change signals corresponds to data bits having different values in the first and second data periods A relative data change potential is generated according to the group of data change signals, and the data change potential is compared with a reference potential to generate a relative judgment signal; the first and second weeks respectively The values of the data bits in the period generate a first and a third data inversion signal, wherein the second data inversion signal is generated according to the judgment signal and the first data inversion signal; and according to the second Data inversion signal selectively outputs each data bit 200540743 VI. Scope of patent application One of the values and complements in the second cycle. 7. The low-noise data output driving method as described in item 6 of the scope of patent application, further comprising the following steps: providing a load and a plurality of current sources; and selectively changing each current according to one of the set of data change signals A source is coupled to the load, and the data change potential is generated on the load. 8. The low-noise data output driving method as described in item 7 of the scope of patent application, wherein the reference potential is generated by a reference current flowing through a reference load. 'The reference current is obtained by mapping from the current sources ^ A reference current source is derived. 12850twf.ptd Page 23