TW200530920A - Microcontroller instruction set - Google Patents

Abstract

A microcontroller apparatus is provided with an instruction set for manipulating the behavior of the microcontroller. The apparatus and system is provided that enables a linearized address space that makes modular emulation possible. Direct or indirect addressing is possible through register files or data memory. Special function registers, including the Program Counter (PC) and Working Register (W), are mapped in the data memory. An orthogonal (symmetrical) instruction set makes possible any operation on any register using any addressing mode. Consequently, two file registers to be used in some two operand instructions. This allows data to be moved directly between two registers without going through the W register. Thus, increasing performance and decreasing program memory usage.

Description

200530920 IX. Description of the invention: [Technical field to which the invention belongs] The present invention relates to a microcontroller, more specifically, the present invention relates to an operation code instruction that is assembled in an instruction set and used to control the behavior of the microcontroller. [Previous Technology] Microcontroller units (MCUs) have been used in the manufacturing and electronics industries for many years. Figure 1 shows a typical core memory bus configuration for a mid-range MCU device. In many cases, microcontrollers use reduced instruction set computing (RISC) microprocessors. The high performance of some of these devices can be attributed to several architectural features commonly found in RISC microprocessors. These characteristics include:

Harvard architecture long word instruction single word instruction single cycle instruction instruction pipeline operation streamlined instruction set register file structure orthogonal (symmetric) instruction Harvard architecture: As shown in Figure 2, Harvard architecture has program memory 26 and data memory 22, this The memory is separated from the memory system and can be accessed by the CPU 24 from a separate bus. This improves the bandwidth compared to the traditional von Neumann architecture (shown in Figure 3). In the von Neumann architecture, the CPU 34 uses the same bus to retrieve programs from the same memory 36. 96779.doc 200530920 ^ Bay In order to execute an instruction, a Von Neumann machine must pass through an 8-bit unit to access one or more (usually multiple) accesses to retrieve the instruction. Then i can retrieve, manipulate and possibly write the profile information. It can be seen from this description that the bus can become extremely crowded. Contrary to Xincong_machine, under the Harvard architecture, all 14 bits of the instruction are fetched in a single: order cycle. Therefore, under the framework, when the program memory is being accessed, the data memory system is in an independent [machine platoon] and can be read and written. These separate buses are not enough to fetch the next instruction while executing one instruction. Longword instruction: The instruction bus of the longword instruction is wider than the 8-bit data memory bus (the former has more bits). This feature is achieved because the two busbars are separate. This further makes the instruction size different from an 8-bit wide data word, which allows more efficient use of program memory because the width of program memory is optimized for architectural requirements. Single-word instructions: An early-word instruction opcode is 14 bits wide, so it can have all single-word instructions. A 14-bit wide program memory access bus can fetch a 14-bit instruction in a single cycle. If a single word command is used, the number of words in the program memory location is equal to the number of commands for the device. This means that all positions are valid instructions. Typically, in the von Neumann architecture (shown in Figure 3), most instructions are multi-bit groups. However, in general, a device with 4-byte program memory will allow approximately 2K instructions. This 2: 1 ratio is general and depends on the application code. Because each instruction uses multiple groups of 96779.doc 200530920, there is no guarantee that each position is a valid instruction. Instruction pipeline: This instruction pipeline is a secondary pipeline that overlaps the fetch and execution of instructions. The fetch of instructions consumes-machine cycle (rTCY), and the execution of instructions consumes another "TCY". However, since the extraction of the private order from ❿ 目 目 overlaps with the execution of the previous instruction, during each TCY period, one instruction is taken and another instruction is executed. 7 Single-cycle instruction: If the program memory bus is 14 bits wide, it can take the entire instruction in a single heart. The instruction contains all the required information and is executed in a single cycle. If the result of the instruction modifies the contents of the program counter, the execution may be delayed by one cycle. This requires and retrieves a new instruction. Rong streamlined instruction set: When an instruction set is carefully designed and requires fewer instructions to perform two :: ... parent (symmetric),, 丨, Japanese, and 必要, necessary tasks for the executive king. If there are fewer instructions, the entire instruction set can be learned faster. Temporary file file structure ··: The special function of addressing or registering the register broadcast / data memory temporarily or temporarily ^, there is. The program counter ’is mapped to data memory. Orthogonal (symmetric) instructions: /] γ I makes it possible to perform any operation on any temporary storage 3 | using any addressing mode. The nature of the skin is the same as the nature of the implementation of this "in addition to the" special instructions, 96779.doc 200530920 makes programming simple and efficient. In addition, the learning curve can be greatly simplified. Σ Xuanzhong only uses two Non-register-oriented instructions, which are used for two core features. One is the SLEEP instruction, which puts the device in the lowest power usage mode. The other is the CLRWDT instruction, which prevents the on-chip watchdog timer (WDT) ) Overflow and reset the device to ensure the correct operation of the chip. 0 clock scheme / instruction cycle:

The clock input (from 0scl) is internally divided into four to generate a non-overlapping quadruple sun pi pulse ', namely Ql, Q2, Q3, and Q4. Internally, increment the private 4 digits of $ (PC) at each ^ and fetch the instruction from program memory at q4 and store it in the instruction register. 纟 Decode and execute the instruction during subsequent Qi and Q4 . Figures 4 and 5 illustrate the clock and instruction execution flow. Instruction flow / pipeline operation ... "π" is composed of four Q cycles (Q1, Q2, q Q4) shown in Fig. 4, and these Q cycles include ay as shown in Figs. Should note

In ㈣5, except for any program branch, the program is executed in a single cycle; the y program is divided into W cycles, because "tear" is "cleared" from the pipeline, and new instructions are fetched and then executed. Fetching takes one instruction cycle, while station 1 t ^ and decoding and execution consumes another instruction J. However, due to pipeline operations, ground is performed. If an instruction: "is available in the-cycle ... to change the number of blades (such as _, it takes an extra cycle to complete ^ L (Figure 5). The instruction is retrieved from the program counter at Qlt is incremented. The fetch is also executed during the execution cycle. The instruction fetched in cycle 01 is latched into the "sniffing" (IR). Then, as in 96779.doc -10- 200530920 Q3 cycle This instruction is decoded and executed during the period. Read (calculate and write (destination write) data memory during Q2. Figure 5 ', "is not used for the operation of the secondary pipeline of the instruction sequence. At time TCY0, the traditional memory gymnastics fetches the first instruction. During Ding Yi, execute the first instruction to fetch the second instruction. During TCY2 'execute the second instruction and fetch the second instruction. During TCY3, fetch the fourth The instruction executes the third instruction (CALL SUB_1) at the same time. When the third instruction finishes executing, the address of the instruction four is forced into the heap g 'and then the program counter (pc) is changed to the address of the crime B ". This means that the pipeline needs to be removed "Clear" instructions during TCY3. During TCY4 ' Divide instruction four (executed as -Qing) and extract the instruction at address SUBJ. Finally, during Mach 5, execute instruction five and fetch the instruction at address SUB-1 + 1. Although the microcontroller of the prior art is useful , But can not simulate various modules. Moreover, the microcontroller type shown in Figure 1 cannot linearize the address space. Finally, the microcontrollers of the first 4 technologies are susceptible to compiler error problems. The need is A device, method and system for a microcontroller, which can linearize the address space in order to achieve modular simulation. There is also a need in the art to reduce compiler errors. [Summary of the Invention] The present invention provides a microcomputer Controller instruction set to overcome the above problems and other defects and shortcomings of the prior art, the microcontroller instruction set can eliminate many compiler errors encountered in the prior art. Moreover, a device and system are provided to implement a linearity Address space, which makes modular simulation possible. The invention can directly or indirectly address its register broadcast or data memory 96779.doc -11-200530920. All special functions Register, register 0v) maps data ^ ^ program counter (PC) and work scale) instruction set, which makes it possible to use any of the present invention with an orthogonal (any operation on the line. This symmetrical nature, :: The mode is executed on any register ", so that the shout design of the present invention not only has the" special optimization situation for writing software applications, but the learning effect is too great. In addition, the system can be greatly simplified and improved. The slot register can be used in some two consecutive TΓΓ 70 instructions. This makes: the ancestor can move directly between the two registers = does not have to go through the W register, thus improving performance, It also reduces the use of memory of program 3. The preferred embodiment of the present invention includes an ALU / W register, a PLA 8-bit multiplier, and a program counter (ρ with stacking). ), A table latch / table index, —ROM latch / ir latch $, fsr, interrupt directional circuit, and the most common status register. Different from the prior art, the design of the present invention does not need—the timer in a separate module, all the reset generating circuits (Nadine, Cancel, Tender, etc.), + break flag, actuation flag, CON register , RC⑽ register, configuration bit, device⑴ character, ID position and clock driver. Those skilled in the art will appreciate additional specific embodiments after referring to the detailed description and drawings. [Embodiment] The present invention is a device, method, and system for providing a microcontroller instruction set and a microcontroller architecture in several specific embodiments. The microcontroller architecture includes a linearized address space. It can realize modular simulation. 96779.doc -12- 200530920 The device architecture of the preferred embodiment of the present invention modifies the Harvard architecture of the prior art with a four-phase internal clock scheme so that the data path is 8 bits and the instruction length is 16 bits. Moreover, the preferred embodiment has a linearized memory addressing scheme, which eliminates the need for paging and fetching. This month. The hidden addressing scheme allows program memory addressing capabilities up to bytes. The invention also supports the simulation of modules. The present invention overcomes the above problems and other shortcomings and deficiencies of the prior art by providing a microcontroller instruction set, which can eliminate many compiler errors encountered in the prior art. Moreover, a device and system are provided to implement a linearized address space, which makes modular simulation possible. The invention can directly or indirectly address its register file or data memory. All special function registers, including program counter (pc) and work register (W), are mapped in the data memory. The present invention has an orthogonal (symmetric) instruction set that enables any operation to be performed on any register using any addressing mode. This symmetrical nature, coupled with the absence of a "special best case", makes the programming of the present invention simple and efficient. In addition, the learning curve can be greatly simplified. One of a series of architectural improvements of the present invention over the prior art 'allows two file registers to be used in certain binary operand instructions. This allows data to be moved directly between the two registers without having to pass through the W register ', thus improving performance and reducing program memory usage. FIG. 6 shows a block diagram of the microcontroller core of the present invention. Figure 6 illustrates the microcontroller core of the present invention. According to common practice, the connection signal line in FIG. 6 may include a slash, and the number next to the slash indicates the bandwidth (in bits) of the （旒 line. Referring to the upper right corner of Figure 6, there is a data 96779.doc • 13-200530920 memory 104, which is used to store data and transmit data to a central processing unit (described below) and transmit data from the central processing unit. The data memory purchase is made up of ― plural residual locations. In a preferred embodiment of the present invention, the lean memory 104 is a linearized 4K memory, which is divided into a plurality of sections, each of which has sixteen pages or repositories. Typically, each repository has 256 address locations. In the preferred embodiment, one of the plurality of storage orders is dedicated to general purpose and special purpose registers, in this case the highest storage level, namely storage level 0. A selection circuit 108 is coupled to the data memory H via an address latch 102. The selection circuit is used to select one of a plurality of sources for supplying a bank address value to the data memory 104. The preferred embodiment of the present invention includes an ALUU0 and a working (w) temporary storage σσ 136, a PLA, an 8-bit multiplier; a program counter (pc) 168 and a heap: £ 170,-table latch 124; table index 148; — ROM latch 152 and IR latch 126 FSH120, 121, 122; interrupt orientation circuit and the most common status register. Different from the prior art, the design of the present invention requires not only a timer in a separate module, all reset generating circuits (WDT, POR, BOR, etc.), interrupt flags, activation flags, intc 〇n register, RCON register, configuration bit, device ID character, ID position and clock driver. I / O list: A large list of input / output (I / O) commands can be obtained by using the present invention, and the I / O list is shown in Table i. 96779.doc • 14- 200530920 Table 1 I / O List Name Count I / O Normal Operation Operation Test Module Program Module Simulation Module addr < 21: 0 > 22/0 Program Memory Address nqbank < 3: 0 > 4 / 0 Active low RAM bank selection d &15; 15: 0 > 16/1 program memory data db < 7: 0 > 8/1/0 data bus forcext 1/1 forced external command test mode irp < 7: 0 > 8/0 peripheral address irp9 I / O instruction register bit 9 ncodeprt 1/1 active low code protection neprtim 1/1 active low EPROM write end nhalt 1/1 active low pause nintake 1/1 active low interrupt confirmation Wake up early and from sleep np < 7: 0 > 8/0 Table latch data npcmux I / O activity low PC multiplexing npchold I / O activity low PC hold nprtchg 1/1 activity low port change interrupt nq4clrwdt I / O Active low clear wdt nq4sleep I / O Active low sleep nqrd I / O Active low read file nreset 1/1 Active low reset nwrf I / O Active low write file ql: q4 4/1 4-phase Q clock ql3 1 / 1 Q clock combination q23 1/1 Q Pulse combination q41 1/1 Q clock combination testO 1/1 Test mode 0 tsthvdet 1/1 High voltage detection wreprom I / O Stomach eprom writem I / O write to memory wrtbl I / O table write command nintakd 1/1 interrupt confirmation delay intak 1/1 interrupt confirmation 96779.doc -15- 200530920 The clock scheme / instruction cycle is shown in Figure 7. The clock input (from 0scl) is divided into four internally to generate Non-overlapping quadruple clocks, namely Q2 Q2, Q3 and Q4. Internally, the program counter 递增 is incremented every = Qi, and Q4 is used to fetch the instruction from the program memory? Asia latches it into the instruction temporary storage 11. Remove obstacles and follow = instructions during subsequent Q1 divisions. PLA decoding is done in between. During the master cycle ', operands are read from memory or peripheral elements and the ALU performs calculations. Time ’will write the result to the destination location. Figure 8 illustrates the clock and instruction execution flow.

Q cycle activity As shown in FIG. 7, each instruction cycle (TCY) is composed of four Q cycles (from Q to Q) into A. The Q cycle is the same as the device oscillator cycle (Tsc). == Decode, read, process data, write, etc. of the instruction cycle: 疋 The following figure (Figure 7) shows the relationship between the Q cycle and the instruction cycle. The four Q cycles that make up the instruction execution cycle (TCY) can be generalized into:

Q1: Instruction decode cycle or forced NOP Q2 • Instruction read cycle or NOP Q3: Processing data 4 • Instruction write cycle or Nop Each instruction will show the detailed Q cycle operation of the instruction. The instruction flow / pipeline operation, private order cycle "is composed of four Q cycles (Ql, Q2, (^ 3, and 卩 4). The fetch and execution system is pipelined, so that fetch consumes-instruction cycle to decode It takes another instruction cycle to execute. "Because the pipeline operates 96779.doc -16- 200530920, each instruction is effectively executed in a cycle. There are four types of instruction flows. The first type is a 1-child 701 cycle pipeline that is being suspended. Instructions. As shown in Figure 9, 'these instructions will be executed with a one-cycle effect. The second type is the i-character 2-cycle pipeline clearing instructions.' Μ 私 7 includes relative branches, relative calls, skips and Back. When an instruction changes the PC, the pipeline is discarded. As shown in Figure 10, this makes the instruction _ two valid cycles to execute. The third type is a table operation instruction: these instructions will be suspended # | Insert and read or write cycles to program memory. The instructions relied upon when performing table operations are guaranteed ... cycles, and are executed in the next cycle after the table operations, as shown in Figure u. The fourth type is new Two-word instructions. These instructions include MOVFF and M0 VLF. In these two, ': Take the remainder containing these addresses. For the MOVFF during the "hit-word το", the machine will perform a read of the source register. During the execution of the second character, the source address is obtained, and the The instruction will = become this move 'as shown in Figure 12. M0VLF is similar, but it moves two text values in two cycles to enter, as shown in Figure η. The fifth' is a two-word instruction of CALL and GOTO. In these instructions, the fetch after ^ contains the remainder of the jump or call destination address. In the second case, the instructions such as Λ will take 3 cycles to execute, and the instructions are used to fetch these 2 instruction characters. In addition, one is used for subsequent pipeline clearing. However, by providing a high-speed path during the second fetch, the PC can be updated with a complete value in the first cycle of instruction execution, thereby obtaining a 2-cycle instruction , As shown in Figure 14. Sixth, system, interrupt identification execution. The instruction cycle during the interrupt is discussed in the interrupt section below. 96779.doc -17- 200530920

ALU The present invention includes an 8-bit arithmetic and logic unit (ALU) 142 and a work register 136, as shown in FIG. ALU 142 is a general arithmetic unit. It performs arithmetic and Boolean functions between the data in the register and any register files. The ALU 142 is 8 bits wide and is capable of performing addition, subtraction, shift, and logical operations. Unless otherwise mentioned, arithmetic operations are two's complement nature. The work (W) register 136 is an 8-bit work register for ALU 140 operation. The W register 136 is addressable and can be directly written or read. The ALU 140 is capable of performing arithmetic or logical operations on two operands or a single operand. All single operation meta instructions operate on the W register 136 or the predetermined file register. For the instructions of two operands, one of them is W register 136, and the other is a file register or an 8-bit immediate constant, or an equivalent storage medium. Depending on the instruction executed, ALU 140 can affect the values of Carry (C), Digital Carry (DC), Zero (Z), Overflow (OV), and Negative (N) bits in the STATUS register (described below). The C and DC bits are used as a borrow and a digital borrow bit respectively in subtraction. A preferred embodiment of the present invention includes an 8x8 hardware multiplier 134, which is included in the ALU 142 of the apparatus shown in FIG. By making multiplication a hardware operation, the operation can be completed in a single instruction cycle. This hardware operation gives an unsigned multiplication of a 16-bit result. The result is stored in a 16-bit product register (PRODHiPRODL). The multiplier does not affect any flags in the STATUS register. Status register 96779.doc -18- 200530920, the side register contains the status bit of ALU 14〇. Figure i5 shows the state of temporary storage & In the preferred embodiment of the present invention, bit M is not implemented and is read as 0 '. Position 4 is N ″ ', which means negative position. This bit is used for signed arithmetic (2's complement). It indicates whether the result is negative, (ALUMSbO, 1 = negative result, 0 = positive result. Bit TC3 is 0V ”± overflow bit. This bit is used for signed arithmetic (2's complement) . It indicates a 7-bit size overflow that causes the sign bit (bit 7) to change ㈣. For this bit, 'signed arithmetic overflows (in this arithmetic operation), and 0 = no overflow Occurs. Bit 2 is the zero bit. For this bit, the result of the arithmetic or logical operation is zero, and 0 = the result of the arithmetic or logical operation is non-zero. Bit 1 is the "DC" digital carry / borrow Bit bit. For this bit, a carry output of the π order shirt bit occurs and no carry output of the 7th order bit of the result. It should be noted that for borrowing, the polarity can be reversed. Bit 0 is the "C" carry / borrow bit. For this bit, 1 = the most significant bit of the result has a carry out, and 0 = the most significant bit of the result has no carry out. Same as bit 丨For borrowing, the polarity can be reversed. C and DC bits are used as a borrow and digital borrow bit respectively in subtraction. Carry is the ALU bit 7 carry output. Digital carry is the ALU bit 3 carry output. If the ALU result bit < 7: 〇 > is 0, then the zero bit is true. The result bit is 7. If 2 If the result of the complement is more than + 127 or less than _128, the overflow bit is set to 96779.doc -19- 200530920. The overflow is the XOR operation of the ALU bit 6 carry output and the ALU bit 7 carry output. Like the register, the STATUS register can be the destination of any instruction. If the STATUS register is the write destination of an instruction that affects any status bit, the write to the status bit is disabled. According to ALU The result and instruction specifications set or clear these bits. Therefore, the result of the instruction using the STATUS register as the destination may not be as expected. For example, the CLRF REG instruction generally writes this register to 0 and sets Z bit. The CLRF STATUS instruction will disable writing to the N, OV, DC, and C bits and set the Z bit. This makes the STATUS register 〇〇〇u uluu. Therefore, it is recommended to use only BCF , BSF, SWAPF and MOVWF instructions to change the STATUS register, because these instructions will not Affects any status bit. To learn how other instructions affect these status bits, see "Instruction Set Overview". The Program Counter module modifies the Program Counter (PC) 168 (see Figure 6) to allow expansion to the maximum 21 bits. This is accomplished by adding a 5-bit wide PCLATU register, which operates similarly to the PCLATH register. PC 168 is also modified to address the bits in program memory and Not a word. To implement this, there must be a byte at the LSb of PC 168. The addressing bit is always 0. The LSb bit of pcl is readable but not writable. If the user attempts to write LSb ', the result will be' 0 '. To allow the hidden test EPROM, the PC 168 needs a hidden bit 22 (bit 21) (see Figure 16). This PC bit is normally 0. When entering test mode or programming mode, set this 96779.doc -20- 200530920 bit, and retrieve these instructions from the test area. Once this bit is set, it cannot be cleared by running the program and the device must be reset. The program counter (PC) 168 is up to a 21-bit register as shown in FIG. The PCL 184, that is, the lower byte of the PC 168, is mapped into the data memory 104 (see FIG. 6). PCL 184 is readable and writable, just like any other register. PCH 182 and PCU 180 are the high byte of PC, and cannot be directly addressed. Because PCH 182 and PCU 184 are not mapped into data or program memory 160, the temporary registers PCLATH 178 (PC High Latch) and PCLATU 176 (PC Upper Latch) are used as the high byte of PC 168 It keeps the latch. PCLATH 178 and PCLATU 176 are mapped into data memory 104. Users can read and write PCH 182 via PCLATH 178 and PCU 180 via PCLATU 176. Each time the instruction is fetched during Q1, the word of PC 168 is incremented by 2 unless: • Modified by a GOTO, CALL, RETURN, RETLW, RETFIE, or Branch instruction. • Modified by interrupt response. • Write to destination of PCL 168 due to an instruction. "Skip" is equivalent to a forced NOP cycle at one of the skipped addresses. Figures 16 and 17 show the operation of the program counter in various cases. Referring to FIG. 16, the operations of the PC 168, PCLATH 178, and PCLATU 176 of the different instructions are as follows: a. Read instruction for PCL: For any instruction to read PCL 184. All byte instructions with d = 0; 96779.doc -21-200530920 MOVFF PCL? X; CPFSEQ; CPFSGT; CPFSLT; MULWF; TSTFSZ then PCL to the data bus and then to ALU or to the destination. Finally, PCH to PCLATH and PCU to PCLATU. b · PCL write instruction: Write any instruction to PCL 184. For example, MOVWF; CLRF; SETF, and then write 8-bit data to the data bus 174, and then to the PCL 184. Also, PCLATH to PCH and PCLATU to PCU. c. Read-modify-write instructions for PCL: Any instruction for read-write-modify operations on PCL. d = l all byte instructions; bit instructions; NEGF. Read: PCL to data bus to ALU. Write: Write the 8-bit result to the data bus and to PCL, then PCLATH to PCH; finally PCLATU to PCU. Read-modify-write affects PCL 184 only as a result. Load the values in PCLATH 178 and PCLATU 176 into PCH 182 and PCU 180, respectively. For example, for the instruction "ADDWF", PCL 184 will cause the following jump. If PC = 0003FOh, W = 30h, PCLATH = 05h, and PCLATU = lh before the instruction, then PC = 010520h after the instruction. In order to complete a real 20-bit calculation jump, the user needs to calculate the 20-bit destination address, write it to PCLATH 178 and PCLATU 176, and then write the low value to PCL 168. d. RETURN instruction: Use Figure 17 to stack < MRU > to PC < 20: 0 >, the operations of PC 168, PCLATH 178, and PCLATU 176 of GOTO and CALL instructions are as follows: e. CALL, GOTO instruction: In 2-word instruction (Opcode) Provide a destination address. First word opcodes 96779.doc -22- 200530920 < 6: 0> to PCL < 7: 1 >. The first word operation codes < 7 > to pcLATH < 0> and to PCH < 0 >. The second word opcodes < 6: 〇 > to PCLATH < 7: 1 > and PCH < 7: 1>. Second word opcodes < 11: 7 > to PCLaTU < 4: 0 > and PCU < 4: 0 > 〇 It should be noted that the following operations related to PC 168 will not change PCLATH 178 and PCLATU 176: a. RETLW, RETURN and RETFIE instructions. b. Force the interrupt vector to the PC. c. PCL read-modify-write instructions (eg BSF PCL, 2). Back stack operation The present invention has a 31-layer deep back (or hardware) stack. The depth of the stack is increased relative to the prior art to allow more complex programs. The stack is not part of the program or data memory space. When a CALL or RC ALL instruction is executed or an interrupt is acknowledged, the PC 168 is pushed onto the stack. When a RETURN, RETLW, or RETFIE instruction is executed, the PC 168 value is pulled from the stack. PCLATU 176 and PCLATH 178 are not affected by any return instruction. This stack is used as a 31-character x 21-bit RAM and a 5-bit stack pointer, and the stack pointer is initialized to 0000b after all resets. There is no RAM word associated with the stack index 000h. This is only a reset value. A CALL-type instruction causes the stack index to be incremented during the push into the stack, and the contents of the PC are written to the RAM location pointed to by the stack index. A RETURN instruction causes the contents of the RAM location pointed to by STKPTR to be transferred to the PC during the fetch from the stack, and then the stack index is decremented. 96779.doc -23- 200530920 Stack top access The top of the stack is readable and writable. Three register locations TOSU, TOSH, and TOSL address the stack RAM locations pointed to by STKPTR. This allows the user to implement a software stack if necessary. After a CALL or RCALL instruction or an interrupt, the software can read the pushed values by reading the TOSU, TOSH, and TOSL registers. This value can be placed on a user-defined software stack. When returning, the software can replace T0SU, TOSH and TOSL and perform a return. It should be noted that during this time, the user must disable the global interrupt actuation bit to prevent inadvertent stack operations. PUSH and POP instructions Because the top of the stack (T0S) is readable and writable, the ability to push values onto the stack and pull values from the stack without disturbing normal program execution is an ideal choice . To push the current PC value onto the stack, a PUSH instruction can be executed. This pushes the current PC value onto the stack; set TOS = PC and PC = PC + 2. The ability to pull the TOS value from the stack and replace it with the value previously pushed onto the stack without disturbing normal execution is achieved by using the POP instruction. The POP instruction pulls the TOS value from the stack, but this value is not written to the PC; the previous value pushed onto the stack becomes the TOS value. Return Stack Index (STKPTR) The STKPTR register contains return stack index values and overflow and underflow bits. Stack overflow bit (STK0VF) and underflow bit (STKUNF) allow software to verify stack conditions. Only clear STKOVF and 96779.doc after resetting the POR. • 24-200530920 STKUNF bit. After pushing the PC to the stack 31 times (without pulling any value from the stack), the 32nd push overwrites the value from the 31st push and sets the STK-OVF bit, and the STKPTR It stays at 11111b. The 33rd push overwrites the 32nd push (and so on), while 3! ^? Ding 11 remains at 111111). After the stack is taken out many times to unload the stack, the next removal will return a zero value to the PC and set the STKUNF bit while keeping the STKPTR at 00000b. The next fetch returns again to zero (and so on) while keeping STKPTR at 00000b. It should be noted that returning a zero to the PC in the case of an underflow has the effect of orienting the program to the reset vector, where the stacking conditions can be verified and appropriate actions taken. Stack indicators can be accessed via the STKPTR register. Users can read and write the stack index value. RTOS can use this value for return stack maintenance. Figure 18 shows the STKPTR register. The value of the stack index will be 0 to 31. When reset, the stacking index value will be 0. The stacking indicator will increase when pushing in, and decrease when removing. Stack Overflow / Underflow Reset According to the user's selection, overflow and underflow can reset the interrupt code of a device. A configuration bit STVRE is used to activate the reset. When the STVRE bit is disabled, the overflow or underflow will set the appropriate STKOVF or STKUNF bit without causing a reset. When the STVRE bit is actuated, the 'overflow or underflow' will set the appropriate STKOVF or STKUNF bit, and then reset the nature of a device very similar to WDT reset. In either case, the STK0VF or STKUNF bits are not cleared unless they are cleared by user software or a POR reset. Figure 18 96779.doc -25- 200530920 to 21 illustrates the stack register. Illustration. So to explain the stacking operation. Program memory 鳢 A preferred embodiment of the present invention has up to 2 million bytes (2M) x 8 user program memory space. The program memory space mainly contains instructions for execution. Table read and write instructions can be used to store and access data tables. There is another-test 8 memory space for testing ROM, configuration bits and identification characters. The device has a program counter up to 21 bits, which can address 2MX8 program memory space. And—the 22% bit, which is 'hidden' during normal operation, and when it is set, can access the configuration bit, device ID, and ROM. This bit can be set in test mode or programming mode, and the device must be reset to clear this bit. With this bit set, user program memory space cannot be accessed. Because the pc must access instructions on the boundary of the even-numbered S group in program memory, the Lsb of the pc is an implied, 0, and for every instruction, the pc is incremented by two. The reset vector is 000000h, and the high-priority interrupt vector is 000008h, and the low-priority interrupt vector is 0000i8h (see FIG. 30). Program Memory Organization Each location in program memory has a one-byte address. In addition, every 2 adjacent bytes have a -word address. Figure 31 shows the mapping of program memory with the indicated bytes and 2 addresses. In program memory, the words of these instructions must be aligned. Figure 32 shows the mapping of the program memory with several exemplary instructions and the hexadecimal codes placed in the mapping for those instructions. Table operations will work with byte entities. The table block does not need to be aligned 96779.doc -26- 200530920 so the table block can start and end at any byte address. The exception to this is the case of using table writes to program internal program memory or external :: Yuankuan flash memory. When stylized, you may need to align the writing material with the character width used by the stylized method. Program memory mode The present invention can be operated by five types of program memory—the configuration bit selects the configuration. Possible modes are: • MP-Microprocessor • EMC-Expansion Microcontroller • PEMC-Protected Expansion Microcontroller • MC-Microcontroller • PMC-Protected Microcontroller Microcontroller and Protected Microcontroller The controller mode allows only execution. Any access outside the program = memory reads all zeros. Protected microcontroller mode also activates the code protection feature. Microcontroller system—default mode for unprogrammed devices. Extended Microcontroller mode to access internal program memory and external program memory. Performs automatic switching between internal and external memory. The 21-bit address allows 2M bytes of program memory range. The protected extended microcontroller mode will code protect the internal program memory by preventing table read / write from internal memory while still allowing execution and table read / write from external program memory. This microprocessor mode only accesses external program memory. Ignore the on-chip format. The hidden 21-bit address allows the program memory of bytes to be in the range 96779.doc -27- 200530920. During normal operation of the device, test memory and configuration bits can be read by using TBLRD instructions. If the LWRT bit in the RCON register is set or the device is in test and programming mode, these areas can only be modified using the TBLWT instruction. You can only run from these areas in test and programming mode. The extended microcontroller mode and microprocessor mode are only available on devices with external memory buses that are defined as part of the I / O header. Table 2 lists the modes that can access internal and external memory. Figure 33 illustrates device memory mapping in different program modes. Figure 2 Device Mode Memory Access Operation Mode Internal Program Memory External Program Memory Microprocessor No Access Execution / TBLRD / TBLWT Extended Microcontroller Execution / TBLRD / TBLWT Execution / TBLRD / TBLWT Text Protection Expansion Microcontroller Port &Quot; " ------— Run / TBLRD / TBLWT AfUf port — ^ t / TBLRD / TBLWT No access protection micro-controller SJatblrd No access to external program memory interface Tin I U processing In the controller or expansion micro-controller mode, a maximum of four port groups can be used as the system and sink. Part of the two ports and the third port are multiplexed address / data buses, and part of the other port is used for control signals. Requires external components, Yang Nixian, Xianxi site and information. The external memory interface can be operated in 8-bit or 70-bit mode or 16-bit data mode. The addresses on the external memory interface are always byte addresses. Figures 36 and 37 illustrate the external memory connections of 16-bit and 8-bit data, respectively. The external program memory bus shares the 1/0 port function on the header. Figure 38 shows a typical mapping of the external bus function on the I / O header function. In Extended Microcontroller mode, when the device is executed outside the internal memory, these control numbers will not be active. It will enter a state where 1 $, eight < 19: 〇 > are tri-state; UBA0 and ALE are "〇". 16-bit external interface If the external interface is 16-bit, these will be captured as 16-bit characters. The output activation signal will actuate two types of program memory at one time and output 16-bit sub-bits. yuan. It is not necessary to connect the least significant bit of the address ΒΑ0 to the memory device. An external table read is performed logically one byte at a time, although the memory will read a 16-bit character from the outside. The least significant bit of this position will be selected internally between high and low bytes (LSb = 0 to lower bytes, Lsb = 丨 to higher bytes). The outer 4 addresses in the microprocessor and extended microcontroller modes are 21 bits wide; this allows addressing up to 2M bytes. An external table write on a 16-bit bus is performed logically one 7L group at a time. The actual writing will depend on the type of external device connected and the WM < 1: 0 > bits in the MEMCON register, as shown in Figure 34. The table operation section details the actual write cycle. 8-bit external interface If the external interface is 8-bit, 4th order deduction will be retrieved as 2 8-bit bytes. Fetch two bytes in one instruction cycle. It is not necessary to connect the least significant bit of the address to the memory device. The 0E output activation signal and 96779.doc -29- 200530920 BA ^ 1 will be activated at the q3 part of the cycle to read the most significant byte of the instruction from the program memory, and then in the Q4 part of the cycle, βΑ〇. Will become 0 and Asia will read the least significant byte to form a 16-bit instruction character. The master / nephew form is also executed one tuple at a time. An external form is written to the system to execute a tuple. WRL is active at every external write. When the 8-bit interface is selected, WRH, 118, and 1; 1 ^ lines are not used, and 妾 and 返回 return to the I / O port function. A configuration bit selects the 8-bit mode of the external interface. External wait period. The Haiwai 邛 σ self-memory interface supports wait cycles. The external memory waiting period is only applicable to table read and table write operations through the external bus. Because the execution of the device is related to the fetching of instructions, it does not make sense to execute faster than the rate of operation. Therefore, if program fetching needs to be slowed down, the processor speed must be slowed down at a different TCY time. The τ < 1: 〇 > bit in the MEMCON register will select 0, 丨, 2 or 3 additional TCY cycles in each record fetch cycle. For table reads and writes on a 16-bit 70 interface, these wait cycles will be valid. On the 8-bit " surface, for table reads and writes, the wait will only occur on Q4. The default setting for waiting at power-on is to wait for a maximum of 3 TCY cycles. This ensures that slow memory can work in microprocessor mode immediately after reset. A configuration bit, called WAIT, will activate or deactivate wait states. Figure 39 illustrates the 16-bit interface, and Figure 40 illustrates the 8-bit interface. In both cases, the status of 96779.doc -30- 200530920 shows the retrieval of program memory instructions without waiting and table reading with waiting status. . External bus signal deactivation In order to flexibly utilize the pins submitted to the external bus, several deactivations are provided in the configuration bit. To disable the entire external bus, as may be done in the extended microcontroller mode, and to allow a DMA function, configure the EBDIS bit in the MEM-CON register as shown in Figure 35. This deactivation will allow tristate of the entire external bus interface. This will allow DMA operation and direct control of external devices through program control via the I / O header function. In the simulator system, the -ME device must have an input for indicating the bus stop configuration bit, so that the I / O port function can detect the status of the pin as an external interface. The -ME device also has a special input pin that indicates whether the simulator system is in microprocessor or expansion microcontroller mode. Data Memory In the present invention, the data memory and general-purpose RAM size can be expanded to 4096 bytes. The data memory address is 12 bits wide. The data memory is divided into 16 repositories, each of which has 256 bytes. These repositories include a general purpose register (GPR) and a special function register (SFR). The GPR is mechanized into a one-byte wide RAM array with the size equivalent to a combined GPR register. SFRs are usually allocated between peripheral elements whose functions are controlled by the SFR. The bank is selected by a bank selection register (BSR < 3: 0 >). The BSR register may access more than 16 repositories, but the direct long addressing mode 96779.doc -31-200530920 is limited to 12-bit addresses or 16 repositories. BSR is restricted accordingly. Memory mapping device instructions can read, modify, and write to a specific location in an instruction cycle. Only one address is generated per cycle, & it is not possible to read one location and modify / write to another location in a single cycle. Figure 42 illustrates an exemplary data register. Universal Registers In all PIC devices, all data RAMs are used as registers by all instructions. Most data memory repositories contain only GPR memory. All 1 banks must include GPR memory. The absolute minimum number of GPRs in Repository 0 is 128. This GpR area, called access RAM, is necessary so that the programmer can have a data structure that can be accessed regardless of the settings of the computer. Special function register SFR is a special register, which is usually used for device and peripheral control and status functions. All registers can access these registers. If possible, all SFRs should be contained in the 128-byte upper byte of bank b. If SFR does not use all available locations on a particular device, unused locations are not implemented and read as 0. Some devices, such as the LCD controller, may have SIR areas in banks other than the bank 15. The boundaries of the SFR in the repository 15 may be modified for different devices. The access repository must include at least 16 GPRs. Figure 43 shows a possible special function register mapping. Figures 44 and 45 show an overview of the core special function registers. Addressing mode 96779.doc • 32- 200530920 The invention supports 7 data addressing modes: • inherent • text • direct short • direct coercion • direct long • indirect • index indirectly offsets its three modes, namely direct coercion and direct length A new model of the PIC architecture with indirect indexing. Inherent For some instructions, such as DAW, no addressing is required other than the addressing explicitly defined in the opcode. Text The text instruction contains a literal constant block, which is usually used for a mathematical operation, such as ADDLW. Text addressing is also used for GOTO, CALL, and branch opcodes. Direct Short Most math and move instructions operate in direct short addressing mode. In this addressing mode, the instruction contains eight bits of the least significant address of the data. The remaining four bits of the address are from the bank select register or BSR. The BSR is used to switch between repositories in the data memory area (see Figure 47). The need for large-capacity general-purpose memory space indicates a general-purpose RAM sub-library scheme. The lower half of the BSR selects the currently active general-purpose RAM to store the 96779.doc -33- 200530920 library. To assist with this instruction. A m0Vlb repository has been provided in the Caiyu Collection. The enemy will not apply the currently selected repository (for example, repository 13). Any read will win all of them. Anyone who writes A f π ㈣, and sighs and removes the STATUS register bit according to the situation. Directly force the special function register (sfr) of the character to be mapped into the data memory space. In order to / conveniently access the SFR, generally map it all into the storage bank 15. In order to interleave access, there is a meta block in the instruction, which points the address to the lower half of the general-purpose RAM repository 0 and the upper part of Shu's repository, regardless of the contents of the BSR. The job is set to · = η, so the 3 banks can be addressed by any instruction, that is, the banks 0 and 15 in the direct force mode and the bank "n" in the direct short mode. Direct Length Direct Addressing encodes all twelve bits of a data address into the instruction. This mode is used only by the MOVFF instruction. 'Day Indirect Addressing Indirect addressing is a mode of addressing data memory, where the address of the data memory in the instruction is determined by another-a register. This may be useful for data tables or stacks in data memory. Figure 53 shows the operation of indirect addressing. The value of the FSR register is used as the data memory address. Indirect Addressing Registers The present invention has three 12-bit registers for indirect addressing. These temporary

Eg: Said · σσ · 96779.doc -34- 200530920

• FSR0H and FSROL

• FSR1H and FSR1L

• FSR2H and FSR2L FSR are 12-bit registers and allow addressing anywhere in the 4096-byte data memory address range. In addition, there are register INDF0, INDF1, and INDF2 that are not physically implemented. Reading or writing to these registers can initiate indirect addressing, where the corresponding value in the FSR register is the address of the data. If the file INDF0 (or INDF1, 2) itself is read indirectly via the FSR, all '0' (set zero bits) are read. Similarly, if INDF0 (or INDF1, 2) is written indirectly, the operation will be equivalent to NOP, and the STATUS bit will not be affected. Indirect Addressing Operations Each INDF register has four addresses associated with it. When data access to one of the four INDF locations is complete, the selected address configures the FSR register as: • Automatically decrement the value (address) in the FSR (post-decrement) after indirect access. • The value (address) in the FSR is automatically incremented after indirect access (post-increment). • Automatically increment the value (address) (pre-increment) in the FSR before indirect access. • The value (address) in the FSR is not changed after indirect access (no change). When using the auto-increment or auto-decrement feature, the effect on FSR will not be reflected in the STATUS register. For example, if indirect addressing makes FSR equal to f0 ', the Z bit will not be set. Adding these features allows FSR to be used for stacked indicators in addition to data table operations. Index Indirect Addressing 96779.doc -35- 200530920 Each INDF has an address associated with it, which performs indirect access to an index. When data access to this INDF location occurs, configure the FSR to: • Before indirect access, add the signed value in the W register and the value in the FSR to form the address. • Do not change the FSR value. Indirect addressing (INDF) register indirect write If the FSR register contains a value that points to one of the indirect registers (FEFh-FEBh, FE7h-FE3h, FDFh-FDBh), an indirect read will Read 00h (set the zero bit), and an indirect write will be equivalent to a NOP (STATUS bit is not affected). Index (FSR) register indirect write If an indirect addressing operation is completed, where the target address is an FSRnH or FSRnL register, the write operation will dominate the pre-increment / decrement or post-increment / decrement functions. For example: FSR0 = FE8h (one less than FSR0L position) W = 50h MOVWF * (++ FSR0); (PREINCO) Increment FSR0 by FE9h to point to FSR0L. Then, writing W to FSR0L can change FSR0L to 50h. However, FSR0 = FE9h (the location of FSR0L) W = 50h MOVWF * FSR0 ++; (POSTINCO) At the same time that FSRO increment is to occur, an attempt will be made to write W to FSROL. The write of W will exceed the post-increment, and FSR0L will be 50h. 96779.doc -36- 200530920 Instruction Set Overview ： The instruction set of the invention consists of 77 instructions. Due to the previous page and repository switching in the prior art architecture, a linearization program and data memory mapping are needed and the instruction set is modified to promote this linearization. The data memory space of this embodiment is up to 4 kbytes, which is composed of 16 repositories, each of which has 256 bytes. In a preferred embodiment of the present invention, all special function registers are located in two repositories, preferably in the operation code of deduction 7 which specifies all file manipulations (which can force a virtual repository). One bit. Therefore, it is not necessary to switch banks to access special function registers. In the preferred implementation < column, the program memory space is modified to a maximum of 2M it groups based on the & previous technology system. Increase the PC from 13-bit to the latest 21-bit, and change some instructions (CALL ·, GOTO) that cause jumps to two-word instructions to load the 21-bit value for the PC. Compared with the prior art, another improvement system includes a modular simulator. This requires communication between the two chips used for simulation, and in order to achieve the required speed, it is not possible to have different source and destination registers in the same instruction cycle. Therefore, "'" eliminates the MOVPF and MOVFP instructions in the prior art. In order to maintain this functionality, a two-word instruction MOVFF is added. The instruction set of the present invention can be grouped into three types: • Byte-oriented • Bit-oriented • Text and control operations. Figure% shows these formats. Figure 54 shows a field description of the opcode. These 96779.doc 200530920 2 clearly help to understand the operation codes in each instruction description found in Figures 57 to 59 and Appendix A. Figure 114 illustrates the instruction decode map. For byte-oriented instructions, H indicates the -file temporary storage ϋ specifier, and d, indicates -destination specifier. The slot register specifier specifies which file register to use for the 1 instruction. The destination specifier specifies where to put the result of ^. If d, =, 〇, then put the result in;: memory. If ... ’, the result is placed in the register designated by the instruction. 〃 Similarly, for byte-oriented instructions, a, indicates the selection of a virtual repository. If a = '0', the BSR is overwritten and the virtual repository is selected. If a 1, the repository selection register (BSR) is not overridden. For bit 7G-oriented instructions, b indicates the _bit field designator, and selects the number of bits affected by the operation, while f indicates the address of the slot where the bit is located. , Pair: text and control operation, 'k' represents an 8, 12, 16, or 20-bit constant A text value n 'v represents a quick call / return selection bit. If ☆ · 〇, the shadow register is unused. If v =, then the two RETURN or RETFIE instructions update the w, bsr ', and TUS registers from the shadow register, or load the corresponding PS register from the corresponding register via a CALL instruction. Finally, the 2 Complement, which determines the direction and magnitude of the jump relative to the branch instruction. The instruction set is highly orthogonal and is grouped into groups. • Byte-oriented operations • Bit-oriented operations 96779.doc -38- 200530920 • Text and control operations execute all instructions in a single instruction cycle, unless: • A conditional test is true. • The program counter is changed due to an instruction. • A file-to-file transfer is performed. • A table read area or a table write instruction is executed. In the above case, the execution takes two instruction cycles. The two cycles are executed as a NOP. Special Function Registers as Source / Destination The orthogonal instruction set of the present invention allows reading and writing of all file registers, including special function registers. There are some special situations that users should be aware of:

STATUS as a destination If an instruction is written to the STATUS register, the Z, C, DC, OV, and N bits can be set or cleared as a result of the instruction and the original data bits written can be overwritten.

PCL as source or destination Read, write or read-modify-write on PCL can have the following results: • For a read PCL, first PCU to PCL ATU; then PCH to PCLATH; then PCL to destination Ground. • For a write to PCL, first PCLATU to PCU; then PCLATH to PCH; then 8-bit result value to PCL. • For a read-modify-write: first PCL to ALU operand, then PCLATH to PCH, then PCLATU to PCU, and then 8-bit result to 96779.doc -39- 200530920 PCL〇 Among them: PCL = program counter low Tuple PCH = program counter i: device high byte PCLATH = program counter high holding latch PCU: upper part of program counter tuple PCLATU = program counter upper holding latch dest = destination, W or f. Bit manipulation All bit manipulation instructions are completed by first reading the entire register, operating on the selected bit, and writing back the result (Read-Modify-Write (R-M_W)). Users should keep this in mind when operating on some special function registers (such as ports). It should be noted that the status bits (including interrupt flag bits) controlled by the device are set or cleared during the Q1 cycle. Therefore, there is no problem when executing the R_M-W instruction on the register containing these bits. Figures 60 to 113 contain flowcharts of the general operations of each instruction in the instruction set of the present invention. The figures show generalized and specific steps for retrieving and executing instructions within the instruction set of the present invention. For example, Figure 60 shows the steps for retrieving a byte-oriented file register operation, which includes the instructions ADDWF, ADDWFC, ANDWF, COMF, DECF, INCF, IORWF, MOVF, RLCF, RLCCF, RRCF, RRCCF, SUBFWB, SUBWF, SUBWFB, SWAPF, XORWF, MOVWF and NOP 〇 Similarly, Figure 61 shows the steps for performing a byte-oriented file register operation, which includes the instructions ADD WF, ADWDFC, AND WF, COME, DECF, INCF, 96779 .doc -40- 200530920 IORWF, MO VF, RLCF, RNLCF, RRCF, RRCCF, SUBF WB, SUBWF, SUWFB, SWAPF, and XORWF (but MOVWF only performs a dummy read, and NOP performs a dummy read and a dummy write Into). Figure 77 shows the retrieval steps for text operations, which include the instructions ADDLW, ANDLW, IOLWL, MOVLW, SUBLW, and XORLW. As before, FIG. 78 shows the execution steps of the text operation, which includes the instructions ADDLW, ANDLW, IOLWL, MOVLW, SUBLW, and XORLW. FIG. 90 shows a flowchart of a fetch branch operation, which includes instructions BC, BN, BNC, BNN, BNV, BNZ, BV, and BZ. Similarly, Fig. 90 shows a flowchart for performing a branch operation, which includes instructions BC, BN, BNC, BNN, BNV, BNZ, BV, and BZ. The remaining diagrams show the steps to retrieve and execute other instructions in the instruction set. For multi-word instructions that require two fetches to obtain a complete instruction, three flowcharts are used to illustrate the entire fetch and execution process. For example, Figures 70 to 72 illustrate the MOVFF instruction. Figure 70 shows a relatively standard acquisition operation. However, Fig. 71 shows the execution of the first part of MOVFF on the left side of the operation box, and the right part of the operation box shows the fetching of the second character of the instruction. Therefore, Fig. 72 only shows the execution steps of the second character of the MOVFF instruction. Similar flowcharts are provided for other multi-word instructions: LFSR (Figures 79 to 81); GOTO (Figures 102 to 104); CALL (Figures 105 to 107); TBLRD *, TBLRD * +, TBLRD *-and TBLRD + * (Figure (108 to 110); TBLWT *, TBLWT * +, TBLWT *-, and TBLWT + * (Figures 111 to 113). Appendix A contains a detailed list of operation codes and instructions of the instruction set of the present invention. Materials incorporated in Appendix A by reference for all purposes. 96779.doc -41-200530920 Index with text offset Figure U5 illustrates another addressing mode, specifically an addressing mode with an index with text offset. In a specific embodiment, the addressing mode of an index with text offset is activated by programming a context bit called an index bit to T. The index bit may be implemented as a fuse, but it may also be implemented in software or any flag / switch actuation technology. When the index bit is programmed into actuation, the index address pattern with text offset will depend on the address and will also depend on the value of the access bit in the instruction character. This mode is only applicable to instructions using direct forced addresses. If the access bit is set to, the addressing method from the previous architecture will not change, and the addressing mode is preset to be directly short. If the value of the access bit is 0, the address contained in the instruction character is decoded and compared with the value 5Fh. If the address is greater than 5Fh, the addressing mode is decoded as directly forced. If the access bit is zero and the address in the instruction character is less than or equal to 0Fh, the addressing mode is an index with text offset. When this happens, the address in the instruction character is preset to a literal value added to the fsr2 content. The resulting value is then used as the address to be manipulated. Figure 116 shows how an index with text offset is partitioned into an access repository when it is activated. You can map locations_ to 51? 11 to any location in memory. Map the starting address of this part of the access repository to the address contained in the FSR2H: FSR2L register. Modifications to FSR2 include the instruction register ’added to FSR2. To support the index mode with text offset, the lower seven bits are included as one of four possible values. 96779.doc 200530920 content. The data contained in the IR is treated as an unsigned integer, and the result is not stored in FSR2. There are four addressing modes: • Indirect (INDF); • Increment / decrement (FSR2 +), (+ FSR2) and (FSR2-) indirect modes; • Offset indirect mode (FSR2 + W, where W Content is for offset); and • Indirect mode with text offset (FSR2 + text). The invention includes an instruction set that, when invoked, executes one or more tasks on a microcontroller. Several instructions are described below. In special cases, these instructions can be called by, for example, a switch or other equivalent measures. The "PUSHL" instruction pushes an 8-bit text value onto the stack. The actual syntax of the PUSHL instruction is "PUSHLk", where 0 < = k < = 225. The invocation of this command does not affect the state of the microcontroller. The encoding of the PUSHL instruction is "1110 1010 kkkk kkkk", in which 8-bit characters are specified by the kkkk kkkk part of the instruction. Here, this 8-bit text is copied to the location where the second file selection register ("FSR2") is being addressed, and FSR2 is decremented. The "SUBFSR" instruction subtracts a 5-bit text from a file selection register ("FSR"). The syntax of this command is "SUBFSR f, k", where 0 < = f < = 2 and 0 < = k < = 63. The invocation of this command does not affect the state of the microcontroller. The encoding of this command is "1110 1001 ffkk kkkk". When called, it subtracts 6-bit (unsigned) text from 96779.doc -43- 200530920 FSRf and stores the result back to FSRf, where the " The "ff" section specifies a specific file selection register, and the "kk kkkk" section of the command specifies text. The "SUBULNK" instruction subtracts a 5-bit character from the second file selection register ("FSR2") and returns the resulting value. The syntax of this command is "SUBULNK k", where 0 < = k < = 63. The invocation of this command does not affect the state of the microcontroller. The encoding of this command is "1110 1001 llkk kkkk". When called, it subtracts 6-bit (unsigned) text from FSR2, stores the result back to FSR2, and returns the result and the execution to the caller. The "ADDFSR" instruction adds a 5-bit text to an FSR. The syntax of this instruction is "ADDFSR f, k", where 0 < = f < = 2 and 0 < = k < = 63. The state of the microcontroller is not affected by this instruction. The encoding of this instruction is "1110 1000 ffkk kkkk". When called, it adds 6-bit (unsigned) text to the slave FSRf and stores the resulting value back to the FSRf, where the "ff" part of the instruction Specify a specific file selection register and specify text in the "kk kkkk" part of the command. The "ADDULNK" instruction adds a 5-digit character to FSR2, and returns the result and the execution to the call routine. The syntax of this instruction is "ADDULNK k", where 0 < = k < = 63. The call of this instruction does not affect the state of the microcontroller. The encoding of the instruction is "11 10 1000 llkk kkkk", where when called, a 6-bit (unsigned) text (specified by the "kk kkkk" part of the instruction) is added to FSR2, and the result is Save back to F SR2 and return execution to the pager. The "MOVSF" instruction stores a stack location in the general register 96779.doc -44- 200530920 ("GPR"). The syntax of this instruction is r m0VSF s, d ", where 0 < = s < = 127 and 0 < == d < = 4095. The call of this instruction does not affect the state of the microcontroller. The instruction is coded in two words, of which Word 1 is "1110 1 〇 11

Osss ssss "and Word 2 is" mi dddd dddd dddd ", and the" sss ssss "part of the first character of the command specifies a source, and the" dddd dddd dddd "part of the second character specifies the destination . When this instruction is called, the 7-bit text value is added to the value in FSR2 to obtain an 8-bit value source address', and then the source address is copied to a location specified by the 12-bit value d . The FSR2 value is not affected by the MOVSF instruction, and the state of the microcontroller is not affected. The "MOVSS" instruction copies one stack position to another stack position. The syntax of this instruction is "MOVSS s, d", where 0 < = s < = 127 and 0 < = d < = 127. The call of this instruction does not affect the state of the microcontroller. The instruction is encoded in two words, where Word 1 is "1110 1011 lsss ssss", and Word 2 is "1111 χχχχddd dddd", and the "sss ssss" portion of the first character of the instruction specifies a source , And the r ddd dddd "portion of the second character specifies the destination. When this instruction is called, a 7-bit text value is added to the value in FSR2 to obtain a source address of an 8-bit value. The source address is then copied to a single-bit address (the address is The 7-bit value is added to the value in FSR2 to determine the position specified). The FSR2 value is not affected by the MOVSS instruction and the state of the microcontroller is not affected. The "CALLW" command is an indirect call. The syntax of this command is "C ALLW". The call of this instruction does not affect the state of the microcontroller. The encoding of this command is "0 0 0 0 0 0 0 0 0 0 01 010 0". When this command is called, the address of the next instruction of 96779.doc • 45-200530920 is pushed onto the hardware stack. To be clear, copy the value from the first register (such as PCLATU: PCLATH) into the higher 16 bits of the program counter ("PC") and copy the second register (such as w register ( "WREG")) to the lower 8 bits of the pc. The present invention is thus well suited for carrying out this purpose, and obtains the above-mentioned objects and advantages, and others inherent therein. Although the invention has been described and defined with reference to exemplary embodiments thereof, such references do not represent a limitation of the invention, nor can it be inferred. As is known to those skilled in the art, the present invention can modify and change the equivalent type and function of the shell. The specific embodiments described and illustrated in the present invention are only for illustrative purposes, and are not intended to describe the scope of the present invention in detail. Therefore, the present invention is limited only by the spirit and scope of the scope of the appended patent application, and it fully grants equivalents in all respects. [Brief description of the drawings] Figure 1 is a schematic block diagram of a medium-sized microcontroller unit of the prior art; Figure 2 is a schematic block diagram of the Harvard architecture of the prior art; Figure 3 is a schematic block diagram of the vonNeumann architecture of the prior art; Timing chart of technology clock / instruction cycle; Figure 5 is a schematic diagram of executing multiple instructions; Figure 6 is a schematic block diagram of the microcontroller core of the present invention; Figure 7 is a timing diagram of Q cycle activities of the present invention; Figure 8 is Timing diagram of the clock / instruction cycle of the present invention; Figure 9 is a flowchart of the instruction pipeline of the present invention; Figure 10 is a flowchart of the instruction pipeline of the present invention; 96779.doc -46- 200530920 Figure 11 is a flowchart of the instruction pipeline of the present invention Figure 12 is a flowchart of the instruction pipeline of the present invention; Figure 13 is a flowchart of the instruction pipeline of the present invention; Figure 14 is a flowchart of the instruction pipeline of the present invention; Figure 15 is a block diagram of a state register of the present invention; 16 is a block diagram of the program counter of the present invention; FIG. 17 is a block diagram of the program counter of the present invention using CALL and GOTO instructions, FIG. 18 is a block diagram of a stack index register of the present invention, and FIG. 19 is the present invention. Block diagram of the top register of the stack top, Figure 20 is a block diagram of the stack top high register of the present invention; Figure 21 is a block diagram of the stack top low register of the present invention; Figure 2 2 illustrates the present invention Stack reset operation; FIG. 23 illustrates the first € 80 on the initial stack of the present invention; FIG. 24 illustrates the second consecutive call on the stack of the present invention; and FIG. 25 illustrates the 31st and The 32nd continuous CALL ·; Take FIG. 26 to explain a pop operation on the stack of the present invention; FIG. 27 illustrates a stack return that causes a stack underflow condition in the present invention; FIG. 28 illustrates a stack on the stack of the present invention pUSH instruction; FIG. 29 illustrates a pop instruction on the stack of the present invention; FIG. 30 is a block diagram of the program memory mapping and stacking of the present invention; FIG. 31 is a block diagram of the memory mapping of the present invention; Block diagram of the memory map of the invention; 96779.doc -47- 200530920 Figure 33 is a block diagram of the device memory map of the invention in different program modes; Figure 34 is a MEMCON register of the invention Block diagram; Figure 35 is an illustration Block diagram of the invention's coNFIGi state byte; Figure 36 is a schematic block diagram of the 16-bit external memory connection configuration of the present invention; Figure 37 is a diagram of the 8-bit external memory connection configuration of the present invention Block diagram; Figure 38 is a list of typical port functions of the present invention; Figure 39 is a timing diagram of the external program memory bus in the 16-bit mode of the invention; Figure 40 is an external program memory in the 8-bit mode of the invention Figure 41 is a timing diagram of the external bus cycle type of the present invention; Figure 42 is a schematic block diagram of the data memory mapping and instruction "&" bit of the present invention; Figure 43 is the present invention. Mapping of special function register; Figure 44 is a schematic diagram of the core special function register of the present invention; Figure 45 is a continuation of the core special function register of Figure 44; Figure 46 is a schematic diagram of the direct short addressing mode of the present invention Block diagram, Figure 47 is a schematic block diagram of the BSR operation of the present invention; Figure 48 is a schematic block diagram of the BSR operation of the present invention during the simulation / test mode; ^ Figure 49 is a schematic block of the direct forced addressing mode of the present invention Figure; 50 is a schematic block diagram of the direct strong addressing mode of the present invention; 96779.doc -48- 200530920 Figure 51 is a schematic block diagram of the direct long addressing mode of the present invention; Figure 52 is a schematic block diagram of the indirect addressing mode of the present invention Figure 53 is a schematic block diagram of the indirect addressing mode of the present invention; Figure 54 is an illustrative list operation code field of the present invention; Figure 55 is a list of indirect addressing symbols of the present invention; Figure 56 illustrates the generality of the instructions of the present invention Format; Figure 57 is a partial list of the instruction set of the present invention; Figure 58 is a partial list of the instruction set of the present invention; Figure 59 is a partial list of the instruction set of the present invention; Figure 60 is a byte-oriented file of the present invention Flow chart of register operation; Figure 61 is a flowchart of byte-oriented file register operation (execution) of the present invention; Figure 62 is a flowchart of CLRF, NEGF, SETF (fetch) instructions of the present invention; Figure 63 is a flowchart of the CLRF, NEGF, SETF (execute) instructions of the present invention, Figure 64 is a flowchart of the DECFSZ, DCFSNZ, INCFSZ, ICFSNZ (fetch) instructions of the present invention; Figure 65 is a DECFSZ of the present invention , DCFSNZ INCFSZ, ICFSNZ (fetch) instruction flowchart; Figure 66 is a flowchart of the CPFSEQ'CPFSQT ^ CPFSLT ^ TSTFSZ ^ fetch) instruction of the present invention; Figure 67 is a CPFSEQ, CPFSQT, CPFSLT, and TSFTSZ (execution) of the present invention Instructions flow chart; 96779.doc -49- 200530920 Figure 68 is a flowchart of the MULWF (retrieval) instruction of the present invention; Figure 69 is a flowchart of the MULWF (execute) instruction of the present invention; Figure 70 is a MULFF of the present invention (Fetch) instruction flowchart; Figure 71 is a flowchart of the MULFF (execute 1) instruction of the present invention; Figure 72 is a flowchart of the MULFF (execute 2) instruction of the present invention; and Figure 73 is a BCF and BSF of the present invention , BTG (fetch) instruction flowchart; Figure 74 is a flowchart of the BCF, BSF, BTG (fetch) instructions of the present invention; Figure 75 is a flowchart of the BTFSC and BTFSS (fetch) instructions of the present invention; 76 is a flowchart of the BTFSC and BTFSS (execute) instructions of the present invention; FIG. 77 is a flowchart of the text operation (retrieval) of the present invention; FIG. 78 is a flowchart of the text operation (execution) of the present invention; Flow chart of the LFSR (fetch) instruction of the present invention; FIG. 80 shows the LFSR (execution 1) of the present invention Instructions flow chart; Figure 81 is a flowchart of the LFSR (execute 2) instruction of the present invention; Figure 82 is a flowchart of the DAW (fetch) instruction of the present invention; Figure 83 is a flow of the DAW (execute) instruction of the present invention Figures; Figure 84 is a flowchart of the MULLW instruction of the present invention; Figure 85 is a flowchart of the MULLW (execute) instruction of the present invention; Figure 86 is a CLRWDT, HALT, RESET, and SLEEP (retrieval) of the present invention ) Instructions flow chart, Figure 87 is a flowchart of the CLRWDT, HALT 'RESET and SLEEP (execute) instructions of the present invention; Figure 88 is a flowchart of the MOVELB (fetch) instruction of the present invention; Figure 89 is a MOVLB of the present invention (Execution) instruction flow chart; 96779.doc -50- 200530920 Fig. 90 is a flow chart of the branch operation (acquisition) of the present invention; Fig. 91 is a flow chart of the branch operation (execution) of the present invention; Flow chart of the BRA and RCALL (fetch) instructions of the invention; Figure 93 is a flow chart of the BRA and RCALL (execution) instructions of the invention; Figure 94 is a flow chart of the PUSH (fetch) instructions of the invention; Flow chart of the PUSH (execute) instruction of the present invention; FIG. 96 is a POP (fetch) of the present invention Fig. 97 is a flowchart of the POP (execute) instruction of the present invention; Fig. 98 is a flowchart of the RETURN and RETFIE (retrieve) instruction of the present invention; Fig. 99 is a RETURN and RETFIE (execute) of the present invention Instructions flow chart; Figure 100 is a flowchart of the RETLW (fetch) instruction of the present invention; Figure 101 is a flowchart of the RETLW (execute) instruction of the present invention; Figure 102 is a flow of the GOTO (retrieve) instruction of the present invention Fig. 103 is a flowchart of the GOTO (execute 1) instruction of the present invention; Fig. 104 is a flowchart of the GOTO (execute 2) instruction of the present invention; Fig. 105 is a flowchart of the CALL instruction of the present invention; Fig. 106 is a flowchart of the CALL (execute 1) instruction of the present invention; Fig. 107 is a flowchart of the CALL (execute 2) instruction of the present invention; Fig. 108 is a TBLRD *, TBLRD * +, TBLRD *-and TBLRD + * (fetch) instruction flowchart; Figure 109 is a flowchart of the TBLRD *, TBLRD * +, TBLRD *-and TBLRD + * (execute 1) instructions of the present invention; 96779.doc -51-200530920 Figure 110 Series The flowchart of the TBLRD *, TBLRD * +, TBLRD *-and TBLRD + * (execute 2) instructions of the present invention; FIG. 111 shows the present invention. TBLWT *, TBLWT * +, TBLWT *-and TBLWT + * (fetch) instructions flowchart; Figure 112 is a flowchart of the TBLWT *, TBLWT * +, TBLWT *-and TBLWT + * (execute) instructions of the present invention; Figure 113 is a flowchart of the TBLWT *, TBLWT * +, TBLWT *-and TBLWT + * (execute 2) instructions of the present invention; Figure 114 is the instruction decoding map of the present invention; Figure 115 is a block of the alternate paging scheme according to the principles of the present invention Illustration. FIG. 116 is a block diagram of an alternate paging scheme according to the principles of the present invention. [Description of Symbols of Main Components] 22 Data Memory 24 CPU 26 Program Memory 34 CPU 36 Data and Program Memory 100 Microcontroller Core 102 Address Latch 104 Data Memory 106 Data Latch 108 Selection Circuit 110 Repository 112 decoder 96779.doc -52- 200530920

118 Bank selection register 120 FSR 121 FSR 122 FSR 124 Table latch 126 IR latch 128 Product register 134 Hardware multiplier 136 Working (W) register 140 Arithmetic and logic unit (ALU) 142 Arithmetic and Logic Unit (ALU) 144 Instruction decoder 148 Table pointer 152 ROM latch 154 System bus 158 Data latch 160 Data or program memory 162 Address latch 168 Program counter (PC) 170 Stack 172 Stack Indicator 174 Data bus 176 PCLATU 178 PCLATH

96779.doc -53- 200530920

180 PCU 182 PCH 184 PCL

96779.doc -54- 200530920

Annex A

96779.doc 200530920

ADDLW: Add text to π to W Syntax: [Mark]: ADDLW k Operand: 0 ^ 1 ^ 255 Operation: (W) + k—W Affected states: N, OV, C, DC, Z 0000 1111 kkkk kkkk Description: Add the contents of W to the 8-bit text V and place the result in W. Words: 1 Cycles: 1 Q cycle activity:

Q1 Q2 Q3 Q4 Decode and read the text 'k1 Processed data is written to W Example: ADDLW 0x15 Before the instruction W = 0xl0 After the instruction W = 0x25 ADDWF: Add W to f Syntax ·· [Mark]: ADDWF f, d , A operand: 0SfS255 cK〇, l] a bank 0, 1] operation: (W) + (f)-&d; dest 96779.doc 200530920

Affected states: N, OV, C, DC, Z 0010 Olda ffff ffff Description: Add W to the scratchpad, f. If 'd' is 0, the result is stored in W. If 'd' is 1, the result is stored back in register T (default). If fa ’is 0, the virtual repository will be selected. If 'af is 1, the BSR (preset) is not covered.

Words · 1 Number of cycles: 1 Q cycle activity: Q1 Q2 Q3 Q4 Decoding Read register'f Process data Write to destination Example: ADDWF REG, 0, 0 Before the instruction W = 0xl7 REG = 0xC2 After the instruction

W = 0xD9 REG = 0xC2 ADDWF: C adds W to the carry bit α to f Syntax: [Mark] ADDWFC f, d, a Operand: 0SfS255 d ,, l] a ,, l] 96779.doc 200530920

Operation: (W) + (f) = (C) —dest Affected states: N, OV, C, DC, Z 0010 OOda ffff ffff Description: Add W, Carry Flag and data memory position T. If 'df is 0, the result is placed in W. If 'd' is 1, the result is placed in data memory location T. If it is not 0, the virtual repository will be selected. If 'aW is 1, BSR is not covered.

Words · 1 Cycles: 1 Q cycle activity: οι Q2 Q3 04 Decode Read register τ Process data Write to destination Example · ADDWFC: REG, 0, 1 Carry bit before instruction = 1 REG = 0x02

W = 0x4D Carry bit after instruction = 0 REG = 0x02 W = 0x50 ANDLW: AND text and W Syntax: [Mark] ANDLWk 96779.doc 200530920

Operand: 0 ^ 1 ^ 255 Operation ... (W) .AND.k—W Affected state: N, Z 0000 1011 kkkk kkkk

Explanation: The content of W is ANDed with the 8-bit character 'k'. Place the result in W.

Words: 1 Number of cycles: 1 Q cycle activity: Q1 Q2 Q3 Q4 Decode Read text ‘k’ Process data Write to w Example: ANDLW 0x5F Before instruction W = 0xA3 After instruction W = 0x03

ANDWF: AND W and f Syntax: [Mark] ANDWF f, d, a Operand: 0 < f ^ 255 d ,, l] a ,, l]

Operation: (W) .AND · (f) —dest Affected state: N, Z 96779.doc 200530920 0001 01 da ffff ffff Description: AND operation is performed on the contents of w and the register τ m and d. , The spleen fruit is stored in W. If yes, the result is stored back in staging_ (default). If V is 0, the virtual repository will be selected. If, / does not overwrite the BSR (default). ° & ’系 1,

Words · 1 Cycles: 1 Q Cycle Activities: Q3

^ —— Pay for asset management Example: ANDWF: REG, 0, 〇 ^ ~ Before the instruction W = 0xl7 REG = 0xC2 After the instruction W = 0x02 REG = 0xC2

BC: if carry, branch syntax: [mark] BC η operand: -128 < η ^ 127 operation: if carry bit '1, then (PC) + 2 + 2n ~> Pc Affected state: None 1110 0010 nnnn ηηηιΓ 96779.doc 200530920 Description: If the carry bit is' r, the program will branch. 2's complement f2n 'is added to the PC. Because PC has been incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is a one or two cycle instruction. Words: 1 Cycles: 1 (2) Q cycle activity: If jump:

Ql Q2 Q3 04 Decode read text fn 'Process lean write to PC No operation No operation No operation No operation If there is no jump: Q1 Q2 Q3 Q4 Decode read text' η 'Processing data without operation Example: HERE BC 5 instruction Before PC = address (HERE) instruction If Carry = 1; PC = address (HERE + 12) If Carry = 0; PC = address (HERE + 2) BCF: Clear bit syntax in f: [mark] BCF f , B, a Operand: 0 ^ f ^ 255 96779.doc 200530920 0 ^ b < 7 a ,, l] Operation: 0—f < b > Affected state: None 1001 bbba ffff ffff Description: Clear register Bit 'b' in T. If 'a' is 0, the virtual bank will be selected, overriding the BSR value. If 'a' is 1, the bank will be selected according to the BSR value (default).

Words: 1 Number of cycles: 1 Q cycle activity: Q1 Q2 Q3 Q4 Decoding read register τ Processing lean write register 'f Example ·· BCF FLAGJRJEG, 7, 0 FLAG—REG = 0xC7 # instruction before instruction Post FLAG_REG = 0x47 BN: If negative, branch syntax: [Mark] BN η Operand: -128Snd27 Operation: If negative bit system is '1', then (PC) + 2 + 2n—PC Affected state: None 96779.doc 200530920 1110 0110 ηηηη ηηηη Note: If the negative bit system is τ, the program will branch. 2's complement '2η' is added to the PC. Because PC has been incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is a one or two cycle instruction. Words: 1 Cycles: 1 (2) Q cycle activity: If jump: οι 02 03 04 Decode read text soil 'Process data written to PC No operation No operation No operation No operation If no jump: Q1_Q2_Q3_Q4 Decode read text 'nf Example of processing lean material without operation: HERE BN Jump instruction before POaddress (HERE) instruction if Negative = 1; PC = address (Jump) if Negative = 0; PC = Address (HERE + 2) BNC: if no carry, Then the branch syntax: [Mark] BNC η 96779.doc 200530920 Operand: -128 lights < 127 operation · · If the carry bit system is '〇', then (PC) + 2 + 2n—PC Affected state: None 1110 0011 nnnn nnnn Description: If the carry bit is '0', the program will branch. 2's complement '2n' is added to the PC. Because PC has been incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is a one or two cycle instruction.

Words: 1 Φ Number of cycles: 1 (2) Q cycle activity: If jump:

Ql Q2 Q3 Q4 Decode read text 'nf processed data written to PC No operation no operation No operation No operation if no jump: Ql Q2 03 Q4 Decode read text' nf processed data No operation Example: PC before HERE BNC Jump instruction = address (HERE) If Carry = 0 after the instruction; PC = address (Jump) If Carry = 1; 96779.doc -10- 200530920 PC = address (HERE + 2) BNN: If non-negative, branch syntax: [mark] ΒΝΝη Operand: -128 < fS127

Operation: If the negative bit system is ‘〇’, then (PC) + 2 + 2n—PC Affected state: None Editing stone horse · 1110 0111 nnnn nnnn Description: If the negative bit system is f0f, the program will branch. Add 2's complement to PC. Because PC has been incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is a one or two cycle instruction. Words: 1 Number of cycles: 1 (2) Q cycle activity: If jump: Q1 Q2 Q3 Q4 Decode read text 'η' Process data written to PC No operation No operation No operation No operation If no jump: Q1 Q2 Q3 Q4 No operation example for decoding and reading word processing data: PC = address (HERE) 96779.doc -11-200530920 before instruction, if Negative = 0; PC = address (Jump) if Negative = 1; PC = address ( HERE + 2) BNV: if there is no overflow, branch syntax: [mark] BNVn operand: -128 < η < 127 operation: if the overflow bit is '0', then (PC) + 2 + 2n—PC Affected status: None 1110 0101 nnnn nnnn Description: If the overflow bit is '0', the program will branch. A 2's complement of 2nf is added to the PC. Because PC has been incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is a one or two cycle instruction.

Words: 1 Cycles: 1 (2) Q cycle activity: If jump:

Ql Q2 Q3 Q4 Decoding and reading text processing data is written to PC No operation No operation No operation No operation If there is no jump: Q1 Q2 Q3 Q4 Decoding reading text 'η' Processing data without operation 96779.doc • 12- 200530920 Example : HERE BNV Jump instruction before POaddress (HERE) instruction If Overflow = 0; PC = address (Jump) If Overflow = 1; PC = address (HERE + 2) BNZ: If non-zero, branch syntax ·· [mark] BNZ η Operand ·· -128 < η < 127 Operation: If the zero bit system is '〇', then (PC) + 2 + 2n—PC Affected state: No stone horse · 1110 0001 nnnn nnnn Explanation: If If the zero bit is '0', the program will branch. 2's complement '2n' is added to the PC. Because PC has been incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is a one or two cycle instruction. Words: 1 Cycles: 1 (2) Q cycle activity: If jump:

Ql Q2 Q3 Q4 Decode read text 'nf Process data written to PC 96779.doc • 13-200530920 No operation No operation No operation No operation If there is no jump Q1 Q2 Q3 Q4 Decode read text' 1 ^ Processing lean material No operation Example: Before HERE BNZ Jump instruction PC = address (HERE) instruction

If Zero = 0; PC = address (Jump) if Zero = 1; PC = address (HERE + 2) BRA: unconditional branch syntax: [tag] BRA η operand: -1024 < nS1023 operation: (PC) +2+ 2n- > PC 0 Affected state: None 1101 Onnn nnnn nnnn Description: Add 2's complement '2n' to the PC. Because the PC has been incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is a two-cycle instruction. Words: 1 Number of cycles: 2 Q cycle activities: 96779.doc 14- 200530920 Q1 Q2 Q3 Q4 Decode and read text soil 'Process data written to PC No operation No operation No operation No operation Example: POaddress (before the HERE BRA Jump instruction HERE) After the instruction PC = address (Jump) BSF: Set the bit syntax in f ·· [marker] BSF f, b, a operand ·· 0 ^ f ^ 255 〇 ^ b < 7 a ,, l] operation : 1—f < b> Affected state: None 1000 bbba ffff ffff Description: Set bit 'b' in register 'f. If it is not 0, the virtual repository will be selected, overriding the BSR value. If Y is 1, the bank will be selected according to the BSR value.

Words ·· 1 Cycles: 1 Q cycle activity:

Ql Q2 Q3 Q4 Decoding Read register Processing data Write register T 96779.doc -15- 200530920 Example: BSF FLAG_REG, 7, 1 Before the instruction

FLAG_REG = 0x0A After the instruction

FLAG_REG = 0x8A BTFSC: Only the bit test is accepted. If cleared, the syntax is skipped: [tag] BTFSC f, b, a operand · 〇sfS255 0 post 7 a ,, l] operation: if (f < b> ) = 0 Skip the affected states: None 1011 bbba ffff ffff Description: If bit 'b' in register T is 0, skip the next instruction. If bit seven 'is 0, the next instruction fetched during the current instruction execution is discarded and NOP is executed instead, making it a one- or two-cycle instruction. If 'a' is 0, the virtual repository will be selected, overriding the BSR value. If 'a' is 1, the bank will be selected according to the BSR value (default).

Words: 1 Cycles: 1 (2) Remarks: If skipped and followed by a 2-word instruction, it will be 3 cycles Q cycle activity: 96779.doc -16- 200530920

Ql Q2 Q3 Q4 Decode Read Register T Process data without operation if skipped: Ql Q2 Q3 Q4 No operation No operation No operation No operation If skipped and followed by a 2-word instruction: Ql Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation No operation example · HERE BTFSC FLAG, 1, 0 FALSE: TRUE: PC = address (HERE) before the instruction If FLAG < 1> = 0 after the instruction; PC = address (TRUE) If FLAG < 1 > = 1; POaddress (FALSE) ❿ BTFSS: bit test audit, if set U skip syntax: [tag] BTFSS f, b, a Operand: 0 < fS255 0 < b < 7 a ,, l] 96779.doc -17- 200530920 Operation: If (f < b >) = l then skip the affected states: None 1010 bbba ffff ffff Note: If bit 'b' in register T is 1, skip the next instruction. If bit% 'is 1, the next instruction fetched during the current instruction execution is discarded and NOP is executed instead, making it a one- or two-cycle instruction. If it is not 0, the virtual repository will be selected, overriding the BSR value. If it is 1, the bank will be selected according to the BSR value (default).

Words: 1 Cycles: 1 (2) Remarks: If skipped and followed by a 2 word instruction, it will be 3 cycles Q cycle activity:

Ql Q2 03 Q4 Decode read register 'f Handle lean material No operation if skipped: Ql Q2 03 Q4 No operation No operation No operation No operation If skipped and followed by 2 word instruction: Ql Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation Example: HERE BTFSS FLAG, 1, 0 FALSE: TRUE: Before the instruction 96779.doc -18- 200530920 PC = address (HERE) If FLAG < 1 > = after the instruction 0; PC = address (FALSE) if FLAG < 1〉 = 1; POaddress (TRUE) BTG: bit syntax to trigger f: [tag] BTG f, b, a operand ·· 〇sfS255 0 < b < 7 ae [0,1] Operation: (/ < 6 >)-> (f < b>) Affected state: None 0111 bbba ffff ffff Description: Reverses bit seven 1 in the data memory position T. If fa 'is 0, the virtual repository will be selected, overriding the BSR value. If 'a' is 1, the repository will be selected according to the BSR value (default).

Words: 1 Number of cycles: 1 Q cycle activity: οι Q2 Q3 Q4 Decoding read register T Processing lean write register Example: BTG P0RTC, 4, 0 96779.doc 19 200530920 PORTC = 0111 0101 before instruction 0x75] PORTC = 0110 0101 [0x65] BV: if overflow, branch syntax ·· [mark] BV η Operand: -128Snd27 Operation: If the overflow bit is' Γ, then (PC) +2+ 2n—PC Affected state: No knitting horse · 1110 0100 nnnn nnnn Description: If the overflow bit system is' Γ, the program will branch. 2's complement '2n' is added to the PC. Because PC has been incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is a one or two cycle instruction. Words · 1 Cycles: 1 (2) Q cycle activity: If jump:

Ql Q2 Q3 Q4 Decoded read text 'nf Processed data written to PC No operation No operation No operation No operation If there is no jump: Q1_Q2_Q3_Q4 Decode read text' η 'Process lean material No operation 96779.doc -20- 200530920 Example: HERE BV Jump instruction before POaddress (HERE) after instruction if Overflow = 1; PC = address (Jump) if Overflow = 0; PC = address (HERE + 2) BZ: if zero, branch syntax · [mark] BZ η Operand: -128 ^ 1 ^ 127 Operation: If the zero bit system is T, then (PC) + 2 + 2n—PC Affected state: None 1110 0000 nnnn nnnn Explanation: If the zero bit system is' Γ, the program Will branch. A 2's complement of 2nf is added to the PC. Because PC has been incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is a one or two cycle instruction. Words: 1 Number of cycles: 1 (2) Q cycle activities: If jump: 96779.doc -21-200530920

Qj_Q2_Q3_Q4 Decode read text 'nf Process data written to PC No operation No operation No operation No operation If there is no jump: Ql Q2 Q3 Q4 Decode read text' nf Processing lean material without operation Example: PC = address before the HERE BZ Jump instruction (HERE) If Zero = l; PC = address (Jump) If Zero = 0; PC = address (HERE + 2) CALL: Subroutine call syntax: [Mark] CALL k, s Operand: 〇Skd048575 se [0, l] Operation: (PC) + 4-TOS, k- > PC < 20: l >? If s = l (w) -ws, (STATUS) -STATUSS, 96779.doc -22- 200530920

(BSR) —BSRS Affected Status: None

Note: The entire 2M byte memory range address (PC + 4) is pushed to the return heap Nie μ for hanging calls. First, it will return

Once on. If sf = 1, the w, STATUS, and BSR registers are also pushed to their individual shadow registers — 3, 8 and 8 and BSRS. If V = 0, no update occurs). The persuasion το value 'k' is then loaded into the PC < 20: 1 >. CALL is a two-cycle instruction.

Words: 2 Number of cycles: 2 Q cycle activity: Decode read words, k, < 7: 0 > ____ Q4 Push the PC to the stack to read the words, k, < 19: 8 > Write to PC No operation No operation No operation No operation Example: HERE CALL THERE, PC = address (HERE) before the instruction PC = address (THERE) TOS = address (HERE + 4) after the instruction

WS = W

BSRS = BSR 96779.doc -23- 200530920

STATUSS = STATUS CLRF: Clear f Syntax: [Mark] CLRF f, a Operand ·· 0SfS255 ae [0, l]

Operation: OOOh—f 1- > Z Affected state: z 0110 101a ffff ffff Description: Clear the contents of the specified register. If 'a' is 0, the virtual repository will be selected, overriding the BSR value. If 'a' is 1, the bank will be selected according to the BSR value (default).

Words: 1 Cycles: 1 Q cycle activity:

Ql Q2 Q3 Q4 Decode Read Register T Process Data Write Register ‘f Example: CLRF FLAG_REG, 1 before instruction

FLAG_REG = 0x5A After the instruction FLAG REG = 0x00 96779.doc -24- 200530920 CLRWDT: clear watch timer words> go: [marker already] CLHWDT operand: no operation: 000h—WDT, 000h—WDT post divider, 1 —Calendar, 1—Two affected states: Calendar, @ 编 石 马 · 0000 0000 0000 0100 Description: The CLRWDT instruction resets the watchdog timer. It also resets the WDT back-divider. Set status bits% and two. _

Words: 1 Cycles: 1 Q cycle activity:

Ql Q2 Q3 Q4 Decoding No operation Processing data No operation

Example: WDT counter before CLRWDT instruction =? After instruction WDT counter = 0x00 WDT post divider = 0 Τδ = \ PD = \ COMF: Supplementary f Syntax: [mark] COMF f, d, a 96779.doc -25- 200530920

Operand: 0sfS255 de [0, l] ae [0? L] Operation: (/)-&d; dest Affected state: N, Z 0001 llda ffff ffff Description: Supplement the contents of register 'f. If fd 'is 0, the result is stored in W. If 'df is 1, the result is stored back in register T (default). If 'a' is 0, the virtual repository will be selected, overriding the BSR value. If 'a' is 1, the bank will be selected according to the BSR value (default).

Words: 1 Number of cycles: 1 Q cycle activity: Q1_Q2_Q3_Q4_ Decoding Read register T process data Write to destination Example: COMF REG, 0, 0 Before instruction REG = 0xl3 After instruction REG = 0xl3

W = 0xEC CPFSEQ: Compare f with W, if f = W then skip syntax: [mark] CPFSEQ f, a 96779.doc -26- 200530920 Operand: 0 ^ f ^ 255 a ,, l] Operation: ⑴- (W), if (f) = (W) (unsigned comparison), then skip the affected state: unedited stone 焉 0110 001a ffff ffff Description · Compare data memory by performing an unsigned subtraction The contents of position 'f and the contents of W. If T = W, the fetched instruction is discarded, and a NOP is executed instead, making it a two-cycle instruction. If faf is 0, the virtual repository will be selected, overriding the BSR value. If 'a' is 1, the bank will be selected according to the BSR value (default).

Words: 1 Cycles: 1 (2) Remarks: If skipped and followed by a 2 word instruction, it will be 3 cycles of Q cycle activity: Q1 Q2 Q3 04 Decode Read Register 'f No operation if processing data Skip: Qi Q2 Q3 Q4 No operation No operation No operation No operation If skipped and followed by a 2-word instruction: Qi Q2 03 Q4 No operation No operation No operation No operation No operation No operation No operation No operation No operation 96779.doc- 27- 200530920 Example: HERE CPFSEQ REG, 0 NEQUAL: EQUAL: Before the instruction PC = address (HERE) W =? REG =? After the instruction if REG = W; PC = Address (EQUAL) If REG ^ W; PC = Address ( NEQUAL) CPFSGT: Compare f with W, if Bie skip syntax: [mark] CPFSGT f, a operand: 0 ^ f ^ 255 a ,, l] operation · (f)-(W), if ⑴> ( W) (unsigned comparison) skips the affected states: no knitting horse · 0110 010a ffff ffff Description: Compares the contents of the data memory location ff with the contents of W by performing an unsigned subtraction. If the content of T is greater than the content of W, the fetched instruction is discarded and a NOP is executed instead, making it a two-cycle instruction. If ‘aW is 0, 96779.doc -28- 200530920, the virtual repository will be selected, overriding the BSR value. If 'af is 1, the bank will be selected according to the BSR value (default).

Words: 1 Cycles: 1 (2) Remarks: If skipped and followed by a 2 word instruction, it will be 3 cycles Q cycle activity:

Ql Q2 Q3 Q4 Decoding read register 'f Handle lean material No operation if skipped: Ql Q2 Q3 Q4 No operation No operation No operation No operation If skipped and followed by a 2-word instruction: Q1_Q2_Q3_Q4 No operation No operation No Operation No operation No operation No operation No operation No operation No operation Example: HERE CPFSGT REG, 0 NGREATER: GREATER: PC = address (HERE) W =? Before the instruction If REG> W after the instruction; POAddress (GREATER) If REG ^ W; 96779 .doc -29- 200530920 PC = Address (NGREATER) CPFSLT: compare f with W, if f < W is too grammatical: [tag] CPFSLT f, a operand: 0Sf < 255 a ,, l] operation: ( f > (w), if (f) < (W) (unsigned comparison), skip the affected states: no kishima · 0110 000a ffff ffff Description: compare data by performing an unsigned subtraction The contents of the memory location T and the contents of W. If the contents of T are greater than the contents of W, the fetched instruction is discarded and a NOP is executed instead to make it a two-cycle instruction. If it is not 0, then A virtual repository will be selected, overriding the BSR value. If 'a' is 1, then BSR according to the selected value repository (default).

Words: 1 Cycles: 1 (2) Remarks: If skipped and followed by a 2 word instruction, it will be 3 cycles Q cycle activity:

Qi Q2 Q3 Q4 Decoding Read register T processing data No operation If skipped: Q1 Q2 Q3 Q4 No operation No operation No operation No operation 96779.doc -30- 200530920 If skipped and followed by 2 word instruction:

Ql Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation No operation Example: HERE CPFSLT REG, 1 NLESS: LESS: Before the instruction

PC = Address (HERE) W =? If REG < W after the instruction; PC = Address (LESS) If REG &W;W; PC = Address (NLESS) DAW: Adjust the decimal syntax of the W register: [mark] DAW operand : No operation: if [W < 3: 0 >> 9] or [DC = 1], then (W < 3: 0 >) + 6- ^ W < 3: 0 >; No HW < 3: 0 > ) 4W < 3: 0 >; If [\ ¥ < 7: 4 >> 9] or [01], Bay1 | (\ ¥ < 7: 4 >) = 6- > Boundary < 7: 4 >; No UW < 7: 4〉) — W < 7: 4 >;

Affected status: C 96779.doc -31-200530920 Code: 1 0000 丨 0000 丨 0000 I 0111 Description: DAW adjusts the octet obtained from the previous addition of two variables (each in packed BCD format) in W Value and produce a correct packed BCD result. Words: 1 Cycles: 1 Q cycle activity:

Ql Q2 Q3 Q4 Decode Read register w Process data Write w

Example 1: Before DAW instruction W = 0xA5 C = 0 DC = 0 After instruction W = 0x05 C = 1 DC = 0 Example 2: Before instruction W = 0xCE C = 0 DC = 0 After instruction W = 0x34 C = 1 96779. doc -32- 200530920 DC = 0 DECF ·· Decreasing f Syntax: [Mark] DECF f, d, a Operand: 0 < f < 255 d ,, l] ae [0, l] Operation: (f > l — dest

Affected states: C, DC, N, OV, Z 0000 Olda ffff ffff Description: Decrement register T. If fcT is 0, the result is stored in W. If 'd' is 1, the result is stored back in the register T (default). If 'a' is 0, the virtual repository will be selected, overriding the BSR value. If fa ’is 1, the bank will be selected according to the BSR value (default).

Words ·· 1 Cycles: 1 Q cycle activity:

Ql Q2 03 Q4 Decoding and reading register τ Processing lean write to the destination Example: DECF CNT, 1, 0 before the instruction CNT = 0x01 Z = 0 after the instruction 96779.doc -33- 200530920 CNT = 0x00 Z = 0 DECFSZ: Decrement f, if it is 0, megabytes grammar ... [mark] DECFSZ f, d, a operand 〇 SfS255 d ,, l] ae [0, l] Operation: (f > l —dest If the result = 0, then the affected state is skipped: no stone horse · 0010 1 Ida ffff ffff Description: Decrements the contents of the temporary register T. If 'Earth 0, the result is placed in W. If' If d 'is 1, the result is placed back in register T (default). If the result is 0, the next fetched instruction is discarded and a NOP is executed instead, making it a two-cycle instruction If fa 'is 0, the virtual repository will be selected, overriding the BSR value. If Y is 1, then the repository will be selected according to the BSR value (default).

Words: 1 Cycles: 1 (2) Remarks: If skipped and followed by a 2 word instruction, it will be 3 cycles Q cycle activity:

Ql Q2 Q3 Q4 Decoding Read register’f Process data No operation If skipped: 96779.doc -34- 200530920

01 02 Q3 04 No operation No operation No operation No operation If skipped and followed by a 2-word instruction: Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation No operation Example: HERE DECFSZ CNT, 1 , 1 GOTO LOOP CONTINUE before instruction PC = Address (HERE) after instruction CNT = CNT-1 if CNT = 0; PC = Address (CONTINUE) if CNT ^ O; PC = Address (HERE + 2) DCFSNZ: Decrement f, Mouth fruit 3 ^ 0, Bei Zhao Guo syntax: [tag] DCFSNZ f, d, a operand: 0 < f < 255 de [05l] ae [0? L] operation: (f > l-dest, if the result is 々 0, skip the affected state: no description: decrement the contents of register T. If 'd' is 0, the result is placed in W. 0100 llda ffff ffff 96779.doc -35- 200530920 If 'd 'Department 1, the result is placed back into the register T (default). If the result is 0, the next instruction that has been mined is discarded, and a NOP is executed instead, making it a two-cycle instruction. If 'a' is 0, the virtual repository will be selected, overriding the BSR value. If faf is 1, the repository will be selected according to the BSR value (default .

Words: 1 Cycles: 1 (2) Remarks: If skipped, and followed by a 2 word instruction, it is a 3 cycle Q cycle activity: Q1 Q2 Q3 Q4 Decoding read register 'f No operation if processing data Skip: Q1 Q2 Q3 Q4 No operation No operation No operation No operation If skipped and followed by a 2-word instruction: Q1 02 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation No operation Example: HERE DCFSNZ TEMP ， 1，0 ZERO: NZERO: TEMP before the instruction =? TEMP = TEMP-1 after the instruction, if TEMP = 0; 96779.doc -36- 200530920 POAddress (ZERO) if TESMP = 0; POAddress (NZERO) GOTO: unconditional Branch syntax ·· [mark] GOTO k operand: 0 < 1048575 Operation: k—PC < 20: l > Affected state: no encoding ·· first character (k < 7: 0 >) second Character (k < 19: 8 >) 1110 1111 k7kkk kkkk〇1111 ki9kkk kkkk kkkk8 Description: GOTO allows unconditional branching anywhere in the entire 2M byte memory range. The 20-bit value 'k' is loaded into the PC < 20: 1 >. GOTO is always a one-two two-cycle instruction. Words: 2 cycles: 2 Q cycle activities: Ql Q2 Q3 04 decode and read the text, k, < 7: 0 > push the PC into the stack to read the text, k, < 19: 8>, write to PC No operation No operation No operation No operation Example: PC = Address (THERE) after GOTO THERE instruction 96779.doc -37- 200530920 HALT: Halt processor syntax: [mark] HALT operand: No operation: processor in HALT instruction Suspended execution afterwards Affected state: None 0000 0000 0000 0000 Description: Although it functions in the simulation mode, execution of the pause instruction will suspend the execution of the processor. Triggering the HALT header or resetting (MCZi? = 〇) will take the device out of pause. The HALT instruction is not recognized in non-analog mode. Words: 1 Cycles: 1 Q cycle activity:

Qi Q2 Q3 Q4 Decoding no operation no operation pause INCF: increment f Syntax: [mark] INCF f, d, a Operand: 0sfS255 de [0? L] ae [0, l] Operation: (f) + l- > dest

Affected states: C, DC, N, OV, Z 96779.doc -38- 200530920 0010 lOda ffff ffff Description: Increment the content of register ff. If 'd' is 0, the result is placed in W. If 'd' is 1, the result is placed back in the register T (default). If 'a' is 0, the virtual repository will be selected, overriding the BSR value. If faf is 1, the bank will be selected according to the BSR value (default).

Words · 1 Number of cycles: 1 Q cycle activity: Q1 02 Q3 04 Decoding Read register T to process lean data Write to destination Example: INCF CNT, 1, 0 Before instruction

CNT = 0xFF Z = 0 C =? DC =?

After the instruction, CNT = 0x00, Z = 1, C = 1, DC = 1, INCFSZ: Increment f, and the fruit is 0. The syntax is: [Mark] INCFSZ f, d, a Operand: 0 < fS255 96779.doc -39 -200530920 de [05l] ae [0, l] Operation: (f) + l- &d; dest, if the result is # 0, then the affected state is skipped: No coding · 0011 llda ffff ffff Description: Decrement register T content. If fd 'is 0, the result is placed in W. If fd 'is 1, the result is placed back in the register T (default). If the result is 0, the next fetched instruction is discarded and a NOP is executed instead, making it a one or two cycle instruction. If 'a' is 0, the virtual repository will be selected, overriding the BSR value. If Y is 1, the bank will be selected according to the BSR value (default).

Words: 1 Cycles: 1 (2) Remarks: If skipped, and followed by a 2 word instruction, it will be 3 cycles of Q cycle activity: Q1 Q2 Q3 Q4 Decoding read register T processing data no operation if skip Over: Q1 Q2 Q3 Q4 No operation No operation No operation No operation If skipped and followed by a 2-word instruction: Q1_Q2_Q3_Q4 No operation No operation No operation No operation No operation No operation No operation No operation No operation Example: HERE INCFSZ CNT, 1, 0 96779.doc -40- 200530920 NZERO: ZERO: PC = Address (HERE) before the instruction CNT = CNT + 1 if the CNT = 0;

PC = Address (ZERO) If CNT ^ O; PC = Address (NZERO) INFSNZ ·· Increment f, if it is not 0, skip syntax: [tag] INFSNZ f, d, a Operand: 0sf < 255 de [0? L] ae [0, l] Operation: (f) + l- &d; dest, if the result is # 0, then the affected state is skipped: no stone horse · 0100 10da ffff ffff Description: Decrement temporary storage Contents of the device T. If 'd' is 0, the result is placed in W. If 'd' is 1, the result is placed back in the register T (default). If the result is 0, the next fetched instruction is discarded and a NOP is executed instead, making it a one or two cycle instruction. If V is 0, the 96779.doc -41-200530920 virtual repository will be selected, overriding the BSR value. If 'a' is 1, the bank will be selected according to the BSR value (default).

Words: 1 Cycles: 1 (2) Remarks: If skipped and followed by a 2 word instruction, it will be 3 cycles Q cycle activity: Q1_Q2_Q3_Q4_

Decode and read register processing data without operation T If skipped: Q1 Q2 Q3 Q4 No operation No operation No operation No operation If skipped and followed by 2 word instruction: Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation Example: HERE INFSNZ REG, 1, 0 ZERO: NZERO: POAddress (HERE) before the instruction REG = REG + 1 after the instruction, if REG々0; PC = Address (NZERO) if the REG = 0 ; 96779.doc -42- 200530920 PC = Address (ZERO) IORLW: Integer OR operation between text and W Syntax: [Mark] IORLWk Operand: 0 ^ 1 ^ 255

Operation: (W) · OR · k—W

Affected status: N, Z 0000 1001 kkkk kkkk

Explanation ... OR the contents of W and the octet character V. Place the result in W.

Words ·· 1 Cycles: 1 Q cycle activity:

Qi Q2 Q3 Q4 Decode Read text T Process poor data Write to w Example · IORLW 0x35 Before instruction

After W = 0x9A instruction

W = 0xBF IORWF: W and f are included in the OR operation. Syntax: [label] IORWF f, d, a operand ... 〇sfS255 96779.doc -43- 200530920 de [0? L] ae [0, l ]

Operation: (W) .OR. (F) —dest Affected state: N, Z 0001 OOda ffff ffff Description: Performs an OR operation on W and the register T. If 'd' is 0, the result is placed in W. If it is 1, the result is placed back in the register T (default). If faf is 0, the virtual repository will be selected, overriding the BSR value. If Y is 1, the bank will be selected according to the BSR value (default).

Words · 1 cycle: 1 Q cycle activity:

Ql Q2 Q3 Q4 Decode and read register T process data to write to the destination Example: IORWF RESULT, 0, 1 Before instruction RESULT = 0xl3 W = 0x91 After instruction RESULT = 0xl3 W = 0x93 MOVF: Move f Syntax: [Mark ] MOVF f, d, a 96779.doc -44- 200530920

Operand: 〇SfS255 de [05l] ae [0? L] Operation: f- > dest Affected state: N, Z 0101 OOda ffff ffff Description: Move the contents of the register T according to the state of 'd' To a destination. If 'd' is 0, the result is placed in W. If 'Shi Department 1', the result is placed back in the register 'f (default). The position T can be any position in the 256-byte bank. If 'a' is 0, the virtual repository will be selected, overriding the BSR value. If 'a' is 1, the bank will be selected according to the BSR value (default).

Words' 1 Cycles: 1 Q cycle activity:

Qi Q2 Q3 04 Decoding Read register T Handle lean data Write w Example: MOVF REG 0, 0 Before instruction REG = 0x22

After W = 0xFF instruction, REG = 0x22 W = 0x22 96779.doc -45-200530920 MOVFF: Move f to f Syntax: [Mark] MOVFF fs, fd Operand: 0 < fs < 4095, 0 < fd ^ 4095 Operation: ( fs) —fd Affected state: No stone horse · First character (source) 1100 ffff ffff ffffs Second character (destination) 1111 ffff ffff ffffd Description: Move the contents of the source register, fs, To the destination register, fd. The location of the source register fs can be anywhere in the 4096-byte data space (Xianxian to Jixian) ', and the location of the destination register' fd 'can also be anywhere from Xingxian to Bang. The source or destination register can be a W register (a useful special case). MOVFF is particularly useful for transferring a data memory location to a peripheral register (such as a transfer register or an I / O port). The MOVFF instruction cannot use PCL, TOSU, TOSH, or TOSL as destination registers.

Words: 2 Number of cycles: 2 (3) Q cycle activity: decode read register | f (src) process data Q4 no operation decode no operation no dummy read no operation write to register ff (dest) 96779. doc 200530920 Example: MOVFF REGl, REG1 = 0x33 before REG2, REG2 = 0xll, REGl = 0x33, REG2 = 0x33 after instruction

MOVLB: Move text to the lower nibble in BSR Syntax: [Mark] MO VLB k Operand ·· 0 ^ 1 ^ 255

Operation: k—BSR Affected state: None 0000 0001 kkkk kkkk

Description: Load 8-bit text 1k ’into the bank selection register (BSR). Words · 1 cycle: 1 Q cycle activity:

Q1 Q2 Q3 Q4 Decode and read text 'kf Process data write text' k to BSR Example: MOVLB 5 BSR register before instruction = 0x02 96779.doc -47- 200530920 BSR register after instruction = 0x〇5 LFSR: Move text to FSR Syntax: [Mark] LFSR f, k Operand: 0sfS2 0 < k < 4095 Operation: k- > FSRf Affected state: No coding: 1110 1110 OOff Knkkk 1111 0000 k7kkk kkkk Description: Load the 12-bit text, k, load, and file pointed by f to the register. Words: 2 Cycles: 2 Q cycle activities:

Decode Read text 1’MSB Xi__ Process data Q4 Write text V MSB to FSRfH Decode Read text Process data Write text V to FSRfL Example · LFSR2, 0χ3ΑΒ After the instruction

FSR2H = 0x03

FSR2L = 0xAB MOVLW: Move text to W Syntax: [Mark] MOVLWk 96779.doc -48- 200530920 Operand: 0 ^ 1 ^ 255 Operation: k- > W Affected state: None 0000 1110 kkkk kkkk Explanation: will The octet literal 'k' is loaded into W.

Words: 1 cycle number: 1 Q cycle activity: Q1_Q2_Q3_Q4

Decode Read text 'k' Process data Write to W

Example: After MOVLW 0x5A instruction

W = 0x5A MOVWF: Move W to f Syntax: [Mark] MOVWF f, a Operand: 0sf < 255 ae [0, l] Operation: (W) Affected state: None 0110 1101a ffff ffff Description: Data Move from W to register T. Position 'f can be any position in the 256-byte bank. If fa 'is 0, the virtual repository will be selected, overriding the BSR value. If 'a' = 1, the repository will be selected according to the BSR value (pre-set 96779.doc -49- 200530920).

Words · 1 Number of cycles: 1 Q cycle activity: Q1 Q2 Q3 Q4 Decoding Read register ‘f Process poor data Write register’ f Example: MOVWF REG, 0 before the instruction W = 0x4F #

After REG = 0xFF instruction W = 0x4F REG = 0x4F MULLW: Multiply text by W Syntax: [Mark] MULLWk Operand: 0% 255 ·

Operation: (W) xk—PRODH: PRODL Affected state: None. Shima · 0000 1101 kkkk kkkk Description: Perform an unsigned multiplication between the content of W and the 8-bit text T. Place the 16-bit result in the PRODH: PRODL register pair. PRODH contains high-order bytes. W is unchanged. None of the status flags are affected. It should be noted that it is not possible to have 96779.doc -50- 200530920 overflow and carry in this operation. There may be zero results, but they are not detected. Words · 1 cycle: 1 Q cycle activity:

Q1 Q2 03 Q4 Decode Read text ‘k’ Process data Write to register PRODH: PRODL Example: MULLW 0xC4 Before instruction W = 0xE2 φ PRODH =? PRODL =? After instruction W = 0xE2

PRODH = OxAD PRODL = 0x08 MULWF ·· Multiply W by f Φ Syntax: [Mark] MULWF f, a Operand: 0 ^ ί ^ 255 ae [0, l]

Operation: (W) x (f) ~> PRODH: PRODL Affected state: None 0000 001a ffff ffff Description: Perform an unsigned multiplication between the contents of W and the register file position T. 96779.doc -51-200530920 Store the 6-bit result in the PRODH: PRODL register pair. PRODH contains a high mind. constant. The status flags are not affected. Respond to the main idea, there is no overflow or carry in this operation. There may be no results, but no detection. If, a, is 0, the BSR value of the back cover of the virtual wealth subbank will be selected. If a, =: i, the repository will be selected according to the BSR value (default).

Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 _ -1- | Write to register PRODH: PRODr ^ Example: MULWF REG, 1 before instruction W = 0xC4 REG = 0xB5 PRODH =? PRODL =? After instruction W = 0xC4 REG = 0xB5

PRODH = Ox8A PRODL = Ox94 NEGF: Negative f 96779.doc • 52 · 200530920 Syntax · [Mark] NEGF f, a Operand: 0SfS255 ae [0, l] Operation: (7) + l—f

Affected states: N, OV, C, DC, Z. Shima · 0110 110a ffff ffff Description: Use two's complement to negate the position 'f. Place the result in data memory location T. If 'a' is 0, the virtual repository will be selected, overriding the BSR value. If so, the repository will be selected according to the BSR value.

Words: 1 Number of cycles: 1 Q cycle activity: Q1 Q2 Q3 Q4 Decode read register 'f Process lean write register' f Example: NEGF REG, 1 before instruction REG = 0011 1010 [0x3A] After instruction REG = 1100 0110 [0xC6] NOP: no operation syntax: [mark] NOP operand: no operation: no operation 96779.doc -53- 200530920 Affected status: no stone horse

0000 0000 0000 0000 1111 XXXX XXXX XXXX Description: No operation.

Words: 1 Cycles: 1 Q Cycle Activities: Q1 Q2 Q3 Q4

Decoding 丨 No operation | No operation 丨 No operation Example: None. POP: Remove the top of the stack. Syntax: [Mark] POP Operand: No operation: (TOS) —Bit bucket Affected state: No coding: 1 0000 1 0000 1 0000 1 Olio Description: Pull TOS from the return stack Value and discard. The TOS value then becomes the previous value that was pushed back into the stack. This instruction is provided so that the user properly manages the return stack to merge into a software stack.

Words: 1 Cycles: 1 Q cycle activities: 96779.doc -54- 200530920

Q1 Q2 03 04 Decode No operation POP T0S value No operation Example: POP

TOS = 0031A2h before GOTO NEW instruction

Stack (lolevel down) = 014332h After instruction TOS = 014332h #

PONEW

PUSH: Push back to the top of the stack. Syntax [Mark] PUSH Operand: No operation: (PC + 2) —TOS Affected state: No stone horse. 0000 0000 0000 0101 Description: Push PC + 2 Return to the top of the stack. Push the previous TOS value down into the stack. This instruction allows a software stack to be implemented by modifying TOS and then pushing it onto the return stack.

Words: 1 Cycles: 1 Q cycle activity: 96779.doc -55- 200530920 Q1 Q2 Q3 04 Decoding Push PC + 2 back to the stack No operation No operation

Example: Before PUSH instruction TOS = 00345Ah PC = 000124h After instruction PC = 000126h TOS = 000126h

Stack (l level down) = 00345Ah State: None 1101 lnnn nnnn nnnn RCALL: branch subroutine syntax: [mark] RCALLn operand: -1024 < η < 1023 operation: (PC) + 2—TOS, (PC) + 2 + 2n- > PC affected stone horses Description: Jump to the next normal call up to 1K from the current position. First, push the return address (PC + 2) onto the stack. Then, 2's complement '2n' is added to the PC. Because the PC has been incremented to fetch the next instruction, the new address will be PC + 2 + 2n 〇 itb means ♦ is a 〇

Words: 1 Number of cycles: 2 Q cycle activities: 96779.doc -56- 200530920 Q1 02 Q, 3 Q4 Decode and read the text fn 'Push the PC to the stack to process the data to write to the PC No operation No operation No operation No operation No operation example ·· PC = Address (HERE) before the HERE RCALL Jump instruction PC = Address (Jump) TOS = Address (HERE + 2) after the instruction RESET: Reset Syntax: [Mark] RESET Operand: None Operation: Reset is subject to ^ ^ Reset all registers and flags affected. Affected states: All 0000 0000 1111 1111 Description: This command provides a way to perform reset by software. Words · 1 Cycles: 1 Q Cycle Activity: Q1 02 Q3 Q4 Decoding Start reset No operation No operation

Example: After RESET instruction 96779.doc -57- 200530920

Registers: Reset value Flags * = Reset value RETFIE ·· Return from interrupt Syntax: [Mark] RETFIE s Operand: se [0.1] Operation: (TOS) ^ PC, 1-> GIE / GIEH or PEIE / GIEL If s = 1 (WS) —W, (STATUSS)-> STATIS, (BSRS) aBSR, PCLATU and PCLATH remain unchanged. Affected states: GIE / GIEH, PEIE / GIEL, STATUS reg. 0000 0000 0001 000s Description: Return from interrupt. Remove the stack and load the top of the stack (TOS) into the PC. Interrupts are initiated by setting high or low priority global interrupt enable bits. If 's, == l, the contents of the shadow register ws, STATUSS and BSRS will be loaded into their corresponding registers w, STATUS and BSR. If V = 0, these registers are not updated (default).

Words: 1 Number of cycles: 2 Q cycle activities: 96779.doc • 58-200530920 Q1 02 〇3_ Q4 Decode No operation No operation Remove PC from the stack Set GIEH or GIEL No operation No operation Operation No operation Example: After the RETFIE Fast instruction

PC = TOS w = ws BSR = BSRS STATUS = STATUSS GIE / GIEH, PEIE / GIEL = 1 RLCF: Rotate f to the left by carry Syntax: [Mark] RLCF f, d, a Operand: 〇 ^ f ^ 255 de [ 0, l] ae [0, l] Operation: (f < n >) 4dest < n + 1 >, (f < 7 >)-c, (c) 4dest < 〇 > Affected states: C, N ， Z 石 石 马 · ~ oo 11 r〇Td ^ ~ \ Jm I ffff

Rotate the contents of the register T to the left by the carry flag through the carry flag, and the result is placed in w. If w is 1, the result is stored in the memory T (default). If 'a' is 0, the virtual repository will be selected and the BSR value will be ticked. If ‘a’ = l, the repository will be selected according to the BSR value (pre-emption 96779.doc -59- 200530920

cSi register f—H

Words: 1 Cycles: 1 Q cycle activity:

Qi Q2 03 Q4 Decode Read register T to process data Write to destination Example: RLCF REG, 0, 0 Before the instruction

REG = 1110 0110 C = 0 After the instruction REG = 1110 0110 W = 1100 1100 C = 1 RLNCF: rotate f to the left (no carry)

Syntax: [Mark] RLNCF f, d, a Operand: 0 ^ f ^ 255 de [0, l] aG [0, l]

Operation: (f < n>) ~ > dest < n + l>, (f < 7 >)-&d; dest < 0 > Affected state: N, Z 0100 Olda ffff ffff 96779.doc -60 · 200530920 Explanation: Use the carry flag to rotate the contents of the register one bit to the left. If 'd' is 0, the result is placed in W. If fd 'is 1, the result is stored back in the register τ (default). If it is not 0, the virtual repository will be selected, overriding the BSR value. If 1, the repository will be selected according to the BSR value (default). pH register Fki

Words · 1 cycle: 1 Q cycle activity:

Ql Q2 Q3 Q4 Decoding Read register’f Process data Write to destination Example: RNLCF REG, 1, 0 Before the instruction REG = 1010 1011 After the instruction REG = 0101 0111

RRCF: Rotate f right by carry Syntax: [Mark] RRCF f, d, a Operand: 0 ^ f ^ 255 de [0, l] ae [0, l]

Operation: (f < n>)-> dest < nl〉, (f < 0>)-> C, (C)-> dest < 7 > Affected states: C, N, Z 0011 OOda ffff ffff 96779.doc -61-200530920 Description: Use the carry flag to rotate the contents of the register T one bit to the left. If 'd' is 0, the result is placed in W. If 'df is 1, the result is stored back in register T (default). If fa 'is 0, the virtual repository will be selected, overriding the BSR value. If 'a' = 1, the repository will be selected according to the BSR value (default). H1K register f

Words: 1 Cycles: 1 Q cycle activity:

Ql Q2 Q3 Q4 Decode and read register T process data to write to the destination Example: RRCF REG, 0, 0 REG = 1110 0110 before the instruction C = 0 REG = 1110 0110 W = 0111 0011 after the instruction C = 0 RRNCF: Rotate f (without carry) to the right Syntax: [Mark] RRNCF f, d, a Operand: 0sfS255 dE [0, l] ae [0, l] 96779.doc -62- 200530920 Operation: (f < n> ) ~ ^ Dest < n + l〉, (f < 0〉)-&d; dest < 7 > Affected states: N, Z Stone horse · 0100 OOda ffff ffff Description: Register will be saved by the carry flag 〒 The content is rotated one bit to the left. If fd 'is 0, the result is placed in W. If ′ is Department 1, the result is stored back in register T (default). If 'a' is 0, the virtual repository will be selected, overriding the BSR value. If fa '= l, the repository will be selected according to the BSR value (default). f Register.

Words: 1 Cycles: 1 Q cycle activity:

Qi Q2 Q3 Q4 Decode and read register τ Processing data is written to the destination Example 1: RRNCF REG, 1, 0 REG before the command = 1101 0111 REG after the command = 1110 1011 Example 2: RRNCF REG, 0, 0 before the command W =? REG = 1101 0111 After the instruction W = 1110 1011 96779.doc -63- 200530920 REG = 1101 0111 SETF: Set f Syntax: [Mark] SETF f, a Operand: 0sf < 255 de [0, l] ae [0, l]

Operation: FFh- > f Affected state: None 0110 100a ffff ffff Description: Set the content of the specified register to FFh. If fa 'is 0, the virtual repository will be selected, overriding the BSR value. If Y is 1, the bank will be selected according to the BSR value (default).

Words: 1 Cycles: 1 Q cycle activity:

Ql Q2 03 Q4 Decode Read Register ‘f Process Data Write Register’ f Example: SETF REG, 1 before instruction

After REG = 0x5A instruction

REG = 0xFF 96779.doc -64- 200530920 SLEEP: Enter SLEEP mode syntax ... [mark] SLEEP operand: None 0000 0000 0000 0011 Operation: OOh — WDT, 0 — WDT post-divider, 0 — both affected Status: ¥ 5 Editing Stone Horse Description: Clear the power saving status bit (%). Set the timeout status bit (ra). Clear the watchdog timer and its divider. Put the processor into SLEEP mode and disable the oscillator.

Words · 1 Cycles: 1 Q cycle activity: Q1 Q2 Q3 Q4 Decoding No operation Processing data Go to sleep

Example: Before the SLEEP instruction ΊΌ = Ί ρό = ί After the instruction ΊΌ = \ + PD = 0 + If WDT causes wake-up, clear this bit SUBFWB: Use borrow to subtract f 96779.doc -65- 200530920 Syntax: [Label] SUBFWB f, d, a operand: 〇sfS255 de [0, l] ae [0? L]

Operation: (W)-(f)-(0)-&d; dest Affected states: N, OV, C, DC, Z. Shima · 0101 01 da ffff ffff Description: Subtract register T from W With carry flag (borrow) (2's complement method). If, d 'is 0, the result is stored in W. If fd 'is 1, the result is stored in the register T (default). If faf is 0, the virtual repository will be selected, overriding the BSR value. If Y is 1, the bank will be selected according to the BSR value (default).

Words: 1 Cycles: 1 Q cycle activity:

Ql Q2 Q3 04 Decode Read register T Process data Write to destination

SUBFWB Example 1: SUBFWB REG, 1, 0 Before the instruction REG = 3 W = 2 C = 1 96779.doc -66- 200530920 After the instruction

REG = FF W = 2 C = 0 Z = 0

N = 1; The result is negative Example 2: SUBFWB REG, 0, 0 Before the instruction REG = 2 W = 5 C = 1 After the instruction REG = 2 W = 3 C = 1

z = o N = 0, the result is positive Example 3: SUBFWB REG, 1, 0 REG = 1 before the instruction = W = 2 C = 0 REG = 0 after the instruction = 96779.doc -67- 200530920 W = 2 C = 1 = 1, the result is zero N = 0 SUBLW: Subtract W from text Syntax: [Mark] SUBLWk Operand: 0 ^ 1 ^ 255 Operation: k- (W)-> W Affected states: N, OV, C , DC, Z Editing Shima · 0000 1000 kkkk kkkk Description: Subtract W from the octet text 'k'. Place the result in W. Words · 1 cycle: 1 Q cycle activity:

Qi Q2 Q3 Q4 Decode and read the text 'k' Processing data is written to W Example 1: SUBLW0x02 W = 1 before the instruction ○? W = 1 C = 1 after the instruction; the result is positive -68- 96779.doc 200530920 z = o N = 0 Example 2: SUBLW 0x02 W = 2 before the instruction C =? W = o after the instruction

C = 1; the result is zero Z = 1 N = 0 Example 3: SUBLW 0x02 W = 3 before the instruction C =?

After the instruction W = FF; (2's complement) c = o, the result is negative z = o N = 1 SUBWF: Subtract W from f Syntax: [Mark] SUBWF f, d, a Operand ·· 0 ^ f ^ 255 96779.doc -69- 200530920 de [0, l] ae [0,1] Operation: (f)-(W)-&d; dest

Affected states: N, OV, C, DC, Z 0101 llda ffff ffff Description: Subtract W (2's complement method) from register 'f. If 'd' is 0, the result is stored in W. If 'd' is 1, the result is stored back in register T (default). If 'a' is 0, the virtual repository will be selected, overriding the BSR value. If 'a' is 1, the bank will be selected according to the BSR value (default).

Words: 1 Number of cycles: 1 Q cycle activity: Q1 Q2 Q3 Q4 Decode and read register T process data to write to the destination Example 1: SUBWF REG, 1, 0 REG = 3 before the instruction W = 2 O? After the instruction REG = 1 W = 2 C = 1; The result is positive z = o 96779.doc -70- 200530920 N = 0 Example 2: SUBWF REG, 0, 0 REG = 2 before the instruction W = 2 C =? REG = after the instruction 2 W = 0 C = 1; the result is zero ζ = ι N = 0 Example 3: SUB WF REG, 1, 0 REG = 1 before the instruction W = 2 C =? REG = FFh after the instruction; (2's complement) W = 2 c = o, the result is negative z = o N = l 96779.doc 200530920 SUBWFB: Subtract W from f using borrowing Syntax: [Mark] SUBWFB f, d, a Operand: 0sf < 255 de [ 0? L] ae [0? L]

Operation: (f > (WH5)-&d; dest Affected states: N, OV, C, DC, Z 0101 10da ffff ffff Description: Subtract W and carry flag (borrow) from register T (2) Complement method). If it is 0, the result is stored in W. If 'd' is 1, Beck stores the result back to register T (default). If 'a' is 0, it will be selected Virtual repository, which overrides the BSR value. If 'a' is 1, the repository will be selected according to the BSR value (default).

Words: 1 Cycles: 1 Q cycle activity:

Qi Q2 Q3 04 Decoding Read register’f Process data Write to destination

SUBWFB Example 1: SUBWFB REG, 1, 0 REG = 0xl9 (0001 1001) W = 0x0D (0000 1101) 96779.doc -72- 200530920 c = i REG = 0x0C (0000 1011) W = 0x0D (0000 1101) C = 1 Z = 0

N = 0, the result is positive Example 2: SUBWFB REG, 0, 0 Before the instruction REG = 0xlB (0001 1011) W = 0xlA (0001 1010) C = 0 After the instruction REG = 0xlB (0001 1011) W = 0x00

C = 1 Z = 1, the result is zero N = 0 Example 3: SUBWFB REG, 1, 0 REG before the instruction 0x03 (0000 0011) W = 0x0E (0000 1101) C = 1 after the instruction 96779.doc -73- 200530920 REG = 0xF5 (1111 0100) (2's complement) W = 0x0E (0000 1101) C = 0 Z = 0 N = 1; the result is negative SWAPF: exchange f syntax: [mark] SWAPF f, d, a operand ： 0SfS255 de [0? L] ae [0? L] operation ·· (f < 3: 0〉)-> dest < 7: 4〉, (f < 7: 4 >) 4dest < 3: 0> accept Affected state: None 0011 10da ffff ffff Description: Swap the register, the upper and lower nibble of f. If fd 'is 0, the result is placed in W. If W is 1, the result is placed in register T (default). If Y is 0, the virtual repository will be selected, overriding the BSR value. If 'af is 1, the bank will be selected according to the BSR value (default).

Words: 1 Number of cycles: 1 Q cycle activity: Q1 Q2 Q3 Q4 Decoding read register T Processing lean data to write to the destination Example 1: SWAPF REG, 1, 0 96779.doc -74- 200530920 REG = before instruction 0x53 REG = 0x35 after instruction TBLRD: Table read syntax: [Mark] TBLRD (*; * +; *-, + *) Operand: No operation: If TBRRD *, "Prog Mem (TBLPTR)) ^ TABLAT TBLPTR- no change; if TBLRD * +, then (Prog Mem (TBLPTR))-> TABLAT; (TBLPTR) + 1 ^ TBLPTR; if TBRRD *-, J (Pr0g Mem (TBLPTR))- >TABLAT; (TBLPTR) -1- >TBLPTR; if TBLRD + *, then (TBLPTR) + 1-TBLPTR; (Prog Mem (TBLPTR))->TABLAT; Affected status: No coding: 0000 0000 0000 10nn nm = 0 * = 1 * + = 2 *-= 3 + * Explanation ·· The TBLRD instruction has four options to determine what happens to the 21-bit table index (TBLPTR): no change, post-increment, post-decrement, and pre-increment . Decide the current option, modify TBLPTR appropriately, and load the contents of the program memory location pointed by TBLPTR to 96779.doc -75- 200530920 into the 8-bit table latch (TA BLAT). The LSb of TBLPTR selects which type of program memory location will be read. If LSb = 1, load the high byte into TABLAT. If LSb = 0, load the low byte into TABLAT 〇Words: 1 number of cycles : 2 Q cycle activities:

Qi Q2 03 04 Decoding No operation No operation No operation No operation No operation No operation No operation No operation (Operation on the table of the address bus) (Han becomes low) TABLAT Update TBLRD: Table reading example 1: TBLRD * +; Before the instruction TABLAT = 0x55 · TBLPTR = 0x00A358 MEMORY (OxOOA356) = Ox34 After the instruction TABLAT = 0x34 TBLPTR = 0x00A357 Example 2: TBLRD + *; Before the instruction

TABLAT = 0xAA 96779.doc -76- 200530920 TBLPTR = 0x01A357 MEMORY (0x01A357) = 0xl2 MEMORY (0x01A358) = 0x34 TABLAT = 0x34 TBLPTR = 0x01A358 TBLWT: Table write syntax: [Mark] TBLWT (*; * +; *-, + *) Operand: No operation: If TBLWT *, (TABLAT)-»(ProgMem (TBLPTR); TBLPTR-No change; if TBLWT * +, (TABLAT)-> (Pr〇g Mem (TBLPTR ); (TBLPTR) +1->TBLPTR; if TBLWT *-, (TABLAT)-> (Prog Mem (TBLPTR); (TBLPTR) -l->TBLPTR; if TBLWT + *, (TBLPTR) +1- >TBLPTR; (TABLAT)-> Prog Mem (TBLPTR); Affected status: No coding: 0000 0000 0000 linn ηη = 0 * = 1 * + = 2 *-= 3 + * Explanation: There are four TBLWT instructions The choice determines the 21-bit table index (TBLPTR) issue 96779.doc -77- 200530920. No change, post-increment, post-decrement, and pre-increment. Decide on the current options and modify the TBLPTR appropriately. Lock the table The contents of the register (TABLAT) are written into the program memory location pointed to by TBLPTR. If the BLPTR is pointed to an external program memory location, the Bayer instruction is executed in two cycles. Because TABLAT is only one byte wide, you must execute a multiple of two TBLWT instructions to program the internal memory location. For example, if you define the device as one word at a time, program an internal memory as follows Body position: 1) Set TBLPTR to an even number type

2) Write low byte to TABLAT 3) Execute TBLWT * + (2 cycles)

4) Write high byte to TABLAT 5) Execute TBLWT * + (long write) When an interrupt is received, long write to an internal EPROM location is terminated. The post-increment TBLWT instruction is the only TBLWT instruction recommended for internal memory writes. (Only devices with 64 or more pins can use the internal EPROM.)

Words: 1 TBLWT table write cycle number: 2 (If long write is for EPROM program memory, it takes many cycles) 96779.doc -78- 200530920 Q cycle activities:

Ql Q2 Q3 04 Decode No operation No operation No operation No operation No operation No operation No operation No operation (Operation on the address bus (Table table index on the address bus) Latch, · Go low) Example 1: TBLWT * +; Before order

TABLAT = 0x55 TBLPTR = 0x00A356 MEMORY (OxOOA356) = OxFF After the instruction (table writing is completed) TABLAT = 0x55 TBLPTR = 0x00A357 MEMORY (OxOOA356) = Ox55 Example 2: TBLWT + *; before the instruction

TABLAT = 0x34 TBLPTR = 0x01389A MEMORY (OxO 13 89B) = 0xFF MEMORY (0x01389A) = 0xFF After the instruction (table writing is completed) TABLAT = 0x34 TBLPTR = 0x01389B MEMORY (OxO 13 89 A) = 0xFF 96779.doc -79 200530920 MEMORY (0x01389B) = 0x34 TRAP: debug subnormal call syntax ·· [mark] TRAP operand: None

Operation: (PC) + 2- > TOS, 000028h- > PC < 20: l > Affected state: INBUG 0000 0000 1110 0000 Description: Debug the trap to 0028h. First, push the return address (PC + 2) onto the return stack. The 20-bit value '000028h' is then loaded into the PC < 20: 1 >. Set the INBUG status bit. TRAP is a two-cycle instruction.

Words: 1 Cycles: 2 Q cycle activities:

Ql 02 Q3 04 Decoding Push PC to stack No operation Write 000028h to PC No operation No operation No operation No operation

Example: Before HERE TRAP instruction PC = Address (HERE) After instruction PC = 000028h TOS = Address (HERE + 2) INBUG = 1 96779.doc -80- 200530920

TRET: Trap return syntax from the next normal ... [Mark] TRET operand: no operation: (T〇s)-> PC PCLATU, PCLATH is not affected Affected state: INBUG code: 0000 0000 1110 0001 Explanation: Return from debug trap. The stack is taken out and the top of the stack (TOS) is loaded into the program counter. Clear the INBUG status bit.

Words: 1 Number of cycles: 2 Q cycle activity: Q1 Q2 03 Q4 Decoding No operation No operation Remove the PC from the stack No operation No operation No operation No operation

Example: After TRET interrupt

PC = TOS INBUG = 0 TSTFSZ: 湏 ij try f, the fruit is 0, and the grammar is over: [tag] TSTFSZ f, a Operand: 0 ^ 0255 96779.doc -81- 200530920 a ,, l] operation : If f = 〇, skip the affected state: None 0110 011a ffff ffff Description: If τ = ο, discard the next instruction fetched during the current instruction execution and execute NOP to make it a Two-cycle instruction. If W is 0, the virtual repository will be selected, overriding the BSR value. If 'a' is 1, the bank will be selected according to the BSR value (default).

Words · 1 Cycles: 1 (2) Note: If skipped, followed by a 2-word instruction, it is a 3-cycle Q cycle activity: Q1 Q2_Q3_Q4 Decode Read Register τ Processing data No operation If skipped: Q1 02 Q3 Q4 No operation No operation No operation No operation If skipped and followed by a 2-word instruction • Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation No operation Example: HERE TSTFSZ CNT, 1 NZERO: ZERO: 96779.doc before the instruction -82- 200530920 After the POAddress (HERE) instruction, if CNT = 0x00, POAddress (ZERO) If the CNT = 0x00, PC = Address (NZERO) XORLW: Mutually exclusive OR of text and W Operation syntax: [Mark] XORLWk Operand: 0 place < 255

Operation ·· (W) .XOR. K- > W

Affected states: N, Z 0000 1010 kkkk kkkk Description: Perform X0R operation on the content of W and the 8-bit text V. Place the result in W.

Words: 1

Number of cycles: 1 Q cycle activities:

Q1 Q2 Q3 Q4 Decode Read text “k” Process data Write to W Example: Before XORLW OxAF instruction W = 0xB5 After instruction

W = 0xlA 96779.doc -83- 200530920 XORWF: mutually exclusive OR operation between W and f Syntax: [Mark] XORWF f, d, a Operand: 〇sfS255 de [05l] ae [0? L]

Operation: (W) .XOR · (f) —dest Affected state: N, Z 0001 10da ffff ffff Description: Perform a mutually exclusive OR operation on the contents of W and the register T. If fd 'is 0, the result is stored in W. If 'd' is 1, the result is stored back in the scratchpad (default). If 'a' is 0, the virtual repository will be selected, overriding the BSR value. If 'a1 is 1', the repository will be selected according to the BSR value (default). Words · 1 cycle: 1 Q cycle activity:

Ql Q2 Q3 Q4 Decode Read register T Process tribute Write to destination Example: XORWF REG, 1, 0 Before the instruction

REG = 0xAF W = 0xB5 After the instruction

REG = 0xlA W = 0xB5 96779.doc • 84-

Claims (1)

200530920 10. Scope of patent application: 1. A micro-controller, including a central processing unit; 'data memory, which has a linearized address space and is coupled with the central processing unit. The data memory system is divided into η Repositories; the central processing unit includes a repository selection unit that accesses the _reservoir or accesses a virtual repository, whereby the virtual repository combines two robust repositories of the data memory Part of the memory space, and in which the selected storage bank forms a register file; an arithmetic logic unit, which is coupled to the register file; a plurality of special function registers, which are mapped to the data memory One of the repositories in the system, one of the special function registers is a working register coupled with the arithmetic logic unit; the% type δ ten register register is located in the central processing unit. In the unit, the program counter is mapped in the data memory; and a work register, which is located in the central processing unit and is coupled with the arithmetic logic unit, the work The memory is mapped in the data memory; 隹 wherein the micro-controller has an instruction for controlling the arithmetic logic unit; 包含 at least one of the instructions includes a bit, which indicates the repository σσ-g,疋 Whether to access one of the repositories or the virtual repository, in which the command set includes a command with the code 1110 1010 kkkk kkkk, when calling this command, copy an 8-bit text to a file Select 96779.doc 200530920 to select the location pointed to by the register, and then decrement the file selection register. Specify the text, k, in the kkkk kkkk part of the instruction. 2. If the microcontroller of item 1 is required, the instruction set includes-an instruction with a code of 1110 1001 ffkk kkkk, wherein when calling this instruction, a 6-bit register is subtracted from the first register. Symbolize the text to form a result. The result is stored in the file selection register. Specify the text in the kk kkkk 4 command of the instruction, and specify the file selection register in the 忏 part of the instruction. 3. The micro-controller as claimed in claim 1, wherein the instruction set includes an instruction with a code of 1110 1001 1 Ikk kkkk, wherein when the instruction is called, an unsigned 6-bit text is subtracted from a file selection register. To form a result, the result is stored back in the file selection register and returned, and the text is specified in the kk kkkk portion of the instruction. 4. The micro controller of the request item, wherein the instruction set includes an instruction with a code of 1110 1000 ffkk kkkk, and when the instruction is called, _unsigned 6-bit text is added to a file selection register, The result is stored in the building selection register, the text is specified in the kk kkkk part of the instruction, and the file selection register is specified in the ff part of the instruction. 5. As in the microcontroller of claim 1, wherein the instruction set includes an instruction with a code of 1110 1000 1 1 kk kkkk, wherein when the instruction is invoked, an instruction specified by the kk kkkk portion of the A command is used. The 6-bit text is added to the case selection register on the first floor and the result is stored back to the case selection register. 6. The microcontroller according to claim 1, wherein the instruction set includes an instruction with a code of 1110 1011 Osss SSSS 1111 dddd dddd dddd, of which 96779.doc 200530920 uses this instruction to copy an 8-bit value to A destination specified by the 12-bit value dddd dddd dddd, a value specified by adding the 7-bit text value sss ssss to a file selection register, and the 8 specified to be copied to the destination The position of the bit value. For example, the microcontroller of claim 1, wherein the instruction set includes an instruction having a code 1110 1011 lsss ssss 1111 χχχχ xddd dddd, wherein when the instruction is called, an 8-bit value is copied to a ddd by the instruction The position specified by the dddd section determines the position of the 8-bit value by adding the 7-bit text value sss ssss to a value in a file selection register. 8. The microcontroller of claim 1, wherein the instruction set includes an instruction with a code of 0000 0000 0001 0100, and when the instruction is called, the address of the next instruction is pushed onto a hardware stack. This instruction set includes a micro-controller with 9 · such as request item 1, "code 0__0 0___ instruction, wherein when calling this instruction, the value from-the: register is copied to a program counter comparison The higher 16-bits' and a value in a second register is copied to the lower 8-bits of the process. T benefit 10 ·-a microcontroller, which includes: a central processing unit;- -Combined, the memory system is divided into n repositories; the central processing unit includes two repositories selection units, which are used to select the data: one of the shai temple repositories, where the selected storage is The library forms 96779.doc 200530920 device file; and the material memory: arithmetic logic unit, which is integrated with this register. Several special function registers are mapped to one of the repositories. ; X, one of these special function registers is a working register; and one is an arithmetic logic unit and the instruction set includes a register with a 'where the instruction is called, the selection register is pointed to Where the microcontroller has a Order set, code 1110 101 〇kkkk kkkk instructions-copy 8-bit text to a file, and then decrement the file selection register. Specify the text, k, in the kkkkkkkk part of the instruction. 11 · For example, the micro controller of the request item U), wherein the instruction set includes an instruction with a code of 1110 1001 1001 ffkk kkkk, and when the instruction is called, a 6-bit unsigned text is subtracted from a file selection register to A result is formed, the result is stored in the file selection register, the text is specified in the kk kkkk part of the instruction, and the file selection register is specified in the ff part of the instruction. 12 · As requested item 1 〇 Microcontroller, wherein the instruction set includes an instruction with a code of 1110 1001 llkk kkkk, wherein when the instruction is called, an unsigned 6-bit text is subtracted from a file selection register to form a result, the The result is stored back in the slot selection register and returned, and the text is specified in the kk kkkk part of the instruction. 13. As in the microcontroller of item 10, the instruction set includes a code with a code of 1110 lOO ffkkkkkk instruction, when calling this instruction, add a 6-bit text without 96779.doc 200530920 symbol to a file selection register, the result is stored in the file selection register, at kk kkkk of the instruction The text is specified in the section, and the file selection register is specified in the ff section of the instruction. 14. The microcomputer of claim 10, wherein the instruction set includes an instruction with a compilation of 1110 1000 llkk kkkk, where When the command is called, a 6-bit text specified by the kk kkkk part of the command is added to a file selection register and the result is stored back to the file selection register. 15. The microcontroller of claim 10, wherein the instruction set includes an instruction having a code of 1110 1011 〇SSS ssss 11U dddd dddd dddd, wherein when the instruction is called, an 8-bit value is copied to a The destination specified by the 12-bit value dddd dddd dddd specifies the 8-bit value to be copied to the destination by adding the 7-bit text value sssssss to the value in a file remote register. position. 16. The microcontroller according to claim 10, wherein the instruction set includes an instruction having a code of 1110 1011 lsss ssss 1111 χχχχ xddd dddd, wherein when the instruction is called, an 8-bit value is copied to a through the instruction The position specified by the ddd dddd part determines the position of the 8-bit value by adding the 7-bit text value sss ssss to a value in a file selection register. 17. The microcontroller of claim 10, wherein the instruction set includes an instruction having a code of 0000 0000 0001 0100, and when the instruction is called, the address of the next instruction is pushed onto a hardware stack. 1 8 · Microcontroller as claimed in item 10, wherein the instruction set includes an instruction with a code of 0000 0000 0001 0100, and when the instruction is called, the value from the 9679.doc 200530920 first register is copied to A program counter is higher in the 16 bits, and a value in a second register is copied to the lower 8 bits of the program register. 96779.doc