200523748 玖、發明說明 【發明所屬之技術領域】 本發明是有關於一種多裝置系統，且特別是有關於一 種採用了變速率資料傳送方式，使系統中的即時裝置能得 到快速有效的回應，以保證較高的匯流排頻率的多裝置系 統。 【先前技術】 半導體產業的迅速發展大大推動了積體電路設計業的 發展，特別是半導體產業中，深次微米（DSM ; Deep Sub - Micron) 技術的 出 現把單晶 片 系統 (System-on-Chip ; SoC)設計推到了積體電路設計的前 沿。單晶片系統技術，是把以前分散在多個不同的晶片上 的多個處理器集合在同一塊晶片上，以形成一個功能完 善、性月b優越的完整系統。由於卓晶片系統的物理面積和 封裝針腳相對於多晶片系統有大幅度的減少，使得整個系 統的生產成本也大幅降低。而另一方面，系統中智財模組 (Intellectual Property; IP)的重複使用也縮短了單晶片系統 的設計週期，使系統的設計成本也得以降低。 單晶片系統中可能包括各種處理器，如中央處理器 (CPU )、數位訊號處理器（DSP )和各種針對專 電路（職）[以及儲存單元，甚至可能包括各；内建 處理器核心（kernel)的子系統。整個系統規模的擴大使系 統的複雜性較之以前的多晶片系統高，因而如何合理有效 200523748 地調節系統中各個處理 裔或者疋子糸統的運行，在整個系 統設計過程中成為_個 术 ^ ^ 相虽重要的問題。匯流排架構是用 來達成系統中各個處理哭 益或者子糸統的相互通訊，包括指 令傳送和資料傳送。 在多裝置系統内，多伽酤 夕個裝置之間的訊號傳送中，向匯 ^發出#求/要求進行訊號傳送的裝置稱為主裝置；而 主裝置要求進仃訊號傳送的目標裝置則稱為從屬裝置。對 於多裝置的通訊常當县垃田 韦疋4木用仲裁器來對多個裝置發出的匯 流排使用請求作出判斷，* Μ J ^ 根據各種演算法決定給予匯流排 佔有權的裝置，缺德由谨π …、傻由獲传棱權的主裝置佔有匯流排與相 =的從屬裝置進行通訊。為了達到減小電路面帛、降低製 &成本的目的’多裝置系統中常常採用共用匯流排的方式 達成匯机排上各裝置的通訊；但在同一時間匯流排上只能 由個主裝置佔有匯流排進行通訊。另一方面，多裝置系 統中的各個裝置直木身性暫科、合# & L 一 衣夏八不豸注負就吊常各不相同，有的是輸入 輸出裝置如鍵盤、滑鼠或顯示器等，而有的是中央處理 器（πυ)和數位訊號處理器（Dsp)等，或是一些其他 .的子系統等。輸入輸出裝置對於匯流排的回應速度要求並 不高，因此它所需的頻寬並不要求很高，而中央處理器和 數位訊號處理器等處理器對即時回應速度有較高的要求， 相對地也#纟匯流排能夠為其提供高速頻寬。> 果把頻寬 要求高和頻寬要求不高或者還有一些對頻寬要求介於二者 T間的裝置直接同時連接到匯流排上’而同時由一個仲裁 器進行集中式仲裁，往往造成各種頻寬不同的裝置之間的 200523748 相互制約，而不能對即時裝置進行回應。 規入置日 υ / ’曰曰片糸統技術的發展使積體電路得以增加單位 面積功此，而市場需求又一起推動系統中更多功能的集 成夕功此的實現從硬體上而言，不可避免地要在系統中 加=更多用來執行各種功能的裝置。纟多裝置系統的匯流 排木構中如果主裝置和從屬裝置增多，資料傳送過程中 的佈線延遲就會對資料傳送速率產生較大的影響，因而引 起匯:L排的頻率迅速下降。％由於近年來在大型積體電路 中’系統頻率的大幅提高和佈線的密集，也使得佈線延遲 系、、充的傳輸延遲佔有的比例越來越高，導致系統傳 輸延遲的不確定性也相對增加。 【發明内容】 因此本發明的目的就是 送方法的多裝置系統，該系 分層仲裁並採用不同的速率 兩了匯流排的頻率，保證了 的回應速度。 在提供一種採用變速率資料傳 統對匯流排上的多個裝置進行 進行資料傳送，從一個方面提 對快速回應有較高要求的裝置 一艮據本發明之上述目的，提出一種多裝置系、统，至少 多ΓΛ仲裁器，用以對主裝置提出的匯流排使用請求採 立a 2裁的形式進行仲裁，並在較低層次的主裝置之間 個較低層仲裁’然後把較低層仲裁的仲裁結果 仲：：：的…的匯流排使用請求一起送入匯流排上 °行I同層仲裁；複數個主裝置，與匯流排相i| 200523748 並依頻寬要求的不同分為多個不同層次；以及複數個從屬 裝置’與匯流排相連，並依頻寬要求的不同分為多個不同 層次’且可通過匯流排與主裝置之間進行資料傳送運算。 層次較高的主裝置和層次較高的從屬裝置之間的通訊採用 較高的資料傳送速率·，層次較低的主裝置與從屬裝置之間 的通訊或主裝置與層次較低的從屬裝置之間的通訊則採用 較低的資料傳送速率。 另外，根據本發明之上述目的，提出一種物理佈局，較 南層次的主裝置和較高層次的從屬裝置離匯流排上的仲裁 器較近，而較低層次的主裝置和較低層次的從屬裝置離匯 流排上的仲裁器較遠。 < 。，八n ΊΤ两 制，例如在仲裁器中進一步設有反向仲裁模組，從屬袭 為回應主裝置所發出的讀運算請求而回傳讀數據時，； 向反向仲裁模組申請匯流排佔用。反向仲裁的 依據主裝置和從屬裝置間的資料傳送速率來決定。 因=，頻寬要求較高的主裝置和從屬裝置^間 採用較尚的資料傳送速率，能夠报 算’同時，從物理佈局上，較高層次的主；成二：傳送 的從屬裝置離匯流排仲裁器較近，受到佈n 相對減小，因此能夠充分地滿足此類裝置的頻響 頻寬要求較低的主裝置和從屬裝置雖然離匯=要求。1 遠，但採用了較低的資料傳送速率，主署机仲裁器与 間的資料傳送時間受佈線延遲的^淨從屬裝置4 办響同樣有所減少，使衣 200523748 系統傳輸延遲的不確定性也能相對降低 【實施方式】 請參照第！圖’本發明實施例的多裝置系統包括一匯流 排1〇卜與匯流排101相連的仲裁器114，以及分別與匯流 排HH相連的主裝置Al02、主裝置B 1〇3、主裝置C 1〇4、 主裝置D1〇5、主裝置E106、主裝置F1〇7和從屬裝置A 108、從屬裝置B 109、從屬裝置c 11〇、從屬裝置d ιη、 從屬裝置Ε Π2、從屬裝置F 113。其中，主裝置可以是 CPU、請、ASIC或者是子系統等；從屬裝置可以是同步 動態隨機存取記憶體（SDRAM)或直接記憶體存取（dma) 等裝置。匯流排上的仲裁器，可以對連接在匯流排上的各 裝置所提出的匯流排使用請求做出仲裁，經仲裁選中的主 裝置佔有匯流排與對應的從屬裝置進行資料傳送。 主裝置可以分成重要主裝置和次要主裝置。本實施例 中’主裝置A 102、主裝置b 103和主裝置c 104為重要 主裝置，而主裝置D 105、主裝置E 1〇6和主裝置F 1〇7 為次要主裝置。一般而言，可以把對匯流排回應速度要求 較高的主裝置設為重要主裝置，如需進行即時處理的裝置 等’而把對回應速度要求不是太高的裝置設為次要主裝 置。同樣地，從屬裝置也分成重要從屬裝置和次要從屬裝 置。在本實施例中，從屬裝置A 1〇8、從屬裝置B 109和 從屬裝置c 110為重要從屬裝置，而從屬裝置D 111、從 屬裝置E 112和從屬裝置F 113為次要從屬裝置。一般而 200523748 言，可以把對匯流排回應速度要求較高的從屬裝置設為重 要從屬裝置’如需進行即時處理的裝置等，而把對回應速 度要求不是太高的裝置設為次要從屬裝置。 請參照第2圖’其繪示本實施例之匯流排系統的物理 佈局示意圖。圖中示意性地表示出，在物理佈局上，重要 主裝置A 202、重要主裝置B 203和重要主裝置c 204，離 仲裁器201較近，而次要主裝置D 205、次要主裝置E 2〇6 和次要主裝置F 207離仲裁器201較遠；重要從屬裝置a 208、重要從屬裝置B 209和重要從屬裝置C 2 1 〇離仲裁器 201較近，而次要從屬裝置D211、次要從屬裝置E212和 次要從屬裝置F 2 1 3離仲裁器2 0 1較遠。匯流排上並對主 裝置和從屬裝置分別設置了兩層多工器。次要主裝置d 205、次要主裝置E 206和次要主裝置F 207，分別有訊號 線連接至第二主裝置多工器216的輸入端，第二主裝置多 工器216的輸出端連接至第一主裝置多工器214的輸入 端。第二主裝置多工器216另有訊號線與仲裁器201相連， 使次要主裝置D 205、次要主裝置E 206和次要主裝置F 207也可以直接向仲裁器201傳送資料。重要主裝置A 202、重要主裝置B 203和重要主裝置C 204各有相應的訊 號線連接至第一主裝置多工器214的輸入端，第一主裝置 多工器214的輸出端連接至所有從屬裝置。因此，所有主 裝置可以在得到匯流排授權後直接向對應的從屬裝置傳送 資料。同樣地，次要從屬裝置D 2 11、次要從屬裝置E 2 1 2 和次要從屬裝置F 2 1 3，分別有訊號線連接至第二從屬裝 200523748 置多工态217的輸入端，第二從屬裝置多工器2i7的輸出 端連接至第-從屬裝置多工^ 215的輸入端。重要從屬襞 置A 208、重要從屬裝置B 209和重要從屬裝置c 210各 有相應的訊號線連接至第一從屬裝置多工器215的輸入 端，第一從屬裝置多工器215的輸出端連接至所有主裝 置。因此，在進行讀運算時，所有從屬裝置可以直接向相 應的主裝置回傳資料。在其他實施例中，也可以只使用一 層多工器，或根據實際裝置的數量來選擇多工器的層數。 重要主裝置和重要從屬裝置之間的資料傳送速率較 大’而重要主裝置和次要從屬裝置之間、次要主裝置和重 要彳之屬褒置之間以及次要主裝置和次要從屬裝置之間的資 料傳送速率較小。在本實施例中，重要主裝置A、重要主 裝置B或重要主裝置C與重要從屬裝置A、重要從屬裝置 B或重要從屬裝置c之間的資料傳送速率為1個資料/時 脈’如匯流排為32位元，匯流排頻率為1兆赫茲（MHz )， 則資料傳送速率為3 2百萬位元/秒。重要主裝置A、重要 主裝置B或重要主裝置C與次要從屬裝置D、次要從屬裝 置E或次要從屬裝置f之間，或是次要主裝置〇、次要主 裝置E或次要主裝置ρ與重要從屬裝置a、重要從屬裝置 B或重要從屬裝置c之間，以及次要主裝置D、次要主裝 置E或次要主裝置F與次要從屬裝置D、次要從屬裝置e 或次要從屬裝置F之間的資料傳送速率為1個資料/ 2時 脈’如前述匯流排為32位元，匯流排頻率為1兆赫茲，則 資料傳送速率為1 6百萬位元/秒，小於重要主裝置與重要 200523748 從屬裝置之間的資料傳送速率32百萬位元/秒。 主裝置發出的匯流排使用請求分成不同的級別，本實 施例中，每一主裝置有一 MReq匯流排請求訊號線與仲裁 器相連，該訊號線傳送的MReq訊號可用來表示匯流排使 用請求的級別。通過MReq匯流排請求訊號線發出的MReq 匯流排使用請求訊號分成REQ、CREQ和LREQ三類，其 解碼如下表所示。 表1 MReq 訊號 說明 0 0 IDLE 無請求 0 1 REQ 一般讀寫請求 10 LREQ 一般和MCmd配合。如果MCmd為0，是要 求LOCK的讀運算； 如果MCmd為1，是解除LOCK的寫運算。 11 CREQ 強制性讀寫請求，具有比REQ更高的優先順 序。 其中MCmd為讀寫運算請求，低為讀，高為寫。 MReq匯流排使用請求訊號中，CREQ和LREQ比REQ 優先順序要高，因此，如果主裝置發出的MReq為CREQ 或LREQ，較之REQ往往能更快速地獲得回應。其中，LREQ 的請求是一種配對的讀寫運算請求，它請求的是一個讀寫 運算的配對運算，由於該讀寫運算需要連續進行，而不能 12 200523748 插入其他的運算，因此將其設為一種優先順序別較高的請 求。 MReq可以在每一次資料傳送時由編 活設定，因此，主裝置發出的匯流排使用請求的優先權等 級可以按實際需求而決定。在其他實施例中，MReq的匯 流排使用清求號可以按需要設定一定的等級，其編碼也 可隨之改變，本技術領域人員對此應易於理解和實現。 在本實施例中，匯流排採用流脈衝（Stream Burst ) 形式的資料傳送方式。以流脈衝的形式進行資料傳送，可 傳送的資料包括單一資料及/或脈衝形式的資料。同一個流 脈衝中的單一資料或一個完整的位址連續的脈衝資料可稱 為一個分段脈衝，而分段脈衝之間的位址可以不連續，在 本實施例中，一個流脈衝中的不同分段脈衝還可以發送給 不同的目標從屬裝置。本實施例中規定MLast訊號來代表 主裝置給仲裁器的分段脈衝結束碼，以指示資料傳送的狀 態。MLast訊號有四類值，分別是c〇NT、[ast、same 和DIFF。CONT表示一個分段脈衝正在傳送中；last表 示-個完整的流脈衝已經結束；SAME表示當前分段脈衝 已經結束’但流脈衝尚未結束，而下一個分段脈衝存取的 從屬裝置與當前分段脈衝相同；DIFF表示一個流脈衝尚未 結束，當前分段脈衝已經έ士类， 可〇 ▲、、、口釆，而下一個分段脈衝存取的 從屬裝置與當前分段脈播尤ρη ^ J刀杈脈衝不同。當M]Ust訊號 SAME、DIFF這三種值時， 乂 值f表不s刖分段脈衝已經結束。 在分段脈衝結束時，仲裁 ^ u 哉狀態，下文將對此 13 200523748 作進一步描述。 ★在-個流脈衝的傳送過程中’如果沒有其他較高級別 的請求提出’當前正在進行資料傳送的主裝置則持續佔 匯流排進行資料傳送運算；如果有其他較高級別的匯流排 使用請求在流脈衝的傳送過程中提出，且此時仲裁器進入 可仲裁狀悲則仲裁器將對當前流脈衝的匯流排使用請求 和其他較高級別的匯流排使用請求一併進行仲裁，選中較 南級別的匯流排使用請求進行匯流排授權。 當匯流排上的主裝置要求使用匯流排進行資料傳送運鲁 算時’首先會發出匯流排使用請求給仲裁器，由仲裁器按 知、預设的演算法判斷出可優先進行的請求。本實施例中， 仲裁器可進行的仲裁包括正向仲裁和反向仲裁兩個部分。 正向仲裁是指對主裝置發出的匯流排使用請求進行仲裁； 反向仲裁是指在讀運算中，對從屬裝置為回傳資料而發出 的匯流排使用請求進行仲裁。而正向仲裁又包括兩層仲 裁，分別是第二階段仲裁和第一階段仲裁。 請參照第3圖，圖中所繪示的仲裁器包括實現第二階段 _ .仲裁的正向第二階段仲裁模組3〇6、實現第一階段仲裁的 正向第一階段仲裁模組303和實現反向仲裁的反向仲裁模 組3 07。正向仲裁後的各訊號經過正向解碼器305解碼後， 送給重要主裝置群302以及次要主裝置群301中之相應的 主裝置與從屬裝置群309中之相應的從屬裝置；反向仲裁 後的各訊號經過反向解碼器308解碼後，送給從屬裝置群 309中之相應的從屬裝置和重要主裝置群302以及次要主 14 200523748 裝置群301中夕士+ # ^ 之相應的主裝置。正向第二階段仲裁模組30ό 對次要主裝置群3〇1私ψ从 夏砰3U i七出的匯流排使用請求進行仲裁， 將仲裁結果送入筮一 P比防1 ^入第 ^ &仲裁模組303 ;第一階段仲裁模 組3〇3則把重要主裝置群302發出的匯流排使用請求和第 一階段的仲裁結果一起進行仲裁。 <正向仲裁的第二階段在任何時間都可進行新的仲裁， 斤t :的仲裁演算法可以是熟悉相關技術人員所知曉的各 種次算法。在本實施例中，正向第二階段仲裁模組是採用 固:優先權演算法進行仲裁，即對每一個主裝置設定一個# 確7的優先權等級’在同一時間有兩個或兩個以上的主裝 置提出咕求時，則選中優先順序別較高的主裝置進入第一 1¾奴。例如’本實施例中，次要主裝置群3 〇丨包括次要主 凌置D、-人要主裝置e和次要主裝置f，其優先權等級分 別設定為1級、2級和3級。這樣，當次要主裝置群3〇 i 提出請求時，仲裁器將選中優先權等級相對較高的次要主 波置D長：出的匯流排請求作為仲裁結果，送入第一階段仲 裁模組3 0 3。 請參照第4圖，其繪示了第二階段仲裁一個示範性的 時序圖’其中次要主裝置D發出的匯流排使用請求的訊號 包括MReq3、MLast3和MDstnum3，分別指出請求的級別、 資料傳送狀態和目標從屬裝置的號碼，同樣地，次要主裝 置E發出的匯流排使用睛求的訊號包括MReq4、MLast4 和MDstnum4。第二階段仲裁模組發出的仲裁結果訊號包 括 A2Req、A2Last、A2Dstnum 和 A2MNum，這些訊號分 15 200523748 別指出第二級仲裁後得到的請求的級別、資料傳送狀態、 目標從屬裝置的號碼和回應的主裝置的號碼。本實施例 中，對重要主裝置A、重要主裝置B、重要主裝置C、次 要主裝置D、次要主裝置E、次要主裝置F依序編號為〇、 1、2、3、4、5 ;同樣地，對重要從屬裝置A、重要從屬裝 置B、重要從屬裝置C、次要從屬裝置D、次要從屬裝置E、 次要從屬裝置F依序編號為〇、1、2、3、4、5。 當次要主裝置D、次要主裝置E和次要主裝置F同時 提出匯流排使用請求時，根據優先等級，仲裁器將優先選 _ 中次要主裝置D提出的匯流排彳吏用請求；若只有次要主裝 置E和次要主裝置F同時提出匯流排使用請求時，根據優 先等級’仲裁器將優先選中次要主裝置E提出的匯流排使 用請求。因此，在第4圖的時序中，第二階段仲裁模組發 出的仲裁結果為優先響應次要主裝置D的匯流排使用請 求。在次要主裝置D的匯流排使用請求響應結束後，仲裁 器才對次要主裝置E此時發出的匯流排使用請求做出回 應。第二階段仲裁模組發出的仲裁結果訊號，包括A2Req、 _ A2Last、A2Dstnum和A2MNum等，送入第一階段仲裁模 、、且參/、仲裁在第4圖的範例中，假定此時無其他匯流排 使用請求參與仲裁或第二階段仲裁模組被優先選中，則在 第-階段仲裁模組中，流排上的仲裁器將發出仲裁訊 號，包括第4圖所示的匯流排授權訊號AGrant和授權主裝 置訊號AMNum $。在本實施例中，由於次要主裝置的資 料傳送速率始終為較低的速率，即1個資料/ 2時脈，因此， 16 200523748 仲裁器對於次要主裝i送出的資料在兩自時脈 ， 料的傳达運算發出AGrant有效訊號進行回應。 個貝 、正向第一階段仲裁並不是在任何時間都可進 裁，而只在滿足一定條件而允許仲 ' 典一如法 r戮的時候才能進行仲 Ϊ仲：/1下，第一階段可以進行仲裁的首要條件是當 别t裁益處於閒置狀態。本實施例中，仲裁 岐她訊號，當該訊號為删時，表示仲裁器目前處 於閒置狀恕，即當前無正在進行中的仲裁運算。 第一階段仲裁採用了分級仲裁機制，在本實施例中包 括REQ仲裁時機和CREQ仲裁時機。對應於這兩個仲裁時 機，分別設有較低級仲裁時機訊號AREQ一的和較高級仲 裁時機訊號ACREQ_arb訊號。針對本實施例流脈衝形式的 資料傳送方式，仲裁狀態機中只有在出現一、8細和 DIFF k二種分段脈衝結束碼時，才能進入仲裁狀態。在本 實施例中，-個流脈衝過程只能被CREQ級別的其他匯流 排使用請求中斷，巾REQ級別的其他匯流排使用請求是不 能中斷一個流脈衝的。因此，在出現LAST訊號時， AREQ_arb訊號與ACREQ_arb訊號同時有效；在出現same 或diff訊號時，只有ACREQ—arb訊號有效。 請參照第5圖，圖中以一個仲裁時機的時序當例子對此 做了說明。在主裝置發出的MLast訊號經仲裁器仲裁後， 仲裁器的正向解碼器會發出ALast訊號，圖中共有三個示 範’分別為LAST、SAME和DIFF。LAST訊號表示一個流 脈衝結束，此時AREQ一arb和ACREq一arb兩個訊號同時有 17 200523748 效；SAME和DIFF均只表示一個分段脈衝已經結束，而流 脈衝未結束，此時只有ACREQ —arb訊號有效。 請參照第6圖與表2，本實施例的仲裁狀態機共包括三 個狀態·· IDLE、ARBLEVEL1 和 ARBLEVEL2。ARBLEVEL1 和ARBLEVEL2分別為前文所述的REQ仲裁時機和CREQ 仲裁時機。以下說明請參照表2。 表2 條件1 沒有一個有效請求是CREQ或LREQ，至少 有1個有效請求是REQ 條件2 在AREQ —arb有效時，且沒有一個有效請求 是 REQ、CREQ 或 LREQ 條件3 至少有1個有效請求是CREQ或LREQ 條件4 在ACREQ_arb有效時，且沒有一個有效請 求是 REQ、CREQ 或 LREQ 條件5 在ACREQ —arb有效且AREQ —arb無效時， 至少有1個有效請求是CREQ或LREQ，且 記 AEnterST2 為 1 條件6 在ACREQ —arb有效時，且沒有一個有效請 求是 CREQ 或 LREQ，以及 AEnterST2 為 1， 同時把AEnterST2歸零 當 Arb —state訊號為 IDLE，並且滿足條件 1，即 AREQ —arb訊號有效時，只有REQ級另》J的有效請求而沒有 18 200523748 CREQ 或 LREQ 級別的有效請求，則仲裁器進入 ARBLEVEL1仲裁狀態。在ARBLEVEL1仲裁狀態下，仲裁 器可以對主裝置發出的REQ、CREQ和LREQ級別的匯流 排使用請求進行仲裁。當Arb_state訊號為IDLE，並且滿 足條件3，即ACREQ —arb訊號有效時，只要有CREQ或 LREQ級別的有效請求，而無論是否有REQ級別的有效請 求，則仲裁器進入ARBLEVEL2仲裁狀態。在ARBLEVEL2 仲裁狀態下，仲裁器只對主裝置發出的CREQ或LREQ級 別的匯流排使用請求進行仲裁，而REQ級別的匯流排使用 請求不參與仲裁。 從第6圖也可以看到，仲裁狀態機中ARBLEVEL1和 ARBLEVEL2兩個狀態在一定的條件也可以相互轉換。因 此，在本實施例中，引入了 AEnterST2訊號，用來記錄被 中斷的仲裁狀態。當仲裁器正在ARBLEVEL1狀態下仲裁 時，由於出現較高級別的有效請求，如CREQ或LREQ請 求，需要轉換仲裁狀態到 ARBLEVEL2狀態下，此時記 AEnterST2訊號為1。由於仲裁器從ARBLEVEL 1狀態下轉 換到ARBLEVEL2狀態下時，需記AEntei:ST2訊號為1， 因此，在AEnterST2訊號為1的情況下，當ARBLEVEL2 狀態下的仲裁運算完成後，若只有REQ級別的匯流排使用 請求而沒有CREQ或LREQ級別的匯流排使用請求，仲裁 、器將不進行重新仲裁，而是返回到原先的仲裁狀態，並在 返回的同時將 AEnterST2訊號歸零。而在轉換仲裁狀態 時，需要保留仲裁器的内部狀態，要保留的訊號量暫時放 19 200523748 在緩衝裔中’要保留的訊號量主要有仲裁器送給主裝置以 回應主裝置的訊號AMNum、仲裁器送給從屬裝置以回應 從屬裝置的汛號ASNum和用來指明資料傳送速率的仲裁 器内部訊號ALeve卜在本實施例中，ALevel訊號為高表示 使用較高的速率，即1個資料/時脈，而ALevel訊號為低 表示使用較低的速率，即1個資料/2時脈。而在其他實施 例中，也可採用更多個不同的資料傳送速率，並相應地對 A L e v e 1舌fL 5^進丁、編石馬。 在從IDLE狀態直接轉換到ARBLEVEL2狀態下時，當 仲裁器完成ARBLEVEL2狀態下的仲裁任務後，即使有 REQ級別的有效請求而沒有crEq或LREQ級別的有效請 求時，仲裁器仍將重新對全部的有效請求進行仲裁。 在ARBLEVEL1狀態下，仲裁器採用一般演算法，公 平地對各個主裝置發出的各類匯流排使用請求進行仲裁， 從中選出一個請求，並對發出該請求的主裝置傳送授權訊 號’則主裝置開始資料傳送。在ARBLEVEL2狀態下，仲 裁器將採用一般演算法對CREQ級別的匯流排使用請求進 •行仲裁，從中選出一個請求，對發出該匯流排使用請求的 主裝置傳送授權訊號，主裝置接到授權訊號後開始佔用匯 流排進行資料傳送運算。在ARBLEVEL2狀態下，REQ级 別的請求將被忽略。這裏的一般演算法，指單迴圈仲裁演 算法（Round Robin)或其他為本技術領域人員公知的仲裁 演算法，在此不再贅述。 請參照第7圖，在本實施例的另一個示範例中，次要主 20 200523748200523748 发明 Description of the invention [Technical field to which the invention belongs] The present invention relates to a multi-device system, and in particular, to a method using a variable rate data transmission method, so that real-time devices in the system can get a fast and effective response, so as to Multi-device system that guarantees high bus frequency. [Previous technology] The rapid development of the semiconductor industry has greatly promoted the development of the integrated circuit design industry, especially in the semiconductor industry, the emergence of deep sub-micron (DSM; Deep Sub-Micron) technology has brought single-chip systems (System-on-Chip) ; SoC) design is pushed to the forefront of integrated circuit design. The single-chip system technology is to integrate multiple processors that were previously scattered on multiple different chips on the same chip to form a complete system with complete functions and superior sex. Because the physical area and package pins of Zhuo Wafer System are greatly reduced compared to multi-wafer systems, the production cost of the entire system is also greatly reduced. On the other hand, the reuse of Intellectual Property (IP) modules in the system also shortens the design cycle of single-chip systems and reduces the system design costs. A single-chip system may include various processors, such as a central processing unit (CPU), a digital signal processor (DSP), and various specialized circuits (positions) [and storage units, which may even include each; a built-in processor core (kernel ) Subsystem. The expansion of the entire system scale makes the complexity of the system higher than the previous multi-chip system. Therefore, how to reasonably and effectively adjust the operation of each processing line or system in the system in 200523748 has become a _ technique in the entire system design process ^ ^ Although important issues. The bus architecture is used to achieve the mutual communication of various processing channels or subsystems in the system, including command transmission and data transmission. In a multi-device system, in the transmission of signals between multiple devices, the device that sends # requests / requests for signal transmission to the sink is called the master device; and the target device that the master device requests for signal transmission is called Is a slave device. For multi-device communication, Changtian County, Tiantian County, Tianmu County, uses an arbiter to determine the use of bus requests from multiple devices. * Μ J ^ The devices that give the bus ownership are based on various algorithms. Sincerely,…, the master device possessing the right to possess the power possesses the bus and communicates with the corresponding slave device. In order to reduce the circuit area and reduce the cost of manufacturing & 'multi-device systems often use a common bus to achieve communication between the devices on the bus; but at the same time only one master device on the bus Occupy the bus for communication. On the other hand, the various devices in a multi-device system have different characteristics, such as input, output devices such as keyboards, mice, or monitors. And some are central processing unit (πυ) and digital signal processor (Dsp), etc., or some other subsystems. The input and output device does not require high response speed of the bus, so its required bandwidth is not very high, and the processors such as central processing unit and digital signal processor have higher requirements for real-time response speed.地 也 # 纟 BUS can provide high-speed bandwidth for it. > If the bandwidth requirements are high and the bandwidth requirements are not high, or some devices with bandwidth requirements between T are directly connected to the bus at the same time, and centralized arbitration is performed by an arbiter at the same time, often 200523748 restricts each other between devices with different bandwidths and cannot respond to real-time devices. The development of system integration technology / 'Yue said that the development of integrated circuit technology has enabled integrated circuits to increase unit area performance, and market demand has also promoted the integration of more functions in the system. The realization of this function is from a hardware perspective. It is inevitable to add more devices to the system to perform various functions.汇 Convergence of multi-device systems If there are more master devices and slave devices in the row structure, the wiring delay in the data transmission process will have a greater impact on the data transmission rate, thus causing the sink: the frequency of row L to drop rapidly. % In recent years, the large increase in the system frequency and the denseness of wiring in large-scale integrated circuits have also caused the proportion of wiring delay systems and charging transmission delays to become higher and higher, resulting in relatively uncertain system transmission delays. increase. [Summary of the Invention] Therefore, the object of the present invention is a multi-device system of a transmission method, which is a layered arbitration and adopts different rates. The frequency of the two buses is ensured, and the response speed is guaranteed. In providing a traditional method of using variable-rate data to transmit data to multiple devices on a bus, a device with high requirements for fast response is proposed from one aspect. According to the above-mentioned object of the present invention, a multi-device system and system are proposed. , At least multiple ΓΛ arbiters, used to arbitrate the bus device request made by the master device in the form of a 2 arbitration, and arbitrate the lower layers between the master devices of the lower layers, and then arbitrate the lower layers The results of the arbitration are: ::: The bus use request is sent to the bus at the same level of arbitration; multiple main devices are in phase with the bus i | 200523748 and divided into multiple according to the different bandwidth requirements Different levels; and a plurality of slave devices 'connected to the bus and divided into multiple different levels according to different bandwidth requirements', and data transfer operations can be performed between the bus and the master device. The communication between the higher-level master device and the higher-level slave device uses a higher data transfer rate. The communication between the lower-level master device and the slave device or between the master device and the lower-level slave device. Inter-communication uses a lower data transfer rate. In addition, according to the above object of the present invention, a physical layout is proposed. The master device at the south level and the slave devices at the higher level are closer to the arbiter on the bus, while the master device at the lower level and the slaves at the lower level are closer. The device is far from the arbiter on the bus. <. , Eight-n ΊΤ two systems. For example, a reverse arbitration module is further provided in the arbiter. When the slave sends back read data in response to the read operation request sent by the master device, it applies to the reverse arbitration module for a bus. Occupied. The basis of reverse arbitration is determined by the data transfer rate between the master device and the slave device. Because =, the master device and the slave device with higher bandwidth requirements use a relatively high data transfer rate, and can calculate 'at the same time, from the physical layout, the higher-level master; the second: the slave device transmitted from the confluence The arbiter is relatively close and the distribution n is relatively reduced, so it can fully meet the requirements of the master device and slave devices with low frequency response and bandwidth requirements of such devices. 1 far, but using a lower data transfer rate, the data transfer time between the master arbiter and the arbiter is affected by the wiring delay. The net slave device 4 also reduces the response, which makes the uncertainty of the transmission delay of the 20052005748 system. Can also be relatively reduced [Embodiment] Please refer to page! FIG. 'The multi-device system according to the embodiment of the present invention includes a bus 10, an arbiter 114 connected to the bus 101, and a main device Al02, a main device B 103, and a main device C 1 respectively connected to the bus HH. 〇 4, the master device D105, the master device E106, the master device F107, and the slave device A 108, the slave device B 109, the slave device c 110, the slave device d η, the slave device E Π2, and the slave device F 113. Among them, the master device may be a CPU, an ASIC, or a subsystem; the slave device may be a device such as a synchronous dynamic random access memory (SDRAM) or a direct memory access (dma). The arbiter on the bus can arbitrate the bus use request made by each device connected to the bus, and the master device selected by the arbitration occupies the bus and the corresponding slave device for data transmission. The master device can be divided into an important master device and a secondary master device. In this embodiment, the 'master device A 102, the master device b 103, and the master device c 104 are important master devices, and the master device D 105, the master device E 106, and the master device F 107 are secondary master devices. Generally speaking, a master device that has a high requirement for the response speed of the bus can be set as an important master device, such as a device that needs to perform real-time processing, and a device that does not have a high response speed requirement can be set as a secondary master device. Similarly, the slaves are divided into important slaves and secondary slaves. In this embodiment, the slave device A 108, slave device B 109, and slave device c 110 are important slave devices, and the slave device D 111, slave device E 112, and slave device F 113 are secondary slave devices. Generally speaking, in 200523748, you can set the slave device that requires high response speed to the bus as an important slave device. For devices that require real-time processing, etc., set the device that does not require too high a response speed as a secondary slave device. . Please refer to FIG. 2 ', which illustrates a physical layout diagram of the busbar system of this embodiment. The figure schematically shows that in the physical layout, the important master device A 202, the important master device B 203, and the important master device c 204 are closer to the arbiter 201, while the secondary master device D 205 and the secondary master device E 2 06 and the secondary master device F 207 are far from the arbiter 201; the important slave device a 208, the important slave device B 209, and the important slave device C 2 1 0 are closer to the arbiter 201, and the secondary slave device D211 The secondary slave device E212 and the secondary slave device F 2 1 3 are far from the arbiter 2 01. Two-layer multiplexers are set on the busbar and the master device and slave device respectively. The secondary master device d 205, the secondary master device E 206, and the secondary master device F 207 have signal lines connected to the input terminal of the second main device multiplexer 216 and the output terminal of the second main device multiplexer 216, respectively. Connected to the input of the first master multiplexer 214. The second master multiplexer 216 has another signal line connected to the arbiter 201, so that the secondary master D 205, the secondary master E 206, and the secondary master F 207 can also directly transmit data to the arbiter 201. The important master device A 202, the important master device B 203, and the important master device C 204 each have corresponding signal lines connected to the input of the first master multiplexer 214, and the output of the first master multiplexer 214 is connected to All slaves. Therefore, all master devices can send data directly to the corresponding slave devices after being authorized by the bus. Similarly, the secondary slave device D 2 11, the secondary slave device E 2 1 2 and the secondary slave device F 2 1 3 respectively have signal lines connected to the input terminals of the second slave device 200523748 and the multiplex mode 217. The output of the two slave multiplexers 2i7 is connected to the input of the-slave multiplex ^ 215. The important slave device A 208, the important slave device B 209, and the important slave device c 210 each have corresponding signal lines connected to the input of the first slave multiplexer 215, and the output of the first slave multiplexer 215 is connected To all masters. Therefore, when performing a read operation, all slave devices can directly return data to the corresponding master device. In other embodiments, only one layer of the multiplexer may be used, or the number of layers of the multiplexer may be selected according to the number of actual devices. The data transfer rate between the important master device and the important slave device is relatively large ', and between the important master device and the secondary slave device, between the secondary master device and the important slave device, and between the secondary master device and the secondary slave device The data transfer rate between devices is small. In this embodiment, the data transfer rate between the important master device A, the important master device B or the important master device C and the important slave device A, the important slave device B or the important slave device c is 1 data / clock. The bus is 32 bits, the bus frequency is 1 megahertz (MHz), and the data transfer rate is 32 million bits / second. Important master device A, important master device B or important master device C and secondary slave device D, secondary slave device E or secondary slave device f, or secondary master device 0, secondary master device E or secondary Between the primary master device ρ and the important slave device a, the important slave device B or the important slave device c, and the secondary master device D, the secondary master device E, or the secondary master device F and the secondary slave device D, the secondary slave device The data transmission rate between the device e or the secondary slave device F is 1 data / 2 clocks. 'If the bus is 32 bits and the bus frequency is 1 MHz, the data transmission rate is 16 million bits. Yuan / second, which is less than the data transfer rate of 32 million bits / second between the important master device and the important 200523748 slave device. The bus use request sent by the master device is divided into different levels. In this embodiment, each master device has a MReq bus request signal line connected to the arbiter. The MReq signal transmitted by this signal line can be used to indicate the level of the bus use request. . The MReq bus sent through the MReq bus request signal line is divided into three types of REQ, CREQ and LREQ using the request signal, and its decoding is shown in the following table. Table 1 MReq signal description 0 0 IDLE no request 0 1 REQ general read and write request 10 LREQ generally cooperates with MCmd. If MCmd is 0, it is a read operation that requires LOCK; if MCmd is 1, it is a write operation that cancels LOCK. 11 CREQ Mandatory read and write requests with higher priority than REQ. MCmd is a read and write operation request, low is read, and high is write. In the MReq bus use request signal, CREQ and LREQ have higher priority than REQ. Therefore, if the MReq sent by the master device is CREQ or LREQ, the response is often faster than REQ. Among them, the LREQ request is a paired read and write operation request. It requests a paired read and write operation. Because the read and write operation needs to be performed continuously, it cannot be inserted into other operations, so it is set as a type. Requests with a higher priority. MReq can be set by the editor at each data transfer. Therefore, the priority level of the bus use request issued by the master device can be determined according to actual needs. In other embodiments, the MReq bus can use a clear request number to set a certain level as required, and its coding can be changed accordingly. Those skilled in the art should easily understand and implement this. In this embodiment, the bus adopts a data transmission method in a stream burst (Stream Burst) format. Data is transmitted in the form of stream pulses. The data that can be transmitted includes single data and / or data in the form of pulses. A single piece of data in the same stream pulse or a complete pulse with continuous address can be called a segmented pulse, and the addresses between the segmented pulses can be discontinuous. In this embodiment, the Different segmented pulses can also be sent to different target slaves. In this embodiment, the MLast signal is specified to represent the segmentation pulse end code of the master device to the arbiter to indicate the status of data transmission. There are four types of MLast signals, namely co-NT, [ast, same, and DIFF. CONT indicates that a segmented pulse is being transmitted; last indicates that a complete stream pulse has ended; SAME indicates that the current segment pulse has ended 'but the stream pulse has not ended yet, and the slave device accessing the next segment pulse and the current segment pulse The segment pulses are the same; DIFF indicates that a stream pulse has not ended, and the current segment pulse has been classified, and the slave device for the next segment pulse access is particularly different from the current segment pulse. ^ J blades have different pulses. When M] Ust signal SAME, DIFF three values, the value f indicates that the segmentation pulse has ended. At the end of the segmentation pulse, the arbitration ^ u 哉 state, which will be described further below 13 200523748. ★ During the transmission of a stream pulse, 'if no other higher-level request is made', the master device that is currently transmitting data will continue to occupy the bus for data transmission operations; if there are other higher-level bus use requests It is proposed during the transmission of the stream pulse, and at this time the arbiter enters the arbitrable state. The arbiter will arbitrate the current bus pulse use request and other higher-level bus use requests together. The south-level bus uses the request for bus authorization. When the main device on the bus requires data transfer and calculation using the bus, it will first send a request for the use of the bus to the arbiter, and the arbiter will determine the request that can be performed first according to a known and preset algorithm. In this embodiment, the arbitration that can be performed by the arbiter includes two parts: forward arbitration and reverse arbitration. Forward arbitration refers to the arbitration of the bus use request sent by the master device; reverse arbitration refers to the arbitration of the bus use request issued by the slave device to return data in the read operation. Forward arbitration includes two levels of arbitration, namely the second-stage arbitration and the first-stage arbitration. Please refer to FIG. 3, the arbiter shown in the figure includes a second stage arbitration module 306 that implements the second stage _. A forward first stage arbitration module 303 that implements the first stage arbitration And reverse arbitration module 3 07 which implements reverse arbitration. Each signal after forward arbitration is decoded by the forward decoder 305 and sent to the corresponding master devices in the important master device group 302 and the secondary master device group 301 and the corresponding slave devices in the slave device group 309; After the arbitration, the signals are decoded by the reverse decoder 308 and sent to the corresponding slave devices and important master device groups 302 in the slave device group 309 and the secondary master 14 200523748 in the device group 301. The main unit. The second-stage arbitration module 30 is being used to arbitrate the use of the secondary master device group 301 private bus from Xia Bang 3U i seven bus request, and send the arbitration result to the first P to prevent 1 ^ into the first ^ & Arbitration module 303; The first-stage arbitration module 303 arbitrates the bus use request issued by the important master device group 302 together with the arbitration result of the first stage. < The second stage of forward arbitration can be conducted at any time. The arbitration algorithm can be various algorithms known to those skilled in the art. In this embodiment, the forward second-stage arbitration module uses a fixed: priority algorithm for arbitration, that is, a # # 7 priority level is set for each master device. There are two or two at the same time. When the above master device asks, the master device with a higher priority is selected to enter the first slave. For example, in the present embodiment, the secondary master device group 3 includes the secondary master device D, the primary master device e, and the secondary master device f, and the priority levels are set to 1, 2, and 3, respectively. level. In this way, when the secondary master device group 30i makes a request, the arbiter will select the secondary master wave with a relatively high priority and set the length D: the outgoing bus request as the arbitration result and send it to the first stage arbitration. Module 3 0 3. Please refer to FIG. 4, which shows an exemplary sequence diagram of the second stage arbitration. Among them, the signal of the bus use request issued by the secondary master device D includes MReq3, MLast3, and MDstnum3, which indicate the request level and data transmission, respectively. The status and the number of the target slave device. Similarly, the signals requested by the bus master E, including MReq4, MLast4, and MDstnum4. The arbitration result signals issued by the second-stage arbitration module include A2Req, A2Last, A2Dstnum, and A2MNum. These signals are divided into 15 200523748. Do not indicate the level of the request obtained after the second-level arbitration, the data transmission status, the number of the target slave device, and the response The number of the master device. In this embodiment, the important master device A, important master device B, important master device C, secondary master device D, secondary master device E, and secondary master device F are sequentially numbered 0, 1, 2, 3, 4, 5; Similarly, important slave device A, important slave device B, important slave device C, secondary slave device D, secondary slave device E, secondary slave device F are sequentially numbered 0, 1, 2, 3, 4, 5. When the secondary master device D, the secondary master device E, and the secondary master device F simultaneously request the use of the bus, according to the priority level, the arbiter will preferentially select the bus official request from the secondary master D If only the secondary master device E and the secondary master device F submit a bus use request at the same time, according to the priority level, the arbiter will preferentially select the bus use request submitted by the secondary master device E. Therefore, in the sequence of Fig. 4, the arbitration result issued by the arbitration module in the second stage is a priority response to the bus usage request of the secondary master device D. After the response to the bus use request from the secondary master D is completed, the arbiter responds to the bus use request from the secondary master E at this time. The arbitration result signals sent by the second stage arbitration module, including A2Req, _ A2Last, A2Dstnum, and A2MNum, etc., are sent to the first stage arbitration module, and participate in the arbitration in the example in Figure 4. It is assumed that there is no other The bus use request to participate in arbitration or the second-stage arbitration module is selected first. In the first-stage arbitration module, the arbiter on the bus will issue an arbitration signal, including the bus authorization signal shown in Figure 4. AGrant and authorized master signal AMNum $. In this embodiment, since the data transmission rate of the secondary master device is always a lower rate, that is, one data / 2 clock, therefore, the data sent by the arbiter to the secondary master device is at two clocks. The pulse and data transmission operation responds with a valid AGrant signal. This arbitration is not admissible at any time, but can only be conducted when certain conditions are met to allow the arbitration to proceed as follows: / 1, the first stage The first condition that arbitration can take place is when the judgement benefits from idleness. In this embodiment, the arbitration Qieta signal, when the signal is deleted, indicates that the arbiter is currently idle, that is, there is currently no arbitration operation in progress. The first stage of arbitration uses a hierarchical arbitration mechanism. In this embodiment, REQ arbitration timing and CREQ arbitration timing are included. Corresponding to these two arbitration occasions, a lower-level arbitration occasion signal AREQ-1 and a higher-level arbitration occasion signal ACREQ_arb signal are provided. For the data transmission method in the form of stream pulses in this embodiment, the arbitration state machine can enter the arbitration state only when two types of segmented pulse end codes of one, eight, and DIFF k appear. In this embodiment, a stream pulse process can only be interrupted by other bus use requests at the CREQ level, and other bus use requests at the REQ level cannot interrupt a stream pulse. Therefore, when the LAST signal appears, the AREQ_arb signal and the ACREQ_arb signal are valid at the same time; when the same or diff signal appears, only the ACREQ_arb signal is valid. Please refer to Figure 5, which illustrates the timing of an arbitration timing as an example. After the MLast signal sent by the master device is arbitrated by the arbiter, the forward decoder of the arbiter will send the ALast signal. There are three examples in the figure, which are LAST, SAME, and DIFF. The LAST signal indicates the end of a stream pulse. At this time, the two signals AREQ-arb and ACREq-arb have 17 200523748 effect simultaneously; SAME and DIFF only indicate that one segment pulse has ended, and the stream pulse has not ended. At this time, only ACREQ — The arb signal is valid. Refer to Figure 6 and Table 2. The arbitration state machine of this embodiment includes three states: IDLE, ARBLEVEL1, and ARBLEVEL2. ARBLEVEL1 and ARBLEVEL2 are the REQ arbitration timing and CREQ arbitration timing described above, respectively. Please refer to Table 2 for the following descriptions. Table 2 Condition 1 No valid request is CREQ or LREQ, at least one valid request is REQ condition 2 When AREQ-arb is valid, and no valid request is REQ, CREQ or LREQ condition 3 At least one valid request is CREQ or LREQ condition 4 when ACREQ_arb is valid, and none of the valid requests are REQ, CREQ, or LREQ condition 5 When ACREQ —arb is valid and AREQ —arb is invalid, at least one valid request is CREQ or LREQ, and AEnterST2 is recorded as 1 Condition 6 When ACREQ —arb is valid, and none of the valid requests are CREQ or LREQ, and AEnterST2 is 1, meanwhile, AEnterST2 is reset to zero. When the Arb —state signal is IDLE, and the condition 1 is satisfied, that is, when the AREQ —arb signal is valid If there is only a valid request at the REQ level and other than J and no valid request at the level of 18 200523748 CREQ or LREQ, the arbiter enters the ARBLEVEL1 arbitration state. In the ARBLEVEL1 arbitration state, the arbiter can arbitrate the REQ, CREQ and LREQ-level bus usage requests issued by the master device. When the Arb_state signal is IDLE and satisfies condition 3, that is, the ACREQ-arb signal is valid, as long as there is a valid request at the CREQ or LREQ level, regardless of whether there is a valid request at the REQ level, the arbiter enters the ARBLEVEL2 arbitration state. In the ARBLEVEL2 arbitration state, the arbiter only arbitrates the CREQ or LREQ level bus use request sent by the master device, while the REQ level bus use request does not participate in arbitration. It can also be seen from Figure 6 that the two states of ARBLEVEL1 and ARBLEVEL2 in the arbitration state machine can also switch to each other under certain conditions. Therefore, in this embodiment, the AEnterST2 signal is introduced to record the interrupted arbitration status. When the arbiter is arbitrating in the ARBLEVEL1 state, due to a higher level of valid request, such as a CREQ or LREQ request, it is necessary to switch the arbitration state to the ARBLEVEL2 state. At this time, record the AEnterST2 signal as 1. Because the arbiter transitions from the ARBLEVEL 1 state to the ARBLEVEL 2 state, it is necessary to record the AENtei: ST2 signal is 1. Therefore, when the AEnterST2 signal is 1, after the arbitration operation in the ARBLEVEL 2 state is completed, if only the REQ level The bus use request without a CREQ or LREQ level bus use request, the arbiter and the device will not re-arbitrate, but return to the original arbitration state, and return the AEnterST2 signal to zero at the same time. When changing the arbitration state, it is necessary to retain the internal state of the arbiter. The signal amount to be retained is temporarily placed in the buffer. 'The signal amount to be retained is mainly sent by the arbiter to the master device in response to the signal AMNum, The arbiter sends it to the slave device in response to the flood number ASNum of the slave device and the internal signal ALeve of the arbiter used to indicate the data transfer rate. In this embodiment, a high ALevel signal indicates that a higher rate is used, that is, 1 data / Clock, and a low ALevel signal indicates that a lower rate is used, that is, 1 data / 2 clock. In other embodiments, more different data transmission rates may also be adopted, and the A L e v e 1 and fL 5 ^ may be used accordingly. When directly transitioning from the IDLE state to the ARBLEVEL2 state, when the arbiter completes the arbitration task in the ARBLEVEL2 state, even if there is a valid request at the REQ level and no valid request at the crEq or LREQ level, the arbiter will re- Effective request for arbitration. In the ARBLEVEL1 state, the arbiter uses a general algorithm to arbitrate all kinds of bus use requests sent by each master device, select a request from it, and send an authorization signal to the master device that issued the request. Then the master device starts Data transfer. In the ARBLEVEL2 state, the arbiter will use a general algorithm to arbitrate the CREQ-level bus usage request, select a request from it, and send an authorization signal to the host device that issued the bus usage request. The host device receives the authorization signal Then began to occupy the bus for data transfer calculations. In the ARBLEVEL2 state, requests at the REQ level will be ignored. The general algorithm here refers to a single-loop arbitration algorithm (Round Robin) or other arbitration algorithms known to those skilled in the art, and details are not described herein again. Please refer to FIG. 7. In another exemplary embodiment of this embodiment, the secondary master 20 200523748
裝置D和次要主裝置E需要完成與第4圖的示範例同樣的 資料傳送運算，但在次要主裝置D的傳送過程中，仲裁器 收到了一個較尚級別的匯流排使用請求。在第7圖中，^ 要主裝置A發出了匯流排使用請求，其訊號包括撾〜叫、 MLastO和MDstnumO等。仲裁器收到CREQ級別重要主裝 置A的匯流排使用請求後，仲裁狀態機進入到 ARBLEVEL2，對重要主裝置A的匯流排使用請求進行仲 裁。在次要主裝置D的第一個分段脈衝結束時，仲裁器授 權重要主裝置A進行資料傳送。重要主裝置A的發送目桿 為重要從屬裝m此其資料傳送速率較高，為^固：^ 枓/時脈m裝i a #資料傳送完成後返回原流脈衝， 假設此時無其& CREQ級制匯㈣㈣請求，則繼續進 :次要主裝^ D的資料傳送以及次要主裝置e的資 运，貝料傳送速率仍為1個資料/2時脈。 執行緒 者是子 裁器會 〇 —個 所在的 執行緒 的讀數 在其他 據，從 的反向Device D and secondary master device E need to complete the same data transfer operations as in the example of FIG. 4, but during the transfer of secondary master device D, the arbiter received a higher level bus use request. In FIG. 7, the main device A sends a request for using the bus, and its signals include a signal, MLastO, and MDstnumO. After the arbiter receives the bus use request from the important master device A at the CREQ level, the arbiter state machine enters ARBLEVEL2 to arbitrate the bus use request from the important master device A. At the end of the first segmentation pulse of the secondary master D, the arbiter authorizes the important master A to transfer data. The sending eyepiece of the important master device A is an important slave device, which has a high data transmission rate, which is ^ solid: ^ 枓 / clock mmia ia # Return to the original pulse after the data transmission is completed, assuming that there is no & The CREQ-level system request is continued: the data transmission of the secondary main device ^ D and the data transmission of the secondary main device e, the material transmission rate is still 1 data / 2 clock. The thread is a sub-processor. The reading of the thread is in other data, from the reverse of
本實施例中，主# $ A ^ , 主羞置A和主裝置b還具有多In this embodiment, the master # $ A ^, the master A and the master device b have more
(Thread)，备一去I 母執仃緒可以是CPU、DSP、ASIC或 系統等。當有一批〜1 執仃緒獲得授權使用匯流排時，仲 .發出該執行緒所屉+灿 Τ 執行緒的請求未ή 的號碼和該執行緒的號碼 從屬裝置還未準：,行完全時’例如其讀取的資料 發出铁喪，m備好時，允許同一主裝置中的其他 據，：各自對二可能會有幾個不同執行緒所請求 實施例中，也；、不同從屬裝置同時回傳的情形。 各自對應的二能出現幾個不同主裝置請求的讀數 冋從屬裝置同時回傳的情形。仲裁器 21 200523748 仲裁模組在這種情形下，可以對各個不同從屬裝置回傳讀 數據的匯流排使用請求進行仲裁。類似正向仲裁，當仲裁 器反向仲裁兀成後，仲裁器提供的ARGrant訊號將置於有 效狀態，授權選中的從屬裝置佔有匯流排進行資料回傳運 算，同時，表示已有從屬裝置獲得授權並佔有匯流排， ARGrant訊號為各裝置共用。 本實施例中，仲裁器的反向仲裁也有仲裁時機。在次 要從屬裝置進行反向資料傳送時或是進行反向資料傳送的 目標是次要主裝置時，即正在進行資料傳送速率為i個資_ 料/2時脈的資料傳送運算時，仲裁器不進行仲裁。 睛參照第8圖，圖中對反向仲裁的仲裁時機進行示範性 說明。圖中ARSNum訊號表示進行反向資料傳送的從屬裝 置，ARGrant訊號表示仲裁器對反向資料傳送的從屬裝置 和對應主裝置發出回應，ARMNum訊號表示反向資料傳送 的目標主裝置，ARArb —forbid訊號為低時，表示允許對反 向傳送的從屬裝置的有效請求做出仲裁。從第8圖中可以 看出’重要從屬裝置A在對重要主裝置b進行反向資料傳 _ 送時’資料傳送速率為1個資料/時脈，ARArb —forbid訊 號為低，可進行仲裁；重要從屬裝置B向次要主裝置F回 傳資料的反向匯流排使用請求，資料傳送速率為1個資料 /2時脈，ARArb —forbid訊號變高，不可進行反向仲裁；次 要從屬裝置E對重要主裝置B和次要從屬裝置f對次要主 裝置D發出反向匯流排使用請求時，資料傳送速率均為！ 個資料/2時脈，ARArb 一 forbid訊號會變高，不可進行反向 22 200523748 仲裁。 本實施例中，反向請求也分成不同等級’包括SREQ 級別的反向請求和CSREQ級別的反向請求，其中CSREQ 級別的反向請求優先順序高於SREQ級別的反向請求。在 仲裁器對反向請求進行仲裁時，首先回應CSREQ級別的反 向請求。同級別的反向匯流排使用請求則按發出反向請求 的從屬裝置的固定優先順序來決定。例如，可將從屬裝置 A、從屬裝置b、從屬裝置c、從屬裝置D、從屬裝置E和 從屬裝置F的固定優先順序由高到低設定，因此，若從屬 裝置A、從屬裝置B和從屬裝置c同時發出反向匯流排使 用請求’仲裁器將優先響應從屬裝置A的反向匯流排使用 請求；而若只有從屬裝置B和從屬裝置C同時發出同級別 的反向匯流排使用請求時，仲裁器將優先響應從屬裝置b =反向匯流排使用請求。在其他實施例中，也可採用其他 肩算法對反向匯流排使用請求進行仲裁，同樣應該包 本發明的實質範圍内。 然、本發明已以-實施例揭露如上，然其並非用 本發明，任何孰習！^姑黏土 限疋 '^ 技藝者，在不脫離本發明之精神和㈣ 内’—可作各種之争私命、q fe圍 後附之Φ ri主轰4丨丨θ I3C! /、W隻乾圍當視 攸W之甲吻專利範圍所界定者為準。 田规 圖針ΤΙ附圖為對本發明實施例的輔助說明，-人 圖對本發明實施例的闡述 、…下 V揭露本發明的特 23 200523748 所在’但並不限制本發明，圖中相同符號代表實施例中相 應元件或步驟，其中·· 第1圖繪示本發明一實施例的多裝置系統結構示意 TSI · 圖， 第2圖繪示第i圖所示多裝置系統的匯流排結構示音 圖； ^ 第3圖繪示本發明一實施例的仲裁器之結構圖； 圖 第4圖繪示本發明一實施例之第二階段仲裁的時序 第5 機時序圖 圖繪示本發明一實施例之第一階段仲裁的仲裁時(Thread), which can be a CPU, DSP, ASIC, or system. When a batch of ~ 1 thread is authorized to use the bus, Zhong. Issues a request for the thread drawer + CanT thread and the number of the thread and the slave device of the thread are not yet accurate: when the line is complete 'For example, the data it reads is iron, and when it is ready, other data in the same master device are allowed: each may have several different threads in the requested embodiment, also; different slave devices are simultaneously Postback situation. Two corresponding readings can occur when several masters request readings from the slave device. Arbiter 21 200523748 In this case, the arbitration module can arbitrate the bus usage request for the read data returned by different slave devices. Similar to forward arbitration, when the arbiter reverse arbitration is completed, the ARGrant signal provided by the arbiter will be placed in a valid state, authorizing the selected slave device to occupy the bus for data return operations, meanwhile, it means that the slave device has obtained Authorize and possess the bus, ARGrant signal is shared by each device. In this embodiment, the arbiter's reverse arbitration also has an arbitration opportunity. When the secondary slave device performs reverse data transfer or the target of the reverse data transfer is the secondary master device, that is, when a data transfer operation with a data transfer rate of i data _ data / 2 clock is being performed, arbitration The device does not perform arbitration. Referring to Figure 8, the timing of reverse arbitration is exemplarily illustrated. In the figure, the ARSNum signal indicates the slave device for reverse data transmission. The ARGrant signal indicates that the arbiter responds to the slave device and the corresponding master device for reverse data transmission. The ARMNum signal indicates the target master device for reverse data transmission. ARArb —forbid signal When low, indicates that arbitration is allowed for valid requests from the slave devices transmitted in the reverse direction. It can be seen from the figure 8 that 'important slave device A is performing reverse data transmission to important master device b when sending data'. The data transmission rate is 1 data / clock, and the ARArb —forbid signal is low, which can be arbitrated; The important slave device B sends a reverse bus usage request to the secondary master device F. The data transfer rate is 1 data / 2 clock. The ARARA —forbid signal becomes high, and reverse arbitration cannot be performed. The secondary slave device When E issues a reverse bus use request to the important master device B and the secondary slave device f to the secondary master device D, the data transfer rate is both! Data / 2 clocks, the ARArb-forbid signal will go high and no reverse arbitration will be allowed. In this embodiment, the reverse request is also divided into different levels, including a SREQ-level reverse request and a CSREQ-level reverse request. The CSREQ-level reverse request has a higher priority than the SREQ-level reverse request. When the arbiter arbitrates a reverse request, it first responds to the reverse request at the CSREQ level. Reverse bus use requests at the same level are determined according to the fixed priority order of the slave devices that issue the reverse request. For example, the fixed priorities of slave device A, slave device b, slave device c, slave device D, slave device E, and slave device F can be set from high to low. Therefore, if slave device A, slave device B, and slave device c Simultaneously issue reverse bus use request 'The arbiter will give priority to responding to the reverse bus use request of slave device A; if only slave device B and slave device C issue the same level of reverse bus use request at the same time, arbitration The router will respond preferentially to the slave device b = reverse bus usage request. In other embodiments, other shoulder algorithms may also be used to arbitrate the reverse bus usage request, which should also be included within the true scope of the present invention. However, the present invention has been disclosed as above with the embodiment, but it is not used in the present invention, any study! ^ Gu Clay limit 疋 'Artists, without departing from the spirit and ㈣ of the present invention'-can be used for all kinds of private life, q fe encircled by Φ ri main blast 4 丨 丨 θ I3C! /, W only Qianwei shall be subject to the scope defined by the patent scope of Jiawen W. The diagram of the field plan is as a supplementary explanation to the embodiment of the present invention,-the illustration of the embodiment of the present invention by the human figure, the following V will disclose the features of the invention 23 200523748, but does not limit the invention, the same symbols in the figure represent Corresponding elements or steps in the embodiment, where: Fig. 1 shows a schematic TSI diagram of a multi-device system structure according to an embodiment of the present invention, and Fig. 2 shows a bus structure of a multi-device system shown in Fig. I ^ Figure 3 shows a structure diagram of an arbiter according to an embodiment of the present invention; Figure 4 shows a timing diagram of a second stage of arbitration according to an embodiment of the present invention; a fifth machine timing diagram shows an implementation of the present invention The first stage of arbitration
第6圖繪示本發明 作原理圖； 第7圖繪示本發明 第8圖繪示本發明 機X 以及 圖。 一實施例之仲裁器的仲裁狀態 一實施例的正向仲裁時序圖· 一實施例的反向仲裁時機時序 【元件代表符號簡單說明】 101 匯流排 102 ： 主裴置 A 103 主裝 置 B 104 ： 主裝置 C 105 主裝 置 D 106 ： 主裝置 B 107 主裝 置 F 108: 從屬裝 置 A 109 從屬 裝 置 B 110 : 從屬骏 置 C 111 從屬 裝 置 D 112 : 從屬數 置 E 113 :從屬 裝 置 F 114 : 仲裁器 24 200523748 201 : 203 : 205 : 207 : 209 : 211 : 213 : 215 : 216 : 217 : 301 : 303 : 304 : 306 : 307 309 仲裁器 202 : 重要主裝置A 重要主裝置B 204 : 重要主裝置B 次要主裝置D, 206 : 次要主裝置E 次要主裝置F 208 : 重要從屬裝置A 重要從屬裝置B 210 : 重要從屬裝置C 次要從屬裝置D 212 : 次要從屬裝置E 次要從屬裝置F 214 : 第一主裝置多工器 第一從屬裝置多工器 第二主裝置多工器 第二從屬裝置多工 器 次要主裝置群 302 : 重要主裝置群 正向第一階段仲裁模組 仲裁狀態機 305 : 正向解碼器 正向第二階段仲裁模組 反向仲裁模組 308:反向解碼器 從屬裝置群 25Fig. 6 shows the principle of the invention; Fig. 7 shows the invention; Fig. 8 shows the machine X and the invention. Arbitration status of an arbiter according to an embodiment A timing diagram of a forward arbitration according to an embodiment A timing of a reverse arbitration timing according to an embodiment [a brief description of a representative symbol of a component] 101 bus 102: a master device A 103 a master device B 104: Master device C 105 Master device D 106: Master device B 107 Master device F 108: Slave device A 109 Slave device B 110: Slave device C 111 Slave device D 112: Slave number E 113: Slave device F 114: Arbiter 24 200523748 201: 203: 205: 207: 209: 211: 213: 215: 216: 217: 301: 303: 304: 306: 307 309 Arbiter 202: Important master device A Important master device B 204: Important master device B Secondary master device D, 206: Secondary master device E Secondary master device F 208: Important slave device A Important slave device B 210: Important slave device C Secondary slave device D 212: Secondary slave device E Secondary slave device F 214: First master multiplexer, first slave multiplexer, second master multiplexer, second slave multiplexer, secondary master device group 302: important master device group is forward first Arbitration module to arbitrate section 305: Forward Forward second stage decoder module arbitration arbitration module 308 reverse: Reverse decoder slave device group 25