TW200523747A - An arbiter - Google Patents

Abstract

The present invention is related to an arbiter that can arbitrate the data traffic on the bus. The arbiter includes a forward and a reverse arbitration devices. The forward arbitration device includes a second layer arbitration mode, in which the bus requests from minor master devices will be arbitrated and a candidate minor master device will be chosen, and a first layer arbitration mode, in which the bus requests from the candidate minor master device and the major master devices will be arbitrated and a granted master device will be chosen to send data to the slave devices via the bus. The reverse arbitration device arbitrates the bus requests from major slave devices and chooses a granted slave device to send back the data to the major master device via the bus.

Description

200523747 发明 Description of the invention [Technical field to which the invention belongs] The present invention relates to a kind of arbiter, and in particular, to a kind of multi-device system that quickly and efficiently arbitrates the use of g-streaming requests sent by each device. Arbiter to improve the efficiency of the bus. [Previous technology] The rapid development of the semiconductor industry has greatly promoted the development of integrated circuit design industry, especially in the semiconductor industry, the emergence of deep sub-micron (DSM; Deep Sub-Micron) technology has brought single-chip systems (System_〇n_chip;

SoC) design is pushed to the forefront of integrated circuit design. The single-chip system technology is to integrate multiple processors that were previously scattered on multiple different chips on the same B chip to form a complete system with complete functions and superior performance. Because the physical area and package pins of the single-chip system are greatly reduced compared to the multi-chip system, the production cost of the entire system is also greatly reduced. On the other hand, the reuse of Intellectual module (IP) in the system also shortens the design cycle of the single-chip system and reduces the design cost of the system. A single-chip system may include various processors, such as a central processing unit (CPU), a digital signal processor (DSP), and various application-specific circuits (ASICs), as well as a storage unit (storage unit), and may even include Various subsystems with built-in processor cores. The expansion of the entire system scale makes the system more complex than previous multi-chip systems. Therefore, how to reasonably and efficiently adjust the operation of each processor or subsystem in the system has become a very important part in the entire system design process in 200523747. problem. Convergence is used to achieve mutual communication, instruction transmission and data transmission among the various processors or subsystems in the system. The design of this confluence structure has a crucial impact on the overall work of the =. In the signal transmission between multiple devices in the bus system, a request is made to: and the device requesting the signal transmission is referred to as the main device: device); and the target device that the main device requests the signal transmission is (vedevice). For multi-device communication, the bus is used to use arbitration benefits to make requests for the use of buses issued by multiple devices. Devices that give the bus ownership are determined by various algorithms. ㈣Arbitration M configuration situation ’The current bus architecture is mainly divided into buses and centralized buses. The decentralized bus architecture is to set a corresponding arbiter, and each arbiter competes with each other ::-Decide by which device on the bus is authorized to occupy the bus. The bus is used only for the entire system. Adopt a unified arbiter: the arbitration method preset by the arbitration readings, and make a centralized judgment on all bus use requests σ: determine the authorized use = set. It is easy to understand, especially the centralized bus system; two = the efficiency of the use of the bus has a decisive role. 2. Arbitration is for the current sinking technology. Once the master device obtains and obtains the bus authorization, the master device requests the use of the bus.-The bus is occupied by the master device, and it will not be obtained before the calculation is completed. Respond. Therefore, designers often 2 = the priority order of the bus request. Under the conditions such as the main arbiter 4 setting-determined cutting, etc., priority is given to the bus use request issued by the master device with a higher order of 200523747. Get a response. Some designers have proposed to divide the bus use requests sent by the master device into different priority levels, and the arbiter decides the bus use requests that respond first according to the priority level of each bus use request. However, if the arbiter arbitrates the requests for the use of buses of different levels at the same time, it will complicate the hardware and algorithms of the arbiter and may extend the arbitration period. On the other hand, for a bus system that supports split transaction of read signals, such as a bus master with multiple threads, a certain thread of a master device can be used. b Turtle out five different operations, and responding to the slave device corresponding to its operation also allows other threads of the master device to send signal transmission operations (of course, including read operations). In this case, there may be multiple threads sending data at the corresponding slave device whose read operation is f, and the read operation difference issued earlier = the corresponding slave f setting may require a longer data preparation time. The data sent back in the order sent by the luck will definitely affect the read operation of other threads. In order to improve the use efficiency of the bus, in the design we can allow the read data to be sent out of order, that is, for the prepared read data, regardless of the order in which read operation requests are issued, priority is given to the return. However, this out-of-order return of read data may also cause different slave devices to use confluence: release, read data at the same time, and cause the read data to collide with each other during the return. Instead, it will increase access latency and reduce bus efficiency. The present invention proposes an improved arbiter that can perform both forward and reverse arbitration. In the forward direction, you can use 200523747 to set different arbitration timings for different buses using request levels. In reverse arbitration, you can arbitrate requests for read data return from multiple slave devices. [Summary of the Invention] The purpose of the present invention is to provide Wenliang's arbiter for setting different arbitration timings for different ® bus usage requests, etc., to improve arbitration efficiency 'and improve bus usage efficiency. °… The other purpose of the present invention is to provide an improved arbiter, which has the ability to reverse arbitrate, and to avoid the conflict of read data return on the premise of improving the efficiency of using the bus. According to the above object of the present invention, the bus system includes a connected master device, a slave device, and an arbiter. The master device sends to the arbiter :; the row use request. After the arbiter has arbitrated, it wipes the selected bus use: authorization, the master device that issued the bus use request will occupy the bus center = slave device to perform data transfer operations . The bus issued by the master device uses two different priority levels, and the arbiter is in the arbitration state machine to arbitrate the timing. At the arbitration timing with a short interval, the port arbitrates the bus use request with a higher priority, while arbitrating the bus use request with a lower f priority. At the arbitration timing with a long interval, the car has the same priority. Sequential bus usage requests and lower-priority, row usage requests can be arbitrated by the arbiter at the same time. According to another object of the present invention, the bus system supports separate reading operations: when different slave devices simultaneously send back data for calculations, the bus uses the calculation of the 'arbiter based on-^ calculation in the case of March The method of operation of the returned data shall be arbitrated in 200523747. In one embodiment of the present invention, the software configures the use request of the bus for each data returned from m, sets different priority levels, and the arbiter performs arbitration according to the priority levels. According to an embodiment of the present invention, the arbiter arbitrates multiple devices on the bus and performs knife-level arbitration, and requests with lower response speed are arbitrated in lower-level arbitration modules. High requests and arbitration results obtained from lower-level arbitration modules are arbitrated in higher-level arbitration modules. The arbiter includes the first-stage arbitration module and the second-stage arbitration module. ▲ Relatively, the arbiter's arbitration operation includes the first-stage arbitration and the second-stage arbitration. The operating principle is as follows: first, the main device in the bus system is further divided into important main devices and secondary main devices. In the second stage of arbitration, 'the arbitration H requests the use of the bus from the secondary main device first. "Arbitration" and then send the arbitration result to the first stage arbitration; and what the first stage arbitration needs to do is to conduct the arbitration result of the second stage arbitration with the bus use request issued by the important master device on the bus arbitration. According to one embodiment of the present invention, a screening program (terter) is further provided in the first stage arbitration module of the arbiter, and various filtering and single unit units can be set in the screening program. The bus use request sent by the main device has been checked, and the M bus use request that passed the screening program can be used as a valid request to participate in arbitration. For example, in the embodiment of the present invention, it is provided that the slave device is in a busy state unit. That is, the slave device that is temporarily unable to perform data transmission operations will issue a SBUSy signal check program, and the bus use request is in progress. Before arbitration, check the program to determine 'If the target slave device of the data transfer operation is the k-subordinate device of 200523747 corresponding to the SBUSy signal', the bus use request will be ignored. For another example, in another embodiment of the present invention, a final request control filtering unit is provided for achieving pipeline arbitration, so that the request of the last clock of each ongoing stream burst (Stream Burst) is requested. Masked. For another example, in another embodiment of the present invention, a paired read-write operation filtering unit is provided. When the bus handles the paired read-write operation, the t-bus is placed in a locked state when it is used for read access. On the right, other master I devices issue paired read and write operation bus usage requests and will be ignored. The timing of J Danli's double arbitration has not only improved the response speed to the data values, macros, etc. that need to be responded to, but also improved the arbitration efficiency. In vain bus efficiency. In addition, in the present invention, when a return request is made for a bus system of the ancient reverse type read operation, the reverse device simultaneously sends a data stream blockage to the bus at the same time. Exchange rates caused by data conflicts. On the other hand, the use efficiency of the busbar is improved. [Embodiment] ‘Please refer to FIG. 1, 1 Luo-Shitong. The busbar system includes at least three busbars connected to the busbar system of one embodiment of the present invention, including the busbar 101, and the busbar 101, the master unit D105, and the slaves, respectively. Wear #set 81〇3, master device (: 104, C108 and slave device 106, slave device B 107, slave device and each device on the bus ^ 09. Arbiters 110 are provided on the bus respectively The device is connected to arbitrate the bus use request made by each device connected to the bus 200523747. In a bus system with multiple master devices, several master device units in the system can be used. It is configured as a master device on a bus, and these several master device units can be respectively called a thread of the master device on the bus. A multi-threaded bus system can be advanced The arbitration is performed inside the master device on one bus, so the use efficiency of the arbiter on the bus can be improved. In this embodiment, the master device A has 3 threads, and the bus master device B has 2 threads. Each thread Can be ⑽, ㈣,

ASJC or subsystem. The main unit. And the host device d does not include multiple threads', which may be one of a CPU, a Dsp, an ASIC system, and the like. 8. This embodiment also installs Jingong # 击 热 ># into an important main device and a secondary main device. Main device A and main device b are important

, Receiver device, and main device C and main device D are * ^ to be installed W. ^ One-05 · rTn '_ 5' You can set a master device with a high requirement on the response speed of the bus as an important master dream. 'For devices that require real-time processing, etc., the response speed must be grayed XB > ^ Devices that are not too clever are set as secondary primary devices. The slave device can be synchronous kinetic energy (SDRAM) or direct memory access (DMA).

Arbiter vs. Master® A

When the bus used by the main device B, main device C, and main device D responds to the request of Θ, the taxi driver U will send the corresponding main device number through the AMNum signal line. ,,, &Quot; The corresponding master device. The codes that encode the master device correspond to the following: T master step 詈 Γ .. Master device A, 1 is the master device B, 2 is the robe I, 3 is the master nightmare ". In addition, the main device A and the main device B are respectively equipped with a thread identification signal line MthreadID. When a thread in the main device A or the main device B sends a bus use request to get a response from the arbiter, the arbiter sends the responded main device number to the corresponding main device through the AMNum signal line, and simultaneously passes the MThreadID signal line The corresponding thread number is transmitted to the corresponding thread in the host device. Both the master device and the slave device are provided with various types of signal lines connected to the arbiter, which are used to transmit various control signals in the data transmission operation. For example, the MDstnum signal is the number sent from the master device to the arbiter to request the slave device. In this embodiment, the coding codes of the four slave devices correspond to the following: 0 is a slave device A, 1 is a slave device B, 2 is a slave device C, and 3 is a slave device D. The bus use request sent by the master device is divided into different levels. In this embodiment, each master device has a MReq bus request signal line connected to the arbiter. The MReq signal transmitted by this signal line can be used to indicate the level of the bus use request. . The MReq bus sent through the MReq bus request signal line is divided into three types of REQ, CREQ and LREQ using the request signal, and its decoding is shown in the following table. Table 1 MReq signal description 0 0 IDLE no request 0 1 REQ general read and write request 10 LREQ generally cooperates with MCmd. If MCmd is 0, it is a read operation that requires LOCK; if MCmd is 1, it is a write operation that cancels LOCK. 200523747 11 CREQ Mandatory read and write requests with a higher priority than REQ. MCmd is a read and write operation request, low is read, and high is write. In the MReq bus use request signal, creq and LREQ have higher priority than REQ. Therefore, if the MReq sent by the master device is CREQ or LREQ, the driver ’s REQ often gets a response more quickly. Among them, the [REQ request is a paired read and write operation request. It requests a paired read and write operation. Because the read and write operation needs to be performed continuously and cannot be inserted into other operations, it is set to a Requests with a higher priority. MReq can be flexibly set by programming and other methods at each data transmission. Therefore, the priority level of the bus use request issued by the master device can be determined according to actual needs. In other embodiments, the MReq bus request signal can be set to a certain level as required, and its coding can be changed accordingly. Those skilled in the art should easily understand and implement this. In this embodiment, a data transmission method in the form of a stream burst (Stream Burst) is also used between the master device and the slave device. This data transmission method can transmit a large amount of data at once, and the data transmitted by each stream pulse can include multiple single data (Single) and multiple pulse data (Burst). A single piece of data in the same stream pulse or a complete pulse with continuous address can be called a segmented pulse, and the addresses between the segmented pulses can be discontinuous. In this embodiment, the Different segmented pulses can also be sent to different target slaves. In the embodiment of the present invention, it is also required that the length of the segmented pulse is an integer power of two and the addresses are aligned. 14 200523747 Relative to data transmission in the form of stream pulses, each master device or each thread in the master device is provided with a transmission status MLast signal line, and the rainbow post signal transmitted in the signal line indicates the master device or the master device. The thread requested the status of the data transfer operation. In this embodiment, four states are defined for the transmission and delivery of stream pulse data, including four types of signals: CONT, SAME, DIFF, and LAST. As shown in Table 2, they are encoded separately. _ Table 2 MLast [l: 〇] Signal Description 0 0 CONT The two segment pulses are not over. 0 1 End of LAST stream pulse. 10 SAME indicates the end of a segmented pulse. It is foreseen that the next segmented pulse accesses the same slave device as this segmented pulse, and the access request has the same level (that is, all are req or CREQ). 〇11 diff ~ ''- ------ _ indicates the end of a segmented pulse. It is forewarned that the next segmented pulse and this segmented pulse access different slave devices' or have different levels of access requests. In the shell material transmission operation, it is represented by CC) NT signal—a segmented pulse, which means that the data transmission address corresponding to the 3 NTC signal is also: there is no need to re-arbitrate. The “signal” indicates that a arbiter is required to perform the f data transfer operation again, and updates all bus use requests to arbitrate. 15 200523747 Both the SAME and DIFF signals indicate that a segmented pulse has been transmitted & The main difference is that the two zeta signals are used to predict the next segmented pulse and this segmented pulse access slave device, but the address and this segmented pulse may not be continuous, and the next segmented pulse and this Segmented pulse access requests have the same level, that is, all are CREQ and so on. The chat signal is used to predict the next sub-pulse and the slave device of this sub-pulse access W, or the next sub-pulse and the level of this sub-pulse access request are different. Similarly, the encoding of MLast can also be adjusted according to the type of data transmission operation status that is actually required. The device on the blind row requires the bus to perform data transfer operations: the upper row and the upper row use requests to the arbiter, and the arbiter The request made by the arbiter according to the pre-two: two priority. The order that the arbiter of the present invention can make includes the forward and reverse arbitration of the bus sent to the master device = ruling 4 from M_wh A to run the arbitration, To arbitration refers to the use of ^ nil 2 0 !, J ^ ^ ^ ^ ^ group in the calculation of = :; for the return of the funds needed to return funds; to the corresponding master device and slaves ^ Decoding benefit 206 After decoding, the encoder 208 decodes the signals ^ / ° After the signals are cut in the reverse phase two stages = 2: Wide: Should: Master-slave device and master device. Forward arbitration, and then The arbitration 1 issued by the arbitration bus will be used for arbitration,…, and the arbitration module will be entered into the first stage arbitration module 202; 16th 200523747-P are all arbitration modules, and the group 202 will be re-summed with the second stage The arbitration agency may use the bus from Chuan Chuan to omit the second stage of the arbitration. In his embodiment, the arbitration module does not perform arbitration processing, that is, when the second stage of arbitration ==, the second stage of forward arbitration can start a new r =? The arbitration algorithm can be familiar with various types known to relevant technical personnel. Algorithm. For simplicity, in this embodiment, the forward second-stage service arbitration group uses a fixed priority algorithm (such as itith) for arbitration, that is, one for each secondary master device. The exact priority level 'when there are two or more secondary masters requesting at the same time', then the master of the priority vocational high school is selected to enter the first stage. As shown in Figure 3 ' The main device c and the main device D are secondary main devices, and the -it priority level is set to & i and level 2. The signals of the main device c include MReq3 'MLaSt3 and MDStnum3, which indicate the requested level, data transmission status, and The number of the target slave device. Similarly, the Λ number of the master device d includes MReq4, MLast4, and MDstnum4. When the master device c and the master device D simultaneously request the use of the bus, according to the priority level, the arbiter will select the master device first. The bus use request made by Device C. In the time sequence after the response to the bus use request of the main split C, the arbiter will respond to the bus use request of the main device D at this time. The second stage arbitration module The arbitration signals sent include A2Req, A2Last, A2Dstnum, and A2Mnum, etc., which instruct the bus to use the request level, data transmission status, target slave device number, and responding master device number. These arbitration signals are sent to the first stage of arbitration as the result of arbitration The module participates in arbitration. In this case, 17 200523747 assumes that Yin Yin's assumption is that in the first stage Zhongshi ^., And the arbitration is carried out, and no other bus is used to request participation in arbitration, or the second stage ^ ^ cutting model , And the arbitration result shipped out is given priority k, then the forward decoder sends out / knows the arbitration vanadium, including the bus authorization signal AGrant shown in the picture and the authorized main dream Jinxuan Wangwang type signal AMNum, etc. came to respond to the main device C and the main 奘 sn ^ Ar- + the first stage of forward arbitration first required all arbitrators who need to participate in the arbitration ☆ _ 4 inspection procedures (filter). The screening program will be masked according to the request that the filter bar can't perform before the preparation. A request to continue participating in arbitration through a screening program is called a valid request. In this embodiment, the screening program mainly includes three filtering units.罝 and the main 4 set D bus use request. The first 疋 k belongs to the device busy state (SBusy) filtering unit, which can be communicated only when the slave device accessed by the confluence ^ use request is not in a busy state, and it is a private check type. For example, in this embodiment, the accessed The receive buffer of the slave device must be able to receive commands from the master device. For this condition, each slave device in the second embodiment is configured with a receive buffer, which is used to receive the receive instruction and related data from the t-cutter I. The receive buffer y mentioned here is a first-in-first-out register (FIF0). When the remaining _ free space of the slave device buffer is close to zero, that is, the remaining space of the buffer can only support the length of one pulse data or the length of one pulse data plus one data length, the slave device sends the slave device busy status Signal SBusy signal to the arbiter 'SBusy signal indicates the number of the slave device. The second is a paired read and write request control (LREQ) filtering unit, which is directed to the LREQ type bus use request in this example. For a LREQ request for read access, it will respond only when the bus is not locked. If the bus is locked, the read access of this lreq request must be masked. Here, the bus is locked, which means that another master or other thread has previously issued a lreq request, and the request is performing a read operation. This can prevent a new LREQ request from obtaining a bus authorization for read access operations, and cause errors in previous LREQ operations. The first unit is the last request control filtering unit, which can be used to ensure that the bus system can continuously process multiple bus use requests to achieve the effect of pipeline (pipelineH. For each stream pulse being transmitted For the request of the last clock, the arbiter needs to determine the data transmission status of the stream pulse and the ALast signal to determine the next arbitration state, so the arbiter needs to mask the request of the last clock of the stream pulse. In other embodiments of the present invention, other filtering units can be provided in the screening program. Referring to FIG. 4, the screening program 406 of the arbiter has three control ports, which are respectively connected to the slave device busy status signal line 4 〇2, the bus lock control line 403 and the last request control signal line 404. The input terminal of the screening program 疋 The bus use request 4 from the main device, the output of the screening program is screened Requests that are programmed but not masked are called valid requests 405. The arbiter will use arbitration algorithms to arbitrate valid requests. Figures 5-7 are screening Exemplary timing diagram of the operation of the three filtering units in the formula. In the SBusy filtering unit, the arbiter first locks the SBusy signal from each slave device to the SBusy control end, and the screening program combines the current SBusy signal and MDstnum signal to block Mask operation (mask 200523747 operation), in which the MDstnum signal indicates the number of the slave device to be accessed by the request. If the number of the slave device indicated by the MDstnum signal is the same as the slave device in which SBuSy functions, it means that the slave device accessed by the request The command cannot be received at this time. At this time, the screening program masks the request. Refer to Figure 5. The MReqO signal is the bus use request signal sent by the master device A. The MDstnum signal indicates the slave device to be accessed by the request. The MVReqO signal It is a valid request signal output after passing through the screening program. The SBusyO signal takes effect on the next clock after locking, so that the operation of the last clock accessed by MReqO to slave device A (the corresponding MDstnum signal is 0) is masked (Ie MVReqO is IDLE); and during the access to slave device B (the corresponding MDstnum signal is 1), the screening process No valid SBusyl signal appears, so access to the slave device B is not masked. In the bus lock control filter unit, an ALock signal is applied to the bus lock control terminal. If the bus is locked, the ALock signal Is high, and performs masking operation with the MReq signal at the input. If the bus is locked and the MReq signal is displayed as LREQ, the screening program will mask the request. In the embodiment shown in Figure 6, MReqO and MCmdO is the bus request signal sent by device A; AReq and ACmd are the response signals sent by the arbiter, which indicate the level of authorization request and read and write status, AGrant is the authorized signal of the arbiter; MVReqO is the main signal sent by the output end A valid request for device A. During the period when the AGrant signal is high, when the AReq is LREQ and ACmd is low (represented as a read request), the ALock signal of the bus lock control terminal is high; and when ACmd is high (represented as a write request), the bus is locked The control signal is low. When the ALock signal is high 20 200523747, the bus is locked. At this time, the arbiter will not arbitrate other LREQ read operations. In the figure, the first LREQ request of MReqO is a read operation, and the ALock signal is high in the first clock of this LREQ request, so the MREqO reflects that the LREQ in this clock is masked. For the last request control filtering unit, in an embodiment of the present invention, for the request of the last clock of each stream pulse being transmitted, the arbiter will determine the AGrant, AMNum and ALast signals together. When the AGrant signal is valid, And AMNum refers to the master device that currently owns the bus and transmits the stream pulse, and ALast indicates that the request from the master device has reached the request of the last clock, and the arbiter covers the request of the last clock of this stream pulse. Cover it off. Please refer to Figure 7. The MReqO signal is the bus use request signal sent by the main device A. The ALast signal indicates the data transmission status after the arbiter decodes the bus request signal. From the timing of the AMNum signal, it can be seen that the current The main device A that occupies the bus. In the figure, the timing of the MVReqO signal shows that the request corresponding to the last clock of the ALast signal is masked. The first stage of forward arbitration is not that new arbitration can be conducted at any time, but only when certain conditions are met to allow arbitration. In general, the first condition for arbitration in the first stage is that the current arbiter is idle. In this embodiment, the arbiter provides an Ai * b_state signal. When the signal is IDLE, it indicates that the arbiter is currently in an idle state, that is, no arbitration operation is currently in progress. The hierarchical arbitration in the first stage, in this embodiment, includes the timing of REQ Zhong 21 200523747 arbitration and CREQ arbitration. Corresponding to these two arbitration timings, there are AREQ_arb and ACREQ_arb arbitration timing control signals. In this embodiment, the data transmission method used is a stream pulse format, and the MLast signal is specified to represent the segmented pulse data transmission status code of the master device to the arbiter. The MLast signal has three values to indicate that the current segmentation pulse has ended: LAST indicates that a complete stream pulse has ended; SAME indicates that a stream pulse has not ended, the current segmentation pulse has ended, and the next segmentation pulse access The slave device is the same as the current segment pulse; DIFF means that a stream pulse has not ended, the current segment pulse has ended, and the slave device accessed by the next segment pulse is not the same as the current segment pulse. In the arbitration state machine, it is possible to enter the arbitration state when these three segmented pulse end codes appear. In this embodiment, a stream pulse process can only be interrupted by other requests at the CREQ level, and other requests at the REQ level cannot interrupt a stream pulse. When the LAST signal appears, the AREQ_arb signal and the ACREQ_arb signal are valid at the same time; when the SAME or DIFF signal appears, only the ACREQ_arb signal is valid. Please refer to Figure 8 which illustrates this with arbitration timing. After the MLast signal sent by the master device is arbitrated by the arbiter, the forward decoder of the arbiter will issue the ALast signal. There are four types of values corresponding to the MLast signal, namely CONT, SAME, DIFF and LAST, which can be used to help determine the next time. Pulse arbiter arbitration state to speed up bus pipeline processing. In the figure, there are three examples of ALast signals: LAST, SAME, and DIFF. The LAST signal indicates the end of a stream pulse, and the two signals AREQ_arb and ACREQ_arb are valid at the same time; SAME and DIFF only indicate that a segment pulse has ended 22 200523747, and the stream pulse is not ended, only the ACREQ_arb signal is valid. The ACREQ-arb signal is valid at both the end of the stream pulse and the end of the segment pulse in the stream pulse, while the AREQ_arb signal is valid only at the end of the stream pulse. Obviously, the ACREQ-arb signal is more effective than the AREQ-arb signal. For frequent, in other words, the time interval of the CREQ arbitration opportunity is shorter than the time interval of the REQ arbitration opportunity. Please refer to Figure 9 and Table 3. The arbitration state machine in this embodiment includes three states: IDLE, ARBLEVEL1, and ARBLEVEL2. ARBLEVEL1 and ARBLEVEL2 are the REQ arbitration timing and CREQ arbitration timing described above, respectively. Please refer to Table 3 for the following descriptions. Table 3 Condition 1 None of the valid requests are CREQ or LREQ, at least 1 valid request is REQ condition 2 When AREQ_arb is valid, and none of the valid requests are REQ, CREQ or LREQ condition 3 At least 1 valid request is CREQ or LREQ condition 4 when ACREQ_arb is valid, and none of the valid requests are REQ, CREQ, or LREQ condition 5 When ACREQ_arb is valid and AREQ_arb is invalid, at least 1 valid request is CREQ or LREQ, and AEnterST2 is 1 and condition 6 is When ACREQ_arb is valid, and no valid request is CREQ or LREQ, and AEnterST2 is 1, same as 200523747, AEnterST2 is reset to zero. As can be seen from the arbitration state machine in Figure 9, the arbiter does not arbitrate at any time Yes, arbitration is performed only in the two states of ARBLEVEL1 and ARBLEVEL2. When the Arb jtate signal is IDLE and satisfies condition 1, that is, only valid requests at the REQ level and no valid requests at the CREQ or LREQ level, and the AREQ-arb signal is valid, the arbiter enters the ARBLEVEL1 arbitration state. In the ARBLEVEL1 arbitration state, the arbiter can arbitrate the REQ, CREQ, and LREQ-level bus usage requests issued by the master device. When the Arb_state signal is IDLE and condition 3 is satisfied, that is, as long as there is a valid request at the CREQ or LREQ level, regardless of whether there is a valid request at the REQ level and at the same time an ACREQ-arb signal is valid, the Bayer J arbiter enters the ARBLEVEL2 arbitration state . In the ARBLEVEL 2 arbitration state, the arbiter only arbitrates the CREQ or LREQ-level bus use requests issued by the master device, while the REQ-level bus use requests do not participate in arbitration. It can also be seen from Figure 9 that the two states of ARBLEVEL1 and ARBLEVEL2 in the arbitration state machine can also switch to each other under certain conditions. Therefore, in this embodiment, the AEnterST2 signal is introduced to record the interrupted arbitration status. When the arbiter is arbitrating in the ARBLEVEL1 state, due to a higher-level valid request, such as a CREQ or LREQ request, it is necessary to switch the arbitration state to the ARBLEVEL2 state, and record the AEnterST2 signal as 1. In this way, when the AEnterST2 signal is 1, it enters the ARBLEVEL2 state until the arbitration operation in the ARBLEVEL2 state is completed. 24 200523747 At this time, if there is only a valid request at the REQ level and no other valid request at the CREQ or LREQ level, The arbiter will not re-arbitrate, but will return to the original arbitration state and return the AEnterST2 signal to zero at the same time. When changing the arbitration state for arbitration, the internal state of the arbiter needs to be retained. The amount of signal to be retained is temporarily placed in the buffer. The amount of signal to be retained is mainly sent by the arbiter to the master device in response. The number of the master device AMNum and the arbiter are sent to the slave device in response to the number of the slave device ASNum and so on. When directly transitioning from the IDLE state to the ARBLEVEL2 state, when the arbiter completes the arbitration task in the ARBLEVEL2 state, the arbiter will arbitrate all valid requests again. During the arbiter's arbitration process, when the ACREQ_arb signal is valid, if the arbiter is directly switched from the state of ARBLEVEL1 to the state of ARBLEVEL2, in order to prevent overload of the corresponding slave device to be accessed by the valid bus use request, this embodiment is again Use the SBixsy signal of the busy status signal of the slave device as the judgment basis to determine the current status of the slave device. If the receiving buffer of the slave device is currently unable to receive, the slave device will send an SBusy signal. After the arbiter locks the SBusy signal, it performs mask calculation with the signal MDstnum indicating the target slave device number in the bus use request. When the corresponding slave devices are consistent, the bus use request will be masked. In the ARBLEVEL1 state, the arbiter uses general algorithms to arbitrate various types of bus use requests sent by each master device, selects a request from it, and transmits an authorization signal to the master device that issued the request. The master device receives Data transmission starts after the signal is authorized. In the ARBLEVEL2 state 25 200523747, a general algorithm will be used to perform requests with priorities CREQ and LREQ, and from t cREQ and summation, and request the main m 胄 CREQ or LREQ to send an authorization signal, The right signal is transmitted to the beginning of the poem.

主 K, 丨 a master card receives 1 in ARBLEVEL2 state, REQ

Level M requests will be ignored. This one's V Robin algorithm (Round Robin) ^: & he refers to a single-loop arbitration algorithm, which is no longer an arbitration known to those skilled in the art = the arbiter also includes a reverse Arbitration module 207. Both the main device A and the main device B have multiple threads. When a thread is authorized to use the bus, the arbiter will issue the main device and the number of the thread. The thread of a thread, 'b rail lights, when the request of the person is not completed, such as when the slave device of the data to be retrieved is not ready, other threads in the same master can issue a request Therefore, there may be several read data requested by different threads at the same time from their corresponding different slave devices. In other embodiments, there may also be a situation where several different master devices spray the length | read data, and return data from different slave devices where they are located at the same time. In this case, the reverse arbitration module of the server can arbitrate each of the "different" slave slaves to read back the data using the bus. It ’s similar to the first one. After the cutter performs reverse arbitration on the reverse request sent by the slave device, the arbitration will provide a valid authorization signal ARGrant signal to authorize the selected and small members to possess the confluence. Row for data return operations. The ARGrant signal is shared by all slaves and is valid in the high level state. In this embodiment, the slave device is also divided into important slave devices and ★ 4 major slave devices, such as slave device A and slave device B are important slave devices. Straight from 26 200523747

The slave device c and the slave device D are slave devices for reverse data transmission. When the secondary slave device is set, the data transfer used is [, the target is a low data transfer rate between the secondary devices. For example, the transmission rate of Beckham between 2 and important slave devices is 1 data / clock. The secondary slave wears it ... When transmitting to the data or reverse the data transmission. ^ ^ ^ ^, When the master device is a secondary master device, its data rate is 1 W for the data master. During the reverse data transfer rate of 1 data / 2 clock, the secondary The arbitrator was arbitrated, so the reverse arbitration of the arbiter also has the opportunity for arbitration. Please refer to Figure 1G, which illustrates the arbitration timing of reverse arbitration by way of example. The picture ARSNum signal indicates the slave device for reverse data transmission, the ARGrant signal indicates that the arbiter responds to the slave device and the corresponding master device for the reverse data transmission, and the ARMNum signal indicates the target of the reverse data transmission. When the arbitration signal ARArb_forbid is low, the table does not allow arbitration of a valid request from a slave device transmitted in the reverse direction. It can be seen from the figure M that the slave device A is an important slave device, and the master device B is an important master device. When the slave device A transmits reverse data to the master device B, the ARArb-forbid signal is low and arbitration can be conducted ; During the reverse data transfer from slave B to master D, since master d is the secondary master, the ARArb_forbid signal will become high and arbitration cannot be performed; slave C and slave D are both secondary slaves When the two are transmitting data with any host device, the ARArb-forbid signal will become high and arbitration cannot be conducted. In this embodiment, the reverse request is also divided into different levels, including SREQ level 27 200523747 other reverse requests and CSREQ level reverse requests, wherein the reverse request of the howling level has a higher priority than the reverse request of the SREQ level. When the arbiter arbitrates a reverse request ', first a reverse request at the csreq level. Same-level reverse requests are determined according to the fixed priority of the slave device that issued the reverse request. For example, slave device A, slave device B,

The fixed priorities of slave device C and slave device D are set from high to low. In this way, if slave device A, slave device B, slave device c, and slave device D are the same as k & The device will preferentially respond to the reverse whistle from the shoulder device A, if there is only the slave device b and the slave device. When a wide-time reverse request is issued and it is a valid request, Zhong Ye will give priority to responding to the reverse request from the shoulder device B. In other embodiments, the reverse request method can also be used to arbitrate the reverse request, and the changes should also belong to the present invention. 1 Although the present invention has been disclosed as above with the embodiment, it is not used to: invent, anyone skilled in this art will not depart from the spirit of the present invention ^ 'It can be modified and related, so the scope of protection of the present invention The appended application patents shall prevail.

[Brief description of the drawings] The following drawings are a supplementary explanation of the embodiments of the present invention, and the embodiments of the present invention are intended to further disclose the present invention, but do not limit the present invention. The same symbols in the figures represent: Or steps, where: ························································································································ A timing diagram of the second stage arbitration according to an embodiment of the present invention; FIG. 4 shows the working principle of the screening program according to an embodiment of the present invention; FIG. 5 shows the slaves of the screening program according to an embodiment of the present invention Timing chart of the busy state transition unit of the device; FIG. 6 illustrates the timing chart of the bus lock control filter unit of the screening program according to an embodiment of the present invention; FIG. 7 illustrates the end of the screening program of an embodiment of the present invention Timing diagram of the request control filtering unit; FIG. 8 is a timing diagram of the forward arbitration timing according to an embodiment of the present invention; FIG. 9 is a working principle diagram of the arbitration state machine according to an embodiment of the present invention; Show this hair Timing diagram of reverse arbitration timing of an embodiment. [Simple description of component representative symbols] 1 〇1: Busbar 102: Master device a 103: Master device B 104: Master device c 105: Master device D 106: Slave device a 107: Slave device B 108: Slave device c 109: Slave device d 11 〇: Arbiter 201 · Forward second stage arbitration module 202: Forward first stage arbitration module 203: Screening program 204: Arbitration state machine 205: Buffer 206 : Forward decoder 29 200523747 207: Reverse arbitration module 208 ·· Reverse decoder 401: Bus use request signal 402: Slave device busy status signal 403: Bus lock signal 404 ·· Last requested control signal 405: Valid Request 406: Screening Procedure

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Claims (1)

200523747 Scope of patent application 1. Arbiter, for the transfer of data of a bus, * "μ ^ stretches a bus, the bus k is connected to a plurality of No.-the master device, a plurality of No. Two master devices, a plurality of first slave devices, and a trend towards Iμ „Shu Yi straight and a number of second slave devices, the priority of this one master device is higher than the priority of the first-Leyi master device And the priority of the Sheng-I slaves is higher than the priority of the 4b --- Le Yi slaves, the stretcher includes at least: T A forward arbitration device includes at least: a first-stage arbitration module that judges at least one bus use request issued by these second master devices and selects a candidate second master device; and A first-stage arbitration module to determine the candidate second master device and at least one bus use request issued by the X-th master device ▲ 'Select an authorized master device, wherein the authorized master device is allowed to pass through the 4 bus pairs The f first slave device I and the second slave devices perform data transfer operations; and ^ reverse arbitration device, judges at least one sink row issued by the first slave devices, and selects-authorization Slave device, where the authorized slave device is allowed to perform the first-to-data transfer operation via the bus. Where I is the arbiter described in item 1 of the scope of patent application, wherein the first-order cutting mode includes at least one filter to filter the candidate second 31 200523747 main split and the first At least one bus use request issued by the master device. 3 · The arbiter described in item 2 of the scope of the patent application, wherein the screening program is a slave device busy state filtering unit, which is used to ignore the buses. Those slaves who are busy. 4. The arbiter described in item 2 of the scope of patent application, wherein the screening program is a request control filter unit, and when the bus is in a locked state, the request control filter unit ignores other main devices These bus usage requests were issued. 5. The arbiter described in item 4 of the scope of patent application, wherein the bus use requests are paired read-write operation bus use requests. 6. ^ The arbiter described in item 2 of the patent application scope, wherein the screening program is a last-request control filter unit, and when data transfer calls are performed with a stream pulse, the last-request control-over unit masks the The last clock request of the streaming pulse (3 such as Burst) to achieve a bus pipeline arbitration. 7. The arbiter described in item 1 of the scope of patent application, wherein the second stage arbitration module uses a fixed priority algorithm (bed algorithm) to select the candidate second master device. 32 200523747 8. The arbiter described in item i of the scope of patent application, wherein the first-stage arbitration module uses a single-loop arbitration algorithm (Roundundbin) to select the authorized master device. 9. The arbiter described in item 丨 of the patent application scope, wherein the reverse arbitration device uses a fixed priority algorithm (fixe (i pri〇rity alg0rithm) to select the authorized slave device. 10. An arbiter For arbitrating a data transfer operation of a bus, the bus is connected to a plurality of master devices and a plurality of slave devices, the arbiter at least includes: a forward arbitration device, at least one bus use request issued to the master devices Make a judgment and select an authorized master device, wherein the authorized master device is allowed to perform data transfer operations on the slave devices via the bus; and a reverse arbitration device, at least one bus use request issued by the slave devices Make a judgment and select an authorized slave device, wherein the authorized slave device is allowed to perform reverse data transfer operations on the master devices via the bus. 11. The arbiter according to item 10 of the scope of patent application, wherein The forward arbitration device uses a round-robin arbitration algorithm (Round Robin) to select the authorized master device. 33 200523747 The arbitration device of Zhiru's patent application scope uses a fixed-priority algorithm to select the authorized slave. 13. A kind of arbitration method, in-arbitration time in the material transfer operation, the bus is connected to a plurality of master devices. Arbitration_ is an idle state, a long interval, and a short interval cycle time. The arbitration method includes at least: 乂 When the arbitration time is in the interposed state, and the requests for the use of the buses of the master devices are only-low-optimal-sequence When the bus is busy, the cutting time is switched to the long interval cycle time; when the arbitration time is in the idle state, and the bus use request issued by the master devices includes the low priority bus use request and a high priority Please use the bus, the arbitration time is switched to the short interval cycle time; when the arbitration time is at the long interval cycle time or the short interval cycle time, and the bus use request issued by the master devices does not include the low priority When the sequential bus use request and the high priority bus use request are requested, the arbitration time is switched to the idle time. State; when the arbitration time is in the long interval cycle time and the bus use request sent by the master devices is the high priority bus use request, the arbitration time is switched to the short interval cycle time; and when the When the arbitration time is in the short interval cycle time, and the bus use request issued by the master devices is only the low priority bus use request 34 200523747 the interval cycle time, the arbitration time is switched to the long arbitration method, where This low-level read / write bus use request. 14. • The priority bus use request as described in item i3 and item i3 of the patent application scope is _ _ 15 · The arbitration method as described in item u of the application application scope, I φ 4 The priority order of the bus use request is up ^ 1¾ ^ ^ ^ ^ ffl ^ -¾ Requires the lock bus read-write pairing ϋ 々 々 丨 L row use master request or a mandatory item 冩 bus use request. 16. A method of reverse arbitration. When a plurality of first slave devices return 1 data to the plurality of first master devices, Zhongjiao 7 cuts the data transfer operation of the bus. The bus is connected to an arbiter, There should be a second brother and a master device, a plurality of second master devices, the first-slave devices, and a plurality of second slave devices, among which the first master device has priority over the second master devices. Priority, and the priority of the first-slave device is higher than the priority of the second slaves, the reverse arbitration method includes at least: The four slave devices issue at least one bus use request. The bus use requests issued by the first slave devices include a low priority bus use request and a high priority bus use request. The slave device of the high-priority bus use request is an authorized slave device, wherein the authorized slave device is allowed to perform reverse data transfer operations on the first master devices via the bus; and the slave device issued by the first slave devices When the bus use request is only the low-priority bus use request, the slave device authorized to issue the low-priority bus 35 200523747 uses the slave device to perform the first-to-reverse data transfer operation through the bus. Placement process 17. The reverse method described in item 16 of the scope of patent application, wherein the low priority bus use request is a reverse general answer request. -Writing the busbar ‘of the ® busbar 18 · The reverse arbitrator, as described in item 16 of the scope of patent application, The high priority bus usage request is a mandatory reverse read and write usage request. 36