TW200522352A - Silicon-controlled rectifier with dynamic holding voltage for on-chip electrostatic discharge protection - Google Patents

Abstract

An integrated circuit for electrostatic discharge protection that includes a silicon-controlled rectifier (SCR) including a substrate of a first dopant type, a semiconductor well of a second dopant type formed in the substrate, a first diffused region of the first dopant type formed in the semiconductor well, and a second diffused region of the second dopant type formed outside the semiconductor well, and a control circuit coupled to the SCR for providing a first holding voltage to the SCR to keep the SCR from latching-up during a first condition and providing a second holding voltage to the SCR to keep the SCR in the latch-up state during a second condition, the first holding voltage being different from the second holding voltage.

Description

200522352 发明 Description of the invention: [Technical field to which the invention belongs] The present invention relates to semiconductor devices, and in particular, it relates to an electrostatic discharge (Electrostatic Discharge) that does not occur latch-up during normal operation; ESD) protection element. [Prior Art] Semiconductor integrated circuits (1C), such as 1C with high-order full oxygen half (MOS) electric crystals, are generally susceptible to damage or damage by electrostatic discharge (ESD). Local-level MOS transistors traditionally have characteristics such as short channel lengths, low threshold voltages, and thin gate oxide layers. These MOS transistors, which are fabricated with deep sub-micron complementary CMOS process and have a lightly doped drain structure (1)) structure and silicide shield area, are more vulnerable to ESD damage. ESD 疋 refers to a large amount of positively or negatively charged current flowing to Ic in a short instant. There are many sources of this large current, such as human body and machine discharge, which are separately called human body * electric model weaving (HBM) and machine discharge model (mm). !! Knife is susceptible to damage by HBM and MM during knife manufacturing, transfer or handling. Bai Zhi's esd protective structure manufactured by C] V [0S process — NMOS / PMOS | __mm # + 祜 子 祜 儿 日 日 体, Shi Xi controlled rectifier 1 (SCR), diode, thick oxide layer element (F0m is the 4 4 + + child resistance, UOD) and the viable vertical / horizontal double carrier (BJT). In these Echidori n Shiwentian sun-like bodies, the ESD protection structure of Shibaizhi knows that SCr can be used in a small layout area due to its properties, such as financial-voltage.

The general CMOStH 200522352 used to make SCRs uses electricity that is higher than the holding voltage of SCRs. The holding voltage of S C R is generally about volts, and the second round ’is known as volts. Result ’* ESD caused by SCR latch: =: 2.7 to 5, SCR ^ it # ^ SnCR ^ 1 ^^: Noise and easy to form latch or transient latch. In the positive; the occurrence of ⑽ bolt lock 'is protected by this SCR = two-denier and even damaged. There are many techniques used in the bamboo thermal method to prevent the SCR from being issued during normal operation. The following is referred to as m in US Patent No. 6,031, Che, (hereinafter referred to as the 405 patent). Patent No. was awarded to its invention titled "ESD Anti-terrorist Road that does not lock up during the normal fall of the door during the wooden work of 4 people". Patent No. 405 discloses an ESD path consisting of a μ ~ and an on / off controller connected to a 1C gasket and a ground terminal. The on / off controller is connected to the cathode of the SCR. : During normal operation, even if there is noise interference, the on / off controller will open this ESD path to prevent latch-up. ’,,, and’ ESD current flows not only through the SCR, but also through the switching transistor. With this in mind, the on / off controller must be large enough for large ESD currents to pass. The transistor M1, which must occupy a larger wafer size area, is not only uneconomical in terms of today's j-size ESD protection components, but also does not use 0. Figure 2 shows another prior art. Figure 2 is Figure 4a of U.S. Patent No. 6 J72,404 (hereinafter referred to as Patent No. 404). Patent No. 404 was awarded to Chen et al., Whose invention is entitled "SCRESD protection with adjustable holding voltage". The patent No. 200522352 404 discloses an SCR having an n + region 40 in the N well region of the SCR. The resistor 50 is formed between the base of the pnp parasitic bipolar transistor and the n + region 40. The resistor 50 allows more current to pass, making it difficult for the pnp bipolar transistor to turn on. As a result, the holding voltage of the SCR is increased. The magnitude of the holding voltage depends on the position of the n + region 40 in the N well region. Although Patent No. 404 can raise the holding voltage of SCR to a level higher than the power supply voltage Vdd, once this holding voltage is determined, it cannot be adjusted. An SCR with this fixed, high holding voltage cannot withstand large ESD currents. In addition, under other conditions, the SCR with high holding voltage generates more heat than the SCR with lower holding voltage. In addition, the SCR with high holding voltage usually clamps ESD to a higher voltage than the power supply voltage Vdd. Voltage level, as this may damage internal circuits. SUMMARY OF THE INVENTION Therefore, the present invention relates to an ESD protection element, which can overcome many problems caused by the limitations or disadvantages of the foregoing prior art. The effects and advantages of the present invention will be described below, and some of the effects and advantages will become clearer with the description herein or the implementation of the present invention. The purpose and other advantages of the present invention can be understood from the following description, disclosure of patent application scope and illustrations. In order to achieve the above-mentioned objects and advantages, the present invention provides an integrated circuit for electrostatic discharge protection, which includes a silicon controlled rectifier (SCR) and a control circuit connected to the SCR to provide a first holding power of the SCR during a first condition. 200522352 is pressed to prevent the SCR from latching up, and a second holding voltage of the SCR is provided to keep the SCR in a latched state during the second condition, wherein the first holding voltage is different from the second holding voltage. In the present invention, the SCR includes a parasitic bipolar transistor and a parasitic resistance connected between the base and the emitter of the parasitic bipolar transistor, and the control circuit is connected in parallel with the parasitic resistor. In the present invention, the control circuit exhibits a resistance value smaller than the parasitic resistance during the first condition, and exhibits a resistance value greater than the parasitic resistance during the second condition. The invention also provides an integrated circuit for electrostatic discharge protection, which includes a MOS-triggered SCR, which includes a silicon controlled rectifier (SCR) and a metal-oxide-semiconductor (MOS) transistor connected to the SCR to trigger the SCR, and a A control circuit connected to the MOS-triggered SCR to provide a first holding voltage to the MOS-triggered SCR to prevent the MOS-triggered SCR from latching during a first condition, and to provide a second grip during a second condition Hold the voltage to the MOS-triggered SCR to keep the MOS-triggered SCR in a latched state, where the first holding voltage is different from the second holding voltage. In the present invention, the control circuit includes a capacitor having one end connected to a contact pad to couple a portion of the ESD voltage of the contact pad. The invention also provides an integrated circuit for electrostatic discharge protection, which includes a silicon controlled rectifier (SCR), which has a first doped substrate, a semiconductor well region formed in the substrate and a second doped semiconductor, A first diffusion region of a first doping type formed in a semiconductor well region, and a second diffusion region of a second doping type formed outside the semiconductor well region, and a control circuit 200522352, which Is connected to the SCR to provide a first holding voltage to the SCR during a first condition so that the SCR is not latched, and provides a second holding voltage to the SCR during a second condition to keep the SCR in a latched state, wherein The first holding voltage is different from the second holding voltage. The invention also provides an electrostatic discharge protection method, which includes providing a silicon controlled rectifier (SCR) with a first holding voltage, and controlling the holding voltage of the SCR to be higher than a power supply voltage during a first condition so that The SCR is not latched, and the holding voltage of the SCR is controlled to be lower than the power supply voltage during the second condition to keep the SCR in the latched state. In the present invention, the method further includes connecting the SCR between a first power line and a second power line. The invention provides an integrated circuit for electrostatic discharge protection, which includes a silicon controlled rectifier (SCR); a first conductive type first transistor, which is formed with the SCR integrated body and has a first gate; a second conductive A second transistor, which is integrated with the SCR, has a second gate; and a control circuit, which provides a first holding voltage to a first voltage applied to the first and second gates to The SCR prevents the SCR from being latched, and provides a second holding voltage to the SCR to maintain the SCR in a latched state in response to a second voltage applied to the first and second gates. The invention also provides an integrated circuit for electrostatic discharge protection, including a silicon controlled rectifier (SCR); a p-type transistor formed with the SCR integrated body; a n-type transistor formed with the SCR integrated body; one connected to Control circuits for p-type and η-type transistors, which provide a first voltage to the SCR so that the SCR is not latched, and a second voltage to the SCR to keep the SCR in the latched state 10 200522352. The invention also provides an integrated circuit for electrostatic discharge (ESD) protection, which includes a first power line with a first voltage level; a second power line with a second voltage level; a plurality of contact pads; Silicon controlled rectifiers (SCRs), each of which includes a p-type transistor and an n-type transistor, the p-type and n-type transistor and SCR are formed integrally; and a control circuit via the p-type and n-type The transistor provides a first holding voltage to the SCRs so that the SCRs are not latched, and a second holding voltage is provided to the SCRs through the p-type and n-type transistors to make the SCRs pulse on ESD. The latched state is maintained during the ESD period that occurs in one of the first power supply line or the contact pad. The invention also provides a method for electrostatic discharge protection, including providing a silicon controlled rectifier (SCR) with a holding voltage; forming a first conductive type first transistor and an SCR integrated body, the first transistor having a A first gate; a second transistor of a second conductivity type is integrated with the SCR, and the second transistor has a second gate; a first signal is provided to the first and second gates to improve the SCR Holding the voltage so that the SCR does not latch up; and providing a second signal to the first and second gates to reduce the holding voltage of the SCR to keep the SCR in a latched state. The invention also provides a method for providing electrostatic discharge (ESD) protection for internal circuits, which includes providing a first power line with a first voltage level; providing a second power line with a second voltage level; providing multiple Contact pads; multiple silicon controlled rectifiers (SCRs) are provided, each SCR includes a P-type transistor and an η-type transistor, the p-type and η-type 200522352 transistor and SCR are formed integrally; via p-type And a n-type transistor to provide a first holding voltage to the SCRs so that the SCRs are not latched; and a p-type and n-type transistor to provide a second holding voltage to the SCRs to enable the SCRs The latched state is maintained during the ESD period when the ESD pulse appears in one of the first power line or the contact pad. The foregoing general description of the present invention and the following detailed description are exemplary and illustrative in nature, and are intended to further understand the present invention. [Embodiment] An embodiment of the present invention will be described below with reference to the above drawings. Wherever possible, the same or similar components are represented by the same component numbers in the drawings. The present invention provides an ESD protection circuit having an SCR and a control circuit connected to the SCR to provide a first holding voltage of the SCR during a first condition so that the SCR does not latch up, and to provide an SCR during a second condition. The second holding voltage causes the SCR to latch up. That is, the SCR holding voltage is adjustable. In detail, the holding voltage of the SCR is increased to a first holding voltage higher than the power supply voltage, so that the SCR is not locked during normal operation, and the holding voltage of the SCR is reduced to a value lower than the power supply voltage. This keeps the SCR latched during ESD. FIG. 3 is a circuit diagram of the SCR 60 and the control circuit 74 according to an embodiment of the present invention. Referring to FIG. 3, the SCR 60 includes a parasitic ρηρ double-carrier transistor 62, a parasitic ηρη double-carrier transistor 64, an N-well resistance 66, 12 200522352, a substrate resistance 68 (Rsub), and a parasitic resistor Parasitic resistances 70 (RS1) and 72 (RS2) between the transistor 62 and 64. The holding voltage% of SCR 60 refers to the voltage drop between anode 76 and cathode 78 of SCR 60. The control circuit has a resistance value R 'in this circuit. Paralleling the resistance R of the control circuit 74 with the body pen resistance Rsub ’Vh can be expressed by the following formula: /

Vh ~~ TVcep + vben X [1 + RS2 / (Rsub || R ')] where Vcep is the voltage between the collector (not labeled) and emitter (not labeled) of the pnp transistor 62' Vben is the npn transistor The voltage between the base of 64 (unlabeled) and the emitter ^ (# 未 标 ^. Therefore, when R 'is far less than ^, the value of Vh increases, and if R is much greater than Rsub, the value of vH decreases. Figure 4 is Figure 3 The π characteristic curve of SCR 60 shown. SCR 60 has a holding voltage VH and a trigger voltage Vtrig. Please refer to Figure 4, VH can be dynamically adjusted between, vH1 and, if R is much smaller than u, then coffee The I-V curve is curve A. If R 'is far greater than ^, then the curve of SCR6〇 is curve B. That is, the resistance of SCR60 can be held by changing the resistance of r' in parallel with the substrate resistance The voltage Vh is increased to vH2 that is greater than the power supply voltage ^, or% is reduced to a value that is less than Vdd. In the embodiment, VH1 is approximately equal to νΗ. In another embodiment,% is approximately] volts. 5 is a cross-sectional view of the layout of an E s D protective circuit 82 according to an embodiment of the present invention. See FIG. 5. The ESD protective circuit 82 includes a loop 84 and a control circuit 86. The SCR 84 has a p-type curved body e 88 , N well area 90 The first p-type diffusion region formed in the n-well region, the second-type P-type diffusion region 94 partially formed in the n-well region%, and the first-type diffusion region 96 partially formed in the m-well region%. The -P Type diffusion region 92, n-well region 90 disks, p 13 200522352 type substrate 88 are the emitter, base, and collector of parasitic pnp bipolar transistor (not labeled). Η-well region 90, p-type substrate 88, and A p-type diffusion region 96 is a collector, a base, and an emitter of a parasitic ηρη transistor (not labeled). The SCR 84 also includes a gate 100 located above a channel (not labeled), and the channel is formed at the first Between the first and second P-type diffusion regions 92 and 94. The thick oxide layer 102 is used for electrical insulation. The first p-type region 92, the gate electrode 100, and the second n-type region 104 are connected to the contact pad 108 For example, it is an I / O pad. The first n-type region 96 and the third p-type region 106 are connected to a reference voltage such as Vss or ground. The control circuit 86 includes an NMOS transistor 107, a resistor 110, and a capacitor 112. The NMOS transistor 107 has a terminal (not labeled) connected to the second p-type diffusion region 94 of the SCR 84. One end (not labeled) of the resistor 110 Connected to the gate (unlabeled) of capacitor 112 and NMOS transistor 107, and the other end (unlabeled) to the power supply voltage Vdd. One end (unlabeled) of capacitor 112 is connected to the gate of resistor 110 and NMOS transistor 107 , The other end (unlabeled) is connected to Vss. In the ESD protection circuit 82, the control circuit 86 has a resistance value smaller than the SCR 84 substrate resistance when the NMOS φ transistor 107 is turned on, and has a resistance greater than when the NMOS transistor 107 is turned off. The resistance value of the base resistance of SCR 84. During normal operation, the RC circuit composed of the resistor 110 and the capacitor 112 provides a high level signal to the gate of the NMOS transistor 107 to start the NMOS transistor 107. As a result, the resistance value presented by the control circuit 86 is smaller than the substrate resistance of the SCR 84. The holding voltage of the SCR 84 is raised to a level higher than Vdd, so that the SCR 84 does not latch up. 14 200522352 During ESD, the RC circuit provides a low level signal to the gate of NMOS transistor 108 and turns off NMOS transistor 107. As a result, the resistance value exhibited by the control circuit 86 is smaller than the substrate resistance of the SCR 84. The holding voltage of the SCR 84 is adjusted to a level lower than Vdd, for example, about 1 volt, so that the SCR 84 is kept in a latched state to discharge ESD current. In order for the RC circuit to keep the gate of the NMOS transistor 107 at a low voltage level when ESD occurs, the RC time delay of the RC circuit is set to about 300 nanoseconds (ns) to 500 nanoseconds, which is 150 ns more than the average ESD pulse. Up to 300 ns is long. FIG. 6 is another ESD protection circuit 114 according to an embodiment of the present invention. Referring to FIG. 6, the ESD protection circuit 114 has an SCR 84 and a control circuit 116. The control circuit includes a PMOS transistor 118, an inverter 124, a diode 126, a resistor 120, and a capacitor 122. The PMOS transistor 118 has a source (not labeled) connected to the second p-type diffusion region 94 of the SCR 84. The inverter 124 has an output terminal (not labeled) connected to a gate (not labeled) of the PMOS transistor 118. One terminal (not labeled) of the resistor 110 is connected to one input terminal (not labeled) of the capacitor 122 and the inverter 124, and the other terminal (not labeled) is connected to Vdd. One terminal (not labeled) of the capacitor 122 is connected to the input terminal of the resistor 120 and the inverter 124, and the other terminal (not labeled) is connected to Vss. In the ESD protection circuit 114, the control circuit 116 exhibits a resistance value smaller than the substrate resistance of the SCR 84 when the PMOS transistor 118 is turned on, and exhibits a resistance value larger than the substrate resistance of the SCR 84 when the PMOS transistor 118 is turned off. During normal operation, the RC circuit composed of the resistor 120 and the capacitor 122 provides a low level signal to the gate of the PMOS transistor 118 via the inverter 124 to activate the PMOS transistor 118. As a result, the resistance of the control circuit 116 is lower than that of the SCR 84 substrate. The holding voltage of the SCR 84 is raised to a level higher than Vdd, so that the SCR 84 does not latch up. During the ESD period, the RC circuit keeps the input of the inverter 124 at a low voltage level due to the time delay. At the same time, part of the ESD voltage from the contact pad 108 biases the inverter 124 so that the inverter 124 outputs a high voltage level to the gate of the PMOS transistor 118 and turns off the PMOS transistor 118. As a result, the resistance value exhibited by the control circuit 116 is larger than the substrate resistance of the SCR 84. The holding voltage of the SCR 84 is adjusted to a level lower than Vdd, for example, about 1 volt, so that the SCR 84 is kept in a latched state to discharge ESD current. FIG. 7 is a circuit diagram of the SCR 128 and the control circuit 130 according to the embodiment of the present invention. Referring to FIG. 7, the SCR 128 includes a parasitic pnp bipolar transistor 132, a parasitic npn bipolar transistor 134, an N-well resistance 136 or RNW, a substrate resistance 138, and a parasitic transistor formed. Parasitic resistances 140 (RS3) and 142 (RS4) between 132 and 134. The holding voltage Vh of the SCR 128 refers to the voltage drop between the anode 146 and the cathode 148 of the SCR 128. The control circuit 130 has a resistance value of R ”in this circuit. The resistance R ′ ′ of the control circuit 130 is connected in parallel with the base resistance RNW, and the holding voltage Vh of the SCR 128 can be expressed by the following formula:

Vh ~ Vcen + Vbep X [1 + Rs3 / (RnW II R '')] where vcen is the voltage between the collector (not labeled) and emitter (not labeled) of the npn transistor 134, RS3 is formed in a parasitic type The parasitic resistance between the transistors 132 and 134, Vbep is the voltage between the base (not labeled) and the emitter (not labeled) of the pnp transistor 132. Therefore, when R '' is less than Rnw, the value of Vh increases, and if R '' is greater than RNW, the value of Vh decreases. The I-V characteristic curve of Fig. 7 is similar to that of Fig. 16 200522352, so it will not be described further. FIG. 8 is an ESD protection circuit 15o according to an embodiment of the present invention. Referring to FIG. 8, the ESD protection circuit 150 includes an SCR 128 and a control circuit 130. The SCR 128 has a p-type substrate 152, an n-well region 154, a first p-type diffusion region 156 formed in the n-well region 154, a first n-type diffusion region 158 partially formed in the n-well region 154, and a portion formed in A second n-type diffusion region 160 in another n-well region 162. The first p-type diffusion region 156, the n-well region 154, and the p-type substrate 152 are the emitter, base, and collector of a parasitic ρηρ bipolar transistor (not labeled), respectively. The n-well region 154, the P-type substrate 152, and the second n-type diffusion region 160 are the collector, base, and emitter of a parasitic ηρη transistor (not labeled), respectively. The SCR 128 also includes a gate electrode 164 located above the channel (not labeled), and this traffic is formed between the first and second n-type diffusion regions 158 and 160. The first p-type region 156 and the third n-type region 168 are connected to the contact pad 170. The second patterning region 160 and the second p-type region 172 are connected to ν. The control circuit 130 includes a PMOS transistor 174 and an inverter ρ. The diode 178, the resistor 180, and the capacitor 182QpMOS transistor m have an electrode (not labeled) connected to the first n-type diffusion region 158 of the SCR 128. The inverting phase 176 has an output terminal (not labeled) connected to the gate (not labeled) of the pMOS transistor η. The-terminal (not labeled) of the resistor 180 is connected to the input terminal (not labeled) of the capacitor 18 and the inverter 176, and the other-terminal (not labeled) is connected to: the pole body 178 and Vdd. One end (unlabeled) of the capacitor 182 is connected to the resistor ... and the input terminal of phase 176 is connected, and the other end (unlabeled) is connected to the protective circuit 1 50, which controls the thunder policy n η μ μ τ cylinder thorn The package circuit 130 has a resistance value smaller than that of the n-well area of the SCR128 when the pmos transistor m is turned on. The PM0S1 200522352 crystal 174 has a resistance value greater than the n-well area resistance of the SCR 128 when it is turned off. During normal operation, the RC circuit composed of the resistor 180 and the capacitor 82 provides a low level signal to the gate of the PMOS transistor 174 via the inverter 176 to activate the PMOS transistor 174. As a result, the resistance value presented by the control circuit 130 is smaller than the n-well resistance of the SCR 128. The holding voltage of SCR 128 is raised to a level higher than Vdd, so that SCR 128 cannot be locked. During the ESD period, the RC circuit keeps the input of the inverter 176 at a low voltage level due to the time delay. At the same time, a portion of the ESD voltage from the contact pad 170 biases the inverter 176 so that the inverter 176 outputs a high voltage level to the gate of the PMOS transistor 174 and turns off the PMOS transistor 174. As a result, the resistance value presented by the control circuit 130 is larger than the n-well resistance of the SCR 128. The holding voltage of SCR 128 is adjusted to a level lower than Vdd, for example, about 1 volt, so that SCR 128 is kept in a latched state to discharge ESD current. FIG. 9 is an ESD protection circuit 184 according to an embodiment of the present invention. Referring to FIG. 9, the ESD protection circuit 184 includes an SCR 128 and a control circuit 186. The control circuit 186 includes an NMOS transistor 188, a resistor 190, and a capacitor 192. The NMOS transistor 188 has a source (not labeled) connected to the first n-type diffusion region 158 of the SCR 128. One terminal (not labeled) of the resistor 190 is connected to the gate (not labeled) of the capacitor 192 and the NMOS transistor 188, and the other terminal (not labeled) is connected to the power supply voltage Vdd. One terminal (not labeled) of the capacitor 192 is connected to the gate of the resistor 190 and the NMOS transistor 188, and the other terminal (not labeled) is connected to Vss. In the ESD protection circuit 1 84, the control circuit 1 86 has a resistance value smaller than the η well area resistance of the SCR 128 when the NMOS transistor 188 is turned on, and has a resistance value greater than the η 18 well area of the SCR 128 when the NMOS transistor 188 is turned off. Of resistance. During normal operation, a circuit consisting of a resistor 190 and a capacitor 192 provides a high level signal to the open terminal of the coffee transistor 188 to start the NMOS transistor 188. As a result, the resistance value presented by the control circuit 186 is smaller than the n-well area resistance of the scr 128. The holding voltage of SCR 128 is raised to a level higher than Vdd, so that SCR 128 does not latch up. . ° During ESD, due to the time delay, the RC circuit keeps the gate of transistor 188 at a low voltage level and turns off the NMOS transistor. As a result, the resistance value presented by the control circuit 186 is greater than the n-well resistance of the SCR 84. The holding voltage of SCR 128 is adjusted to a level lower than Vdd, which is about 1 volt in the second example, so that SCR 128 is kept in a latched state to discharge ESD current. Figure ο is an ESD protection circuit 194 for vdd to vssESD protection. Please refer to FIG. 10. The ESD protection circuit 194 includes a PMOS trigger SCR 196 and a control circuit 198. The structure of the ESD protection circuit 194 is similar to that of the circuit 82 of FIG. 5, but it also contains a PMOS transistor 200. The pM0s trigger SCR 196 includes an SCR (unlabeled) and a PMOS transistor 200. This SCR has a p-type substrate 406 (Psub), an n-well region 404 (NW), a p-type diffusion region 402 (p +), an n-type diffusion region 408 (η +), and a parasitic resistance 410 (Rnw), 412 (Rsub). The PMOS transistor 200 has a source (not labeled) connected to the p + region 402, a drain (not labeled) connected to the p-type substrate 406, and a substrate (not labeled) connected to the n-well region 404 of the SCR. The control circuit 198 includes an NMOS transistor 202, a resistor 204, and a capacitor 206. One end (not labeled) of the resistor 204 is connected to the capacitor 206, the gate (not labeled) of the PMOS transistor 200 and the gate (not labeled) of the NMOS transistor 202, and the other end (not labeled) is connected to Vdd. 19 200522352 Electric valley 2 0 6-one end (not ^ Gu ,, ▲ & bluff) is connected to resistor 204, PMOS transistor 2〇〇

The gate of NMOS is the gate of the ship L Erri Sun body 202, and the other end (not labeled) is connected to Vss. ESD anti-tank

In the 7-side circuit 194, the control circuit 198 has a resistance value less than pM0s that triggers the SCR i% of the substrate resistance when the NMOS circuit is turned on, and it has a resistance greater than PM when the NMOS transistor 202 is turned off. 〇s Trigger the resistance value of the substrate resistance of SCR 196.

During normal operation, an rc circuit composed of a resistor 204 and a capacitor 206 provides a K-level signal to the gates of the PMOS transistor 200 and the NMOS transistor 202 to turn off the pM0s transistor 200 and turn on the nms. Transistor 202. As a result, the resistance value presented by the control circuit 198 is smaller than the substrate resistance of the PMOS-triggered SCR 196 ^. pM〇s triggers the holding voltage of scr 196 to rise to a level below Vdd, so that PMOS triggers SCR 196 without latching.

During the ESD period, for example, a positive polarity ESD appears on the Vdd line. Due to the inter-day delay, the RC circuit provides a low level signal to the gate of the pM0s transistor 200 and the NMOS transistor 200 to turn on the pM. 〇s transistor 2〇 (] Sub-turn off the NMOS transistor 200. As a result, the negative value presented by the control circuit 198 is larger than the substrate resistance of the PMOS triggering SCR 196 qPM. The triggering voltage of the sc 196 is reduced to less than V heart level, for example, about 1 volt, seven PMOS triggers SCR 196 to stay in a latched state to discharge ES] □ current. Figure 11 is another ESD protection circuit 208 for vdd to Vss ESD protection. Please refer to In Figure U, the ESD protection circuit 208 includes an NMOS triggering SCR 210 and a control circuit 212. The structure of the ESD protection circuit 208 is similar to that of the circuit 150 of FIG. 8 ', but it also includes an NMOS transistor 21h. The NMOS triggering SCR 210 includes an SCR (unlabeled) and NMOS transistor 214. This SCR device 20 200522352 has P-type diffusion region 414 (p +), n-well region 416 (NW), p-type substrate 418 (Psub), n-type diffusion region 420 (n +), and parasitic resistance 422 (RNW ), 424 (Rsub). The NMOS transistor 214 has a drain (not labeled) connected to the n + region 420, and a source (not labeled) ) Is connected to the n-well region 416 and a substrate (not labeled) is connected to the SCR-type substrate 418. The control circuit 212 includes a PMOS transistor 216, an inverter 218, a resistor 220, and a capacitor 222. The inverter 218 has an output The terminal (not labeled) is connected to the gate (not labeled) of the NMOS transistor 214 and the gate (not labeled) of the PMOS transistor 216. One terminal (not labeled) of the resistor 220 is connected to the input of the capacitor 222 and the inverter 218 Terminal (not labeled), the other terminal (not labeled) is connected to Vdd. One terminal (not labeled) of the capacitor 222 is connected to the input terminal of the resistor 220 and the inverter 218, and the other terminal (not labeled) is connected to Vss. ESD In the protection circuit 208, when the PMOS transistor 216 is turned on, the control circuit 212 has a resistance value smaller than the n-well area resistance of the NMOS-triggered SCR 210, and when the PMOS transistor 216 is turned off, it has a resistance greater than the n-well area resistance of the NMOS-triggered SCR 210. During normal operation, the RC circuit composed of resistor 220 and capacitor 222 provides a low level signal to the gate of NMOS transistor 214 and PMOS transistor 216 via inverter 218 to turn off NMOS transistor 214 and turn it on. PMOS Transistor 216 As a result, the resistance value of the present control circuit 212 than NMOS η SCR 210 triggers the resistance of the well region holding small .NMOS trigger voltage of the SCR 210 is increased to above the level of Vdd, the NMOS triggered SCR 210 will not latch. During ESD, for example, positive ESD appears on the Vdd line. Due to the time delay, the RC circuit provides a high level signal to the 200522352 NMOS transistor 214 and the gate of the PMOS transistor 216 through the inverter 218 to turn on the NMOS. The crystal 214 also turns off the PMOS transistor 216. As a result, the resistance value presented by the control circuit 2i2 is larger than that of the 11 well area triggered by the NMOS triggering 8012110. The holding voltage of NMOS triggering SCR 210 is adjusted to a level lower than Vdd, for example, about 1 volt, so that NM0S triggers SCR 21 and maintains the latched state to

Discharge E S D current. N FIG. 12 is an input stage ESD protection circuit 224 according to an embodiment of the present invention. Referring to FIG. 12, the ESD protection circuit 224 includes a PMOS triggering SCR 226, a first control circuit 228, an NMOS triggering SCR 230, and a second control circuit 232. The PMOS trigger SCR 226 includes an SCR (not labeled) and a PMOS transistor 234. The first control circuit 228 includes a resistor 236, a capacitor 238, and an NMOS transistor 240. The NMOS triggering SCR 230 includes another SCR (not numbered) and an NMOS transistor 242. The second control circuit 232 includes a resistor 244, a capacitor 246, and a PMOS transistor 248. During normal operation, as far as the PMOS triggers the SCR 226, the PMOS transistor 234 is turned off and the NMOS transistor 240 is turned on. Since the NMOS transistor 240 of the first control circuit 228 is turned on, the holding voltage of the PMOS trigger SCR 226 is increased to a level higher than Vdd, so that the PMOS trigger SCR 226 does not latch up. As far as the NMOS triggering SCR 230 is concerned, the NMOS transistor 242 is turned off and the PMOS transistor 248 is turned on. Since the PMOS transistor 248 of the second control circuit 232 is turned on, the holding voltage of the NMOS triggering SCR 230 is raised to a level higher than Vdd, so that the NMOS triggering SCR 230 does not latch up. During the positive polarity Vss (PS) mode ESD, the capacitor 246 couples the contact 22 200522352 part of the ESD voltage of the pad 250 to the gate of the NMOS transistor 242 and the PMMOS transistor 248. Therefore, the gate of the NMOS transistor 242 is pMOS: the gate of the body 248 is positively biased so that the NMOS transistor 242 is turned on and the pMOS transistor 248 is turned off. As the pM0s transistor 248 of the second control circuit 232 is turned off, the holding voltage of the SCR 230 triggered by NMOS is reduced to a small value.

The level of Vdd, for example, about 1 volt, causes the NMOS to trigger the SCR 23 to maintain the latched state. In addition, since the NMOS transistor 242 is turned on, the Nm0 trigger SCR 230 can be quickly turned on to discharge the ESD current. The eSD precautions'%% 224 will appear on the contact pad 250 with a positive ESD voltage clamp at approximately volts. 1 During negative-to-Vdd (ND) mode ESD, the capacitor 238 performs a portion of the ESD voltage that touches the pad 250 to the gate of the NMOS transistor 240 and the surface transistor 234. Therefore, the gates of the NMOS transistor 240 and the PMOS transistor 234 are negatively biased to cause the NMOS transistor 240 to be turned off and the% transistor 234 to be turned on. Due to the NMOS of the first control circuit 228. 224 240 is turned off, the PMOS triggers the holding voltage of the SCR 226 to be lowered to a level lower than γ, for example, about -1 volts, so that the PMOS triggers the SCR 226 to remain private or locked. In addition, since the PMOS transistor 234 is turned on, PMOS 226 can be turned on quickly to discharge ESD current. The ESD protection voltage will appear at the negative ESD voltage clamp of the contact pad 250 located in Yot. FIG. 13 shows an input stage ESD protection circuit & 252 according to another embodiment of the present invention. Please refer to FIG. 13, the ESD protection circuit 252 includes a PMOS touch sound 254, a first control circuit 256, an NMOS triggering SCR 258 and a first; 23 200522352 circuit 260. The PMOS trigger SCR 254 includes an SCR (not labeled) and a pMOS transistor 262. The first control circuit 256 includes a resistor 264, an inverter 266, and an NMOS transistor 268 ° NMOS triggering SCR 258 includes another SCR (not labeled) and an NMOS transistor 270. The second control circuit 260 includes a resistor 272, an inverter 274, and a PMOS transistor 276. During normal operation, as far as PMOS triggers SCR 254, inverter 266 provides a high voltage level to the gates of pmos transistor 262 and NMOS transistor 268 to turn off PMOS transistor 262 and turn on NMOS transistor 268. . Since the NMOS transistor 268 of the first control circuit 256 is turned on, the holding voltage of the PMOS trigger SCR 254 is raised to a level higher than ~, so that the PMOS trigger SCR 254 does not latch up. As far as the NMOS triggering SCR 258 is concerned, the inverter w provides a low level of waste to the junction of the NMQS transistor 27 and the pMOS transistor, so that the NMOS transistor 270 is turned off and off and the transistor 276 is turned on. Since the PMOS of the second control circuit 260 is turned on from the% crystal 276, the NM0S triggers the holding voltage of the SCR 258 to be raised to a high level, so that the NMOS triggers the SCR 258 without latching. During the PS mode ESD, and l. ≫ 'The phase generator 274 is biased by the PSD ESD voltage of the contact pad 278 to provide a voltage level to the NMOS transistor 270 and the PMOS transistor 276 q gate . Therefore, the gate of the NMOS transistor 270 and the PMOS transistor 276 | χ μ ^ 'Positive bias causes the NMOS transistor 艚 270 to turn on and the PMOS transistor 276 to turn off: the body name is m1. Since the PMOS transistor 276 of the second control circuit 260 is turned off, δ, ^ v triggers the holding voltage of SCR 258 and adjusts IV to a level less than vdd, for example

, 々 1 volt, so that NMOS triggers SCR 200522352 258 to remain locked. In addition, since the NMOS transistor 27 is turned on, the NMOS trigger SCR 258 can be turned on quickly to discharge ESD current. The ESD protection circuit 252 clamps the positive polarity ESD voltage appearing on the contact pad 278 to about 1 volt. During the ND mode ESD, the inverter 266 is biased by a portion of the ESD voltage of the contact pad 278 to provide a low voltage level to the gates of the NMOS transistor 268 and the PMOS transistor 262. Therefore, the gates of the NMOS transistor 268 and the PMOS transistor 262 are negatively biased so that the NMOS transistor 268 is turned off and the PMOS transistor 262 is turned on. Since the NMOS transistor 268 of the first control circuit 256 is turned off, the holding voltage of the PMOS triggering SCR 254 is adjusted to a level lower than Vdd, for example, about -1 volt, so that the PM0s triggering the SCR 254 is kept in the latched state. In addition, since the pmos transistor 262 is turned on, the PMOS trigger SCR 254 can be quickly turned on to discharge the ESD current. The ESD protection circuit 252 will appear at the negative ESD voltage of the contact pad 278 at about -1 volts. FIG. 14 is an output stage ESD protection circuit 28 of the embodiment of the present invention. Referring to FIG. 14, the ESD protection circuit 280 includes a PMOS triggering SCR 282, a first control circuit 284, an NMOS triggering SCR 286, and a second control circuit 288. The PMOS trigger SCR 282 includes an SCR (not labeled) and a pMOS transistor 290. The first control circuit 284 includes a resistor 292, a capacitor 294, and an NMOS transistor 296. The NMOS trigger SCR 286 includes another SCR (not numbered) and an NMOS transistor 298. The second control circuit 288 includes a resistor 300, a capacitor 302, and a PMOS transistor 304. The first buffer 306 and the second buffer 308 are used to buffer the signals sent from the internal circuit (not shown) to the contact pad 310 200522352. During normal operation, for the PMOS triggering SCR 282, the gates of the PMMOS transistor 290 and the NMOS transistor 296 are connected to Vdd via a resistor, so that the PMOS transistor 29 is turned off and the NMOS transistor 296 is turned on. Since the NMOS transistor 296 of the first control circuit 284 is turned on, the holding voltage of the PM0S triggering the SCR 282 is increased to a level higher than Vdd, so that the pM0s triggering the SCR 282 does not latch up. As far as the NMOS trigger SCR 286 is concerned, the gates of the NMOS transistor 298 and the PMOS transistor 304 are connected to vss via a resistor 300, so that the NMOS transistor 298 is turned off and the PMOS transistor 304 is turned on. Since the PMOS transistor 304 of the second control circuit 288 is turned on, the holding voltage of the NMOS triggering SCR 286 is increased to a level higher than Vdd, so that the NMOS triggering SCR 286 does not detect the lock. During the PS mode ESD, the capacitor 302 couples part of the ESD voltage of the contact pad 31 to the gate of the NMOS transistor 298 and the PMOS transistor 304. Therefore, the gates of the NMOS transistor 298 and the PMOS transistor 304 are positively biased so that the NMOS transistor 298 is turned on and the PMOS transistor 304 is turned off. Since the PMOS transistor 304 of the second control circuit 288 is turned off, the holding voltage of the NMOS triggering SCR 286 is adjusted to a level lower than Vdd, for example, about 1 volt, so that the NMOS triggering SCR 286 is kept in a latched state. In addition, because the NMOS transistor 298 is turned on, the NMOS trigger SCR 286 can be turned on quickly to discharge ESD current. The ESD protection circuit 280 will appear on the positive ESD voltage clamp of the contact pad 310 at about! volt. During the ND mode ESD, the capacitor 294 couples the contact pads 31 to 26 200522352 part of the ESD voltage to the gates of the NMOS transistor 296 and the pMOS transistor. Therefore, the gates of the NMOS transistor 296 and the PMOS transistor 29 are negatively biased to cause the NMOS transistor 296 to turn off and the PMOS transistor 29 to turn on. Since the NMOS transistor of the first control circuit 284 is turned off, the holding voltage of the PMOS triggering SCR 282 is adjusted to a level lower than Vdd, for example, about volts, so that the PMOS triggering SCR 282 is maintained in the lock detection state. In addition, since the PM0S transistor is turned on, pM0s trigger_282 can be turned on quickly to discharge ESD current. A thin protective circuit will appear on the contact pad 31 and the negative voltage clamp is located at about 4 volts.

FIG. M is an output stage ESD protection circuit 312 according to another embodiment of the present invention. Referring to FIG. 15, the ESD protection circuit 312 includes a PMOS triggering SCR 314 throttling circuit (not labeled), an NMOS triggering SCR 316 and a second working system fast circuit. (Unbluffed). The PM0s triggering SCR includes one (not labeled with PMOS transistor 318. The first control circuit includes a resistor ㈣, a combination, and an NMOS transistor 324. The NMOS triggering SCR 316 includes another number below) and an NMOS transistor 326. The second control circuit includes a fast resistor / inverter 328 and a PMOS transistor 33G. The first—buffer The first, second, and third punches are 334 to buffer the signal sent from the internal circuit (not shown) to the contact pad 336. During normal operation, as far as PM0s triggers scr 314, the rc circuit composed of resistor 320 and capacitor 322 provides a high level signal to the gates of ΓΓ transistor 318 and transistor 324 to turn off PMOS.笔 晶 318 和 闻 # + 文 NMOS 龟 晶 324. As the first control circuit's NMOS electronic crystal office ^ # turned on, the PM s triggers the SCR314i to hold the power 27 200522352 The voltage is raised to a level higher than Vdd, so that the PMOS triggers the SCR 314 without latching. As for the NMOS triggering SCR 316, the RC circuit provides a low voltage level to the gate of the NMOS transistor 326 and the PMOS transistor 330 via the inverter 328 to turn off the NMOS transistor 326 and turn on the PMOS transistor 330. Since the PMOS transistor 330 of the second control circuit is turned on, the holding voltage of the NMOS triggering SCR 316 is increased to a level higher than Vdd, so that the NMOS triggering SCR 316 does not latch up during normal operation. During PS mode ESD, part of the ESD current flows to the Vdd line through a parasitic diode (not shown). This parasitic diode system is diffused by the p-type in the PMOS transistor (not labeled) of the second buffer 334. Area (not shown) and η well area. The RC circuit provides a high voltage level to the gates of the NMOS transistor 326 and the PMOS transistor 330 through the inverter 3 2 8 due to the time delay, so that the NMOS transistor 326 is turned on and the PMOS transistor 330 is turned off. Since the PMOS transistor 330 of the second control circuit is turned off, the holding voltage of the NMOS triggering SCR 316 is adjusted to a level lower than Vdd, for example, about 1 volt, so that the NMOS triggering SCR 316 is kept in a latched state. In addition, since the NMOS transistor 326 is turned on, the NMOS trigger SCR 316 can be turned on quickly to discharge ESD current. The ESD protection circuit 312 will clamp the positive ESD voltage appearing on the contact pad 336 at about 1 volt. During the ND mode ESD, part of the ESD current flows to the Vss line through a parasitic diode (not shown). This parasitic diode system is diffused by the n-type in the NMOS transistor (not labeled) of the second buffer 334 Area (not shown) and ρ well area. Because the capacitor 322 is coupled to the part of the contact pad 336 28 200522352 ESD voltage, the RC power failure and the PMOS transistor 3l /, a low power level to the NMOS transistor 324 PM0S transistor 3 1 8 gate = urgent / official NM〇S The transistor 324 is turned off and the body seems to be turned off. The nTH control circuit controls the level of the NEG crystal vdd of the circuit, for example, the holding voltage of m / 14 is adjusted to be less than the latched state. In addition, the SCR 314 hold is triggered by the two two P Satoshi

Triggering the SCR3H can quickly open the door and the discharge transistor 318 is turned on. PM0S 3! 2 will appear on the contact pad / 3 = discharge: Dp current. Lake protection circuit The negative ESD voltage clamp of cymbal 336 is located at about volts.

FIG. 16 is an ESD protection life path 338 for a mixed pressure human wheel output stage according to an embodiment of the present invention. Please refer to _16. The coffee protection circuit includes pM0s ^ SCR 34o and control circuit (not labeled). The pM0s trigger scr is said to contain two crystals (not labeled) and a PMOS transistor 342. The control circuit includes a resistor and capacitor 346 and an NMOS transistor 348. 4. During normal operation, it is composed of resistors and capacitors 346. Circuit supply-high level signal to delete transistor 348 and PM〇s you

Between 2 and 342, the NM0S transistor 348 is turned on and the PM0 is turned off. "(Since the control circuit is turned on, the transistor 348 is turned on, which triggers the SCR 340 to hold the sense of life, but it is included. Top ^ Sumtun presses to the end The level of Vdd makes ρΜγ

Triggering the SCR 340 does not cause aluminum bolting. During the period when τ W is locked in the positive phase, the PMOS transistor & 342 may be accidentally turned on due to the existence of the positive-polarity source switch ^, p $ 5 to the gate voltage, and leakage current. In the embodiment of the present invention, in order to prevent the leakage of the PMOS transistor during normal operation, a diode string 350 is connected to the trigger SCR 340 in the face 42 muscle system. 29 200522352 During ESD, for example, positive polarity ESD appears in the contact pad. ESD current flows through -parasitic diode 354 to diode string 35_p_ triggers SCR 340. This parasitic diode 354 is controlled by _s transistor. Shaped by pole (unlabeled) and base (unlabeled). Because the time delay circuit provides a low level signal to the gate of nmos pure u master MOS transistor 348 and the gate of PMOS% body 342 to turn off the NMOS thundering body ~ 0 day and day body 348 and turn on the PMOS power Crystal 342. Since the NMOS transistor 34s will be turned off tomorrow, the PMOS triggers the holding voltage of the SCR340 to be lowered to less than the V's carry dry ', so that the PMOS triggers the SCR 340 to remain locked. Also, since PlUnc +

When the Mos transistor 342 is turned on, the PMOS trigger can be turned on quickly to discharge the coffee current. HD protection circuit = set positive = ESD voltage at a level below ^, and this level depends on the number of diodes in a pole string 350. FIG. 17 is an example of a mixed-voltage life-saving circuit in the embodiment of the present invention-Li Gang bit ▲ circuit m 17 of the i-source ESD protection circuit 33 δ 'The circuit example discussed is connected to a high-voltage line. ^ Heart: ^. ”Low The ESD protection circuit 358 between the enclosed lines includes the ESD protection circuit connected between the two low voltage circuits VV and the voltage lines V such as Vdd, Vdd2 and the two low voltage lines Vw and VSS2. Figure 18 shows the present invention. The embodiment uses NM〇f 60. The power supply ESD protection circuit 362 Weifa, SCR 364, and the mixed tank Diyao and Chalachen-# See Figure 18, ESD protection 4 packet road 362 is connected to the first-power line door. Λ —Apricot and prince power line 370. In a yoke example, the first thunder 370 is better than Λ ancient wish +, shield green, ", table road 368 and the second power line 370 ^ Press the power supply line, for example ~ 2. In another embodiment, the ι = 370 of the same voltage level is lower than the A plate voltage +, / 5 green, Λ, Ι, 368, and the second power line 370 are all lower. Power line, such as phase, Vssl of the same voltage level, 200522352

Vss2. The ESD protection circuit 362 includes a NMOS triggering SCR 364 and a control circuit 366. The NMOS trigger SCR 364 includes an SCR (not labeled) and an NMOS transistor 372. The control circuit 366 includes a resistor 374, a capacitor 376, and a PMOS transistor 378. It is assumed that the voltage level of the first power line 368 is higher than the voltage level of the second power line 370, such as Vddi > Vdd2. During normal operation, the RC circuit composed of resistor 374 and Kariya 376 provides the voltage level of vdd2. To the gate of NMOS transistor 372 and PMOS transistor 378. At this time, the PMOS transistor 378 is turned on because its source potential, that is, vddl, is greater than its interrogation potential Vdd2. At the same time, the NMOS transistor 372 is turned off because its gate and source equipotential are both Vdd2. Since the transistor 378 of the control circuit 366 is turned on, the holding voltage of the NMOS triggering the SCR 364 is raised to a level higher than Vddl ', so that the NMOS triggering the SCR 364 does not latch up. If positive ESD appears on Vddl line 368 and Vdd2 line 37 °, the RC circuit provides a positive voltage to the gate and pole of NMOS transistor 372 and PMOS transistor 378 due to the ESD voltage of the coupling portion of capacitor 376. The crystal 372 is turned off and the PMOS transistor 378 is turned on. Because the PM0S transistor 378 of the control circuit 366 is turned off, the holding voltage of NM0s touching the SCR 364 is adjusted to a level less than vdd1, for example, about! ^ In particular, the NMOS-triggered SCR 364 is kept in a latched state. In addition, since the NMOS transistor 372 is turned on, the NMCr triggers sCr 364 to turn on quickly to discharge the ESD current, and clamps the positive-polarity ESD voltage to about 1 volt. If negative ESD occurs on Vdd2 line 370 and Vddl line 368 is grounded, due to time delay, the RC circuit provides a ground voltage to between Nlv10s 200522352 transistor 372 and PM0S transistor 378. At this time, pM0 = its source and gate equipotential potentials.

Bract crystal 372 is turned on due to its gate potential. As the 37th position of the PM0S circuit of the control circuit 366 is larger than its source core, the private daytime body 378 is turned off, the holding voltage of the NMOS touch ... 364 is adjusted to be lower than the trigger one to maintain the locked state. At the same time, CR 364 can be quickly opened to discharge electricity " L sub-negative 忮 ESD voltage clamp is located at about q volts. If the ground appears on the Vdd2 line, 37 °, the V-line 368 is two-way forward. 'Positive polarity-voltage one _, the Ezdazole ESD appears on the vdd] line 368 and the vdd2 line 370 —pole — 380 is the frequency offset. The negative polarity ESD voltage clamp is located at the threshold voltage of the diode 380. t ^ esd 11! I! 8? ", J ^ ^ pmos ^ ^ SCR 3 84 ^ ^ ^ Circuit connection: Circuit diagram of No. 3!?. See Figure ™ Guard. In a 11a, the ratio of the Ditun source line 388 to the second power supply line 390 is also an example, the first power supply line 388 and the second power supply line 390 ask for power supply lines, such as different or the same voltage level Of,

Vdd2. In another meeting, 丄 39〇 is a low voltage ^ the first power line 388 and the second power line V 2. For example, the source voltage is different or the same voltage level, the control circuit Q, the circuit 382 includes a PM0S trigger SCR 384 and a control circuit 86. PM0S triggers SCR 384, including un- PMOS thunder θ) bCR (hew) and sun-day body 392. The control circuit 386 includes a resistor state, a capacitor state 32 200522352, and an NMOS transistor 398. The voltage level of the first power line 388 is higher than the voltage level of the second power line 390, such as Vdcu > Vdd2. During normal operation, an Rc circuit composed of a resistor 394 and a capacitor 396 provides a voltage such as The gates of the PMOS transistor 392 and the NMOS transistor 398 are aligned. At this time, the LED 398 is turned on due to the inter-electrode potential, that is, greater than its source bit vdd2. On the same day temple, PM0S transistor 392 is closed because of its gate 14 source and other bits, all are Vddi. Because the transistor 8 of the control circuit is turned on, the holding voltage of PM0s triggering SCR 384 is increased to a level higher than vdd, so that PM0s triggers scr 384 without latching. If there is a positive polarity ESD on the Vdd line 388 and the Vdd2 line 39. Ground. Due to the time delay, the RC circuit outputs a ground voltage to the gate of the PMOS transistor 392 and the NMOS transistor 398. At this time, the nm os transistor 398 is at _ because its source and gate potentials are both ground potentials. In addition, the PMOS crystal 392 is turned on because its source potential is greater than its gate potential. Since the NMOS transistor 398 of the control circuit 386 is turned off, the PMOS touch smoke SCR 384's holding voltage is reduced to less than about 1 volt, and the PM0S touch ^ SCR 384 remains in the latched state. At the same time, because the pMOS transistor is turned on, the PMOS trigger SCR 384 can be turned on quickly to discharge the ESD voltage and clamp the positive polarity ESD voltage to about 1 volt. Shake off, if negative ESD appears on Vdd2 line 390 and V% line 3 is grounded, due to the ESD voltage of the coupling part of capacitor 396, a negative voltage from the Rc circuit to PMOS transistor 392 and 3% of NMOS transistor ^ 7, δ The intermediate electrode turns on the PMOS transistor 392 and the nmMOS transistor 39 turns off. 33 200522352 As the NMOS transistor 398 of the control circuit 386 is turned off, the holding voltage of the PMOS triggering SCR 384 is adjusted to a level lower than Vdd], for example, about -1 volts, which keeps the PMOS triggering SCR 3 84 in the latched state. In addition, since the PMOS transistor 392 is turned on, the PMOS trigger SCR 384 can be turned on quickly to discharge the ESD current and clamp the negative polarity ESD voltage to about -1 volts. If the positive ESD occurs on the Vdd2 line 390 and the Vddl line 388 is grounded, the diode 400 is forward biased, and the positive ESD voltage is clamped to the threshold voltage of the diode 400. If the negative polarity ESD appears on the Vddl line 388 and the Vdd2 line 390 is grounded, the diode 400 is forward biased, and the negative polarity ESD voltage is clamped to the threshold voltage of the diode 400. The present invention therefore provides a method for protecting against electrostatic discharge, including providing a silicon controlled rectifier (SCR) with a holding voltage, and controlling the holding voltage of the SCR to be higher or lower than a power supply voltage Vdd. In detail, the method of the present invention raises the holding voltage to higher than vdd during normal operation so that the SCR does not latch up, and reduces the holding voltage to below Vdd during ESD to keep the SCR in the locked state. FIG. 20A is a cross-sectional view of an SCR 500 according to an embodiment of the present invention. The structure of the SCR 500 is similar to the SCR 84 of FIG. 5 or the SCR 128 of FIG. 9, but the NMOS transistor 107 of the control circuit 86 of FIG. 5 or the NMOS transistor 188 of the control circuit 186 of FIG. 9 is embedded in the SCR 500. Integrating the MOS transistor in the original control circuit into the SCR can simplify the layout of the SCR, reduce the size of the SCR, and simplify the complexity of the control circuit. Referring to FIG. 20A, the SCR 500 includes a p-type substrate 502, an n-type 34 200522352 well region 504, a first P-type diffusion region 506 formed in the n-type well region 504, and a portion formed in the n-well region 504. A second p-type diffusion region 508 inside, a first n-type diffusion region 510 formed in another -n-well region 512, and a second n-type diffusion region 514 formed in the P-type substrate 502. The second n-type expanded region 514 is connected through a metal layer or a self-aligned metal silicide layer 5 16 * 5 Chu-I, Le-P-type diffusion region 508. The P-type transistor 520 and the n-type solar element 530 and the scr 500 are integrally formed. The p-type transistor 520 has a gate electrode 522, a sidewall spacer layer 524, and a through hole (not shown) formed in the n-well region. The first P-type diffusion region 506 and the second p-type diffusion region 508 are used as a source and an electrode of the P-type transistor 520. The n-type transistor 530 has a gate electrode 532, a sidewall spacer 534, and a p-type substrate ^ 02. Nei Tongtong (not labeled). The first n-type diffusion region 510 and the second n-type diffusion region 514 serve as the source and the drain of the n-type transistor 53. The role of the p-type electric 3 520 is to promote the opening of the ISCR 500. The n-type transistor 53 is used to control the holding voltage of the SCR 500. The materialized layer 54 is used to provide electrical insulation. The diffusion region 506 as the scr is connected to the contact pad 55. As the SCI level (two ㈣ ST-type diffusion regions 510 are connected to a reference potential or ㈣ is connected to a-power line, in the example, the difference between the "P-P" type diffusion is: resistance = on: way 6. °. Control circuit _ and Capacitance-Chengzhi's resistance-capacitance circuit-Delay, "pulse balance of 15. to 3 ...., 20052352 is long. The control circuit 600 is connected between the first power line such as vdd and the second power line such as Vss The output terminal 606 is connected to the gate electrodes 522 and 532 shown in Fig. 20a. The ESD protection provided by the SCR 500 and the control circuit 600 and the ESD compliance circuit 82 of Fig. 5 or the ESI3 protection circuit of Fig. 9 $ 4 is similar. Please refer to FIGS. 20A and 20B. During normal operation, the closed electrodes 522, 532 are biased to the high voltage level Vdd, so that the p-type transistor 52 is turned off and the n-type transistor 530 is turned on. The transistor 530 is turned on and the main resistance is smaller than that of the SCR 500. The holding voltage of the scr 500 is increased above Vdd, so that the SCR 500 does not detect the lock. During the ESD period, the gates 522, 532 Biased to low voltage level Vss due to the time delay provided by the resistor-capacitor circuit, making the p-type The crystal 52 is turned on and the n-type transistor 530 is turned off. The control circuit 600 exhibits a larger resistance than the sCR 500's base due to the shutdown of the type transistor 530. The holding voltage of the SCR 500 is reduced to In this way, the hidden lock is kept to keep the lock-shaped evil to discharge the ESD current. Fig. 21 is an ESD protection circuit 62 of another embodiment of the present invention. The ESD anti-recovery circuit 620 has one SCR 500 and one pM0s. The crystal 52, an NMOS transistor 530, and a control circuit 600. The control circuit 600 is connected between the first power line Vdd and the second power line Vss. The scr 500 is connected to the contact pad 550 and the first Between the two power supply lines Vss. The pM0s transistor 520 and the NMOS transistor 53o are integrated with the scr 5000. During the positive system operation, the control circuit 600 provides a first voltage level Vdd to PMOS Transistor 520 and Ress transistor 53 are used to provide a 36 200522352 first holding voltage higher than Vdd to SCR 500, so that SCR 500 does not latch up. During ESD, for example, positive ESD pulses appear in The contact pad 550 and the second power line Vss are grounded, and the control circuit 6 〇Provide a second voltage level Vss to PMOS transistor 520 and NMOS transistor 530, so as to provide a second holding voltage lower than Vdd to SCR 500 to keep SCR 500 in a latched state. The gasket 550 is discharged to the first power line V ss.

FIG. 22 is an ESD protection circuit 64o according to another embodiment of the present invention. The structure of the esd protection circuit 640 is similar to the ESD protection circuit 620, but the SCR 500 is connected between the first power line Vdd and the second power line \ ^ ss. During the ESD period, for example, a positive polarity ESD pulse appears on the first power line Vdd and the second power line vss is grounded, the control circuit 600 provides a second voltage level Vss to the PMOS transistor 520 and the NMOS transistor 530, thereby providing a The second holding voltage lower than Vdd reaches the SCR 500, so that the SCR 500 is kept in a latched state. The ESD pulse is discharged from the first power line Vdd to the second power line Vss. FIG. 23 is an ESD protection circuit 660 according to another embodiment of the present invention. The ESD protection circuit 660 has a plurality of SCRs 50, 500, 500, and 500_p, and a control circuit 600. As an example, the SCR 500 has a PMS Transistor 520_n and an NMOS transistor 530-n are integrated with SCR 500-n. The control circuit 600 has an output terminal 606 connected to the PM0s and NMOS transistors of these SCRs. Gate (not labeled) SCR 500 p is connected to the first power line vdd and the second power line 200522352

Vss between. Each SCR 5004, 500-2 ... 500-n is connected to a corresponding contact pad 550-1, 550-2 ... 550-n and a second power line

Vss between. During normal operation, the control circuit 600 provides a first holding voltage to the SCRs 500-1, 500-2, 500-n, and 500-p via these PMOS and NMOS transistors, so that these SCRs do not latch up. If a positive polarity ESD pulse appears in a contact pad, such as contact pad 550-1, and the first power line Vdd is grounded, the control circuit 600 provides a second holding voltage to the PMOS and NMOS transistors through these SCR 500-1, 500-2 ... 500-n and 500-p keep these SCRs in a latched state. The ESD pulse is discharged from the contact pad 550-1 through the second power line Vss to the first power line Vdd, which is the first path P1. If a positive-polarity ESD pulse appears on the first power line Vdd and a contact pad is grounded, such as contact pad 550-1, the control circuit 600 provides a second holding voltage to the SCR via these PMOS and NMOS transistors 50 (M, 500-2 ... 500-n and 500-p, keeping these SCRs in a latched state. ESD pulses are discharged from the first power line Vdd through the second power line Vss to the contact pad 550-1, This is the second path P2. If a positive-polarity ESD pulse appears on a contact pad, such as contact pad 550-2, and another contact pad is grounded, such as contact pad 550-n, control circuit 600 These PMOS and NMOS transistors provide a second holding voltage to SCR 500-1, 500-2… 500-n and 500-p to keep these SCRs in a latched state. ESD pulses are provided by contact pads 550-2 is discharged to the contact pad 550-n via the second power line Vss, which is the third path 38 200522352 The present invention also provides a method for protecting against electrostatic discharge (ESD). A silicon controlled rectifier with a holding voltage is provided. (SCR). A PMMOS transistor and an NMOS transistor are integrated with the SCR. PMOS transistor There is a first gate, and the NMOS transistor has a second gate. During the first condition, a first signal is provided to the first and second gates to increase the SCR holding voltage so that the SCR does not latch up. During the second condition, a first k number is provided to the first and second gates to reduce the SCR holding voltage and keep the SCR in a latched state.

In another embodiment of the present invention, the ESD protection method includes providing a first power line having a first voltage level and a second power line having a second voltage level. The second voltage level is different from the first voltage level. Voltage level. Provide multiple contact pads. Provide multiple silicon controlled rectifiers (SCRs). Each SCR has a PMOS transistor and a NMOS transistor, all of which are integrated with the SCR. At least one of the SCRs is connected between the first and second power lines, and the remaining SCr is connected between a corresponding contact pad and the second power line. During normal operation, a first holding voltage is provided to these cells via these PMOS and NMOS transistors, so that these SCRs cannot be locked. During the coffee, it is provided through these pMOS and NMOS transistors-the second holding voltage to these scr, to keep these in a locked state. In the-embodiment, the ESD pulse is discharged from one of the contact pads to the -th power supply line via the second power supply line. In another embodiment, the pulse is discharged from the first power supply line to one of the contact pads via the second power supply line. 39 200522352 One via a second power supply In yet another embodiment, the ESD pulse is discharged from the contact pad circuit to the other contact pad. People in this bank know clearly that the same modifications or changes can be achieved within the spirit of the present invention. Persons in the bank can clearly understand other embodiments of the present invention by reading this book and implementing Mao S #. This note: and the examples in it are just examples. The scope and spirit of the present invention are defined by the following patent application scope. [Brief description of the drawings] FIG. 1 is a circuit diagram of a conventional ESD protection element; FIG. 2 is a sectional view of another conventional ESD protection element; FIG. 3 is a circuit diagram of an SCR and a control circuit according to an embodiment of the present invention; J_v curve of the circuit shown; Figure 5 is a sectional view of the layout of the ESD protection circuit; Figure 6 is a sectional view of the layout of another ESD protection circuit; ^ · Figure 7 is a circuit of the SCR and control circuit according to another embodiment of the present invention. The layout of the ESD protection circuit according to the embodiment of the present invention; FIG. 9 is the layout of another ESD protection circuit; FIG. 10 is the ESD protection circuit according to the embodiment of the present invention; FIG. 11 is another ESD protection circuit according to the embodiment of the present invention; This is an input esd protection circuit in the embodiment of the present invention; Figure 13 is another input ESD protection circuit in the embodiment of the present invention 200522352; Figure 14 is an output ESD protection circuit in the embodiment of the present invention; Figure 15 is an embodiment of the present invention; The other output end ESD protection circuit; Figure 16 is an input and output ESD protection circuit of a mixed voltage power supply according to an embodiment of the present invention; Figure 17 is a schematic diagram of an ESD protection circuit of a mixed voltage power supply according to an embodiment of the present invention; and Figure 18 is an embodiment of the present invention ESD protection circuit of mixed voltage power supply using NMOS to trigger SCR; FIG. 19 is an ESD protection circuit of mixed voltage power supply using PMOS to trigger SCR according to an embodiment of the present invention; FIG. 20A is a cross-sectional view of SCR according to an embodiment of the present invention; 21 is an ESD protection circuit according to another embodiment of the present invention; FIG. 22 is an ESD protection circuit according to another embodiment of the present invention; and FIG. 23 is an ESD protection circuit according to another embodiment of the present invention. Description of component symbols 60: silicon controlled rectifier (SCR) 62: parasitic pnp bipolar transistor 64: parasitic npn bipolar transistor 66: N-well resistance 68: substrate resistance 70: parasitic resistance 72: parasitic resistance 200522352 74: control circuit 78: cathode 84: silicon controlled rectifier (SCR) 88: p-type substrate 92: first P-type diffusion region 96: first P-type diffusion region 100: gate 104: second n-type region 107: NMOS Transistor 110: Resistor 114: Electrostatic discharge protection circuit 118: PMOS transistor 122: Capacitor 128: Silicon controlled rectifier (SCR) U2: Parasitic ρηρ bipolar transistor 134: Parasitic ηρη bipolar transistor 136: [ Well area resistance 140: parasitic resistance 14 6: anode 150: electrostatic discharge protection circuit 154: η well area 158: first η-type diffusion area 162: η well area anode electrostatic discharge protection circuit control circuit η well area second P-type diffusion Area η well area Thick oxide layer Third P-type area Contact pad Xin Capacitor control circuit Resistance inverter control circuit: substrate resistance: parasitic resistance: cathode: p-type substrate: first p-type diffusion region: second n-type diffusion Zone: Gate 42 200522352 168: Third n-type 172: No. Type 176: Inverter 180: Resistor 184: ESD protection circuit 188: NMOS transistor 192: Capacitor 196: Silicon controlled rectifier (SCR) 200: PMOS transistor 204: Resistor 208: ESD protection circuit 212: Control circuit 216: PMOS transistor 220: resistor 224: electrostatic discharge protection circuit 228: control circuit 232: second control circuit 236: resistor 240: NMOS transistor 248: PMOS transistor 252: ESD protection circuit 256: control circuit 260: control circuit : Contact pad: PMOS transistor: Diode: Capacitor: Control circuit: Resistance: ESD protection circuit: Control circuit: NMOS transistor ^: Capacitance: Silicon controlled rectifier (SCR): NMOS transistor: Inverter: Capacitor: Silicon Controlled Rectifier (SCR): Silicon Controlled Rectifier (SCR) ·:: PMOS Transistor: Capacitor: NMOS Transistor: Contact Pad: Silicon Controlled Rectifier (SCR): Silicon Controlled Rectifier (SCR): PMOS Transistor 43 200522352 264: resistor 268: NMOS transistor 272: resistor 276: PMOS transistor 280: electrostatic discharge protection circuit 284: first control circuit 288: second control circuit 292: resistor 296: NMOS transistor 300: resistor 304: PMOS transistor 308 : Second buffer 3 12: ESD protection circuit 316: Silicon controlled rectifier (SCR) 320: Resistance 324: NMOS transistor 328: Inverter 332: First buffer 336: Contact pad 340 · Silicon controlled rectifier (SCR) 344: Resistance 348: NMOS transistor 352: Contact pad inverter NMOS transistor inverter Contact pad Silicon controlled rectifier (SCR) Silicon controlled rectifier (SCR) PMOS transistor capacitor i NMOS transistor capacitor A buffer contact pad Silicon controlled rectifier (SCR) PMOS transistor capacitor NMOS transistor _ PMOS transistor second buffer electrostatic discharge protection circuit PMOS transistor capacitor diode string: diode 44 • 200522352 356: 360: 364: 368: 372: 376: 380: 384: 388: 392: 396: 400: 500-1 500-p 502: 506: 510: 514: 516: 520: 522: 530: 532: PMOS transistor 358: static electricity Discharge protection circuit ESD protection circuit 362: ESD protection circuit Silicon controlled rectifier (SCR) 366: Control circuit first power line 370: second power line NMOS transistor 374: resistance capacitor 378: PMOS power Body diode 382: ESD protection circuit silicon controlled rectifier (SCR) 3 86: Control circuit first power line 390: second power line PM0S transistor 394: resistance capacitor 398: NMOS transistor diode 500 ... silicon Controlled rectifier (SCR): Silicon controlled rectifier (SCR) 500-2: Silicon controlled rectifier (SCR): Silicon controlled rectifier (SCR) 500-n: Silicon controlled rectifier (SCR) p-type substrate 504: η-type well area first p-type diffusion region 508 ·· second ρ-type diffusion region first η-type diffusion region 5 12 ·· η-type well region second η-type diffusion region automatically aligns with metal salicide layer PM0S transistor 520-n : PMOS transistor gate 524: sidewall spacer NM0S transistor 530-n: NMOS transistor gate 534: sidewall spacer

45 200522352 540: 550-1 550-n 602: 606: 640: Thick oxide layer: contact pad: contact pad resistance output terminal electrostatic discharge protection circuit 550: contact pad 550-2: contact pad 600: control circuit 604: capacitor 620: electrostatic discharge protection circuit 660: electrostatic discharge protection circuit

46

Claims (1)

200522352 Scope of patent application: 1. An integrated circuit for electrostatic discharge protection, including: a silicon controlled rectifier (SCR); and a control circuit connected to the SCR, so as to prevent the SCR from latching up, and The first grip ^ ㈣SCR remains in a latched state, where the first-grip voltage is different from the first master 2. If the scope of the patent application is the first! The circuit of the item, wherein the scr contains -cone and-connected to the base and the emitter of the carrier crystal, and the electron crystal circuit presents the circuit during the first condition and presents the circuit during the second condition. For example, the circuit of the second scope of the patent application, wherein the resistance is smaller than the resistance value of the parasitic resistance. 4. The circuit of item 3 in the scope of patent application, wherein the resistance is greater than the resistance value of the parasitic resistance. 5. The circuit of item i in the scope of patent application, wherein the SCR comprises a p-type substrate, an n-well region formed in the P-type substrate, a p-type diffusion region formed in the n-well region, and an n-well. N-type diffusion region outside the region. 6. The circuit of item 1 in the scope of patent application, wherein the control circuit includes a metal-oxide-semiconductor (MOS) transistor connected to the SCR, and a resistor-capacitor circuit that provides delay. 200522352 7. According to the lifecycle of claim 4 in the scope of patent application, it has a drain connected to ^ ', wherein the control circuit includes a NMOS transistor and a diffusion region formed in the 11-well region. 8. The circuit according to item 4 of the scope of patent application, which has a source connected to a portion, wherein the control circuit includes a diffusion region formed by the PMOS in the n-well region. Transistor 9 · If you apply for a patent, the circuit of the item, in which the-terminal is connected to the _s transistor, and Yiguang: Xi J "resistance to the resistor and the NMOS transistor _.% Fen 'heart One end of the valley is connected to the 10th, such as the thunder ^ ~% of the scope of the patent application, where the control circuit includes an inverter, a resistor, and a capacitor, and the output of the inverter is connected to pM. 〇S transistor gate, 忒 one end of the resistor is connected to one of the inverter ^^ cake, and the electric valley-end is connected to # ρΗ and the inverter read terminal. = If you apply for a patent, The circuit of this item further includes a transistor for triggering. The PMOS transistor has a p-type diffusion region whose source is connected to the SCR, a p-type substrate connected to the SCR, and the substrate is connected to the WELL region of the SCR. ° With the circuit as described in the fourth item of the patent application, it also includes an NMOS transistor to trigger the SCR. The NMOS transistor has a η split diffusion region with a source connected to the SCR, and a η connected to the SCR. Well area, and a p-type substrate with basal body connected to SCR. And 13 · —product of electrostatic discharge protection The circuit includes: 200522352 a MOS-triggered SCR including a silicon controlled rectifier (SCR) and a metal-oxide-semiconductor (MOS) transistor connected to the SCR to trigger the SCR; and a control circuit, which is connected The SCR triggered by M0s will raise the first holding voltage during the first condition to the SCR triggered by M0S so that the SCR triggered by M0S will not latch up and provide a second holding voltage to the display during the first condition s The triggering SCR is kept in the latched state, where the first-holding voltage does not hold the voltage. a 14 Clear profit range Item 13 The MOS triggers the SCR, which moves the u circuit, of which the trigger of the MOS is the first -A, which includes a pM0 integrated circuit, and further includes-the B body and ucR 'and its ㈣ second SCR. 4 SCR, which includes a -NMOS transistor and-the control circuit is the first control circuit, -The middle connects to the second control circuit of the -M0S touch trigger SCR. The X read circuit also includes -the connection to the 16th, such as the device in the scope of patent application No. 14, one end of which is connected to a connector, of which the first control The circuit includes a capacitive contact pad to turn on part of the contact pad. ^ 17 · The device of item ls of the scope of patent application 'its-terminal is connected to the-contact pad ^ where the second control circuit contains a part of the ESD voltage of the contact pad. 18 · as the scope of patent application No. 15 Item 3, wherein the first control circuit includes a -NM0 200522352 transistor and an -inverter, which is connected to the pole between the NM0S transistor and the gate of the PMOS transistor whose PMOS triggers the SCR. = For details, please apply In the circuit of the item, the second control circuit includes a picture == and -rib H, the inverse H is connected to the pole of the PM0S voltage and the gate of the NMOS transistor that triggers the SCR. 2〇 ·· Integrated circuit for electrostatic discharge protection, including ··· Shi Xi controlled rectifier H (SCR), which has-the first doped substrate, and the third doped semiconductor The financial region, the first diffusion region of the doping type and the second doping type, and the second diffusion m 形成 formed in the semiconducting horse si, are the second doping type-control circuit in addition to the impurity. Connected to the SCR to provide a first grip and two electric houses to the SCR during the first condition to prevent the SCR from latching, and to provide a second first condition to the chat_lock condition in the second condition, where the first-hold Voltage is different from 21 · — A method of protecting against electrostatic discharge, including: · providing a stone-controlled rectifier (SCR) with a first-holding voltage; and controlling the holding voltage of the SCR to be higher than that during the first-condition = No latching 'and controlling the holding voltage of the SCR during the second state, such as 2222. For example, the type of metal oxide semiconductor (PM0S) transistor of the 21st patent application scope 200522352 23 · The method of claim 2i of patent application scope further includes providing an n-type metal-oxide-semiconductor (NMOS) transistor connected to WR for The SCR is triggered during the second condition. 24. The method of claim 21, further comprising connecting the SCR between a first power line and a second power line. • The method as described in item 24 of U. I. 1§, further comprising using the first power line as a Vdd line 'and the second power line as a vss line. 26 · — A kind of integrated circuit for electrostatic discharge protection, including a silicon controlled rectifier (SCR); a first transistor of the first conductivity type, which is formed with the SCR integrated body and has a first-second conductivity type The second transistor is formed with the SCR integrated body, a gate; and the tooth m circuit, in response to the voltage applied to the first and the second gate, the second 4 = voltage to the SCR so that the SCR does not cause Latched, and should be applied to the first hold in the locked state. ^ Live the electric fort to the SCR to ensure the SCR protection circuit. The control circuit also includes the output terminal connection. 27. For example, the 26th to the first and second gates of the patent application scope. 200522352 28. For example, the circuit resistance of item 26 of the patent system, an extended capacitance of an electric resistance and a capacitor, and a wheel output terminal between the resistor and the capacitor ^ $ Road also includes-29. If you apply for an exclusive round of 26th Circuit. The H1 material includes a 30. As described in the patent application No. 1 circuit, the parent is formed in the n-well region in the P-type substrate,-formed in the read ^-P-type substrate,-n-type diffusion formed outside the η-well region Area. The P-type diffusion region and the shape 31. The channel region in the circuit well region of the patent application No. 30. The crystal additionally includes-a channel region formed in a circuit well region as described in item 30 of the patent application. The first tortoise crystal also includes a integrated circuit formed at ρ 33. — a type of electrostatic discharge protection, including ... a silicon controlled rectifier (SCR); a p-type transistor formed with the SCR integrated product; Body-shaped n-type transistor; a control circuit connected to the p-type and n-type transistor, which provides a first-electron dust to the SCR so that the SCR does not latch up, and a new-second Wei to fa to keep the scr In the locked state. Zuuyzzjyz 34. If the circuit in the scope of patent application item 33, the second capacitor and a wheel between the resistor and the capacitor = the control circuit also includes an electrical limit. 35. If the circuit in the scope of patent application item 33, The control circuit is connected to the gate of the P-type transistor and the gate of the η-type transistor. C $ Outlet connection 36. Ru Shen fiber, 3 slave Wei, the R material contains -ρmer, formed in the P-type substrate In the η well area, one forms the P soil body in the h well area, and one forms the n-type diffusion area outside the η well area. The P-generation expansion area and the one-shaped well area diffusion area 37. For example, the scope of application for patent 36th The circuit of the term 'The SCR also includes a part formed in the other-a P-type diffusion region as a p-type electric The drain of the crystal, and one of them is the source of the P-type transistor. '38. If the circuit of the patent application No. 36' The solitary also includes formed in the ρ-type substrate = Xina, State 0 Lai San District 39. If the circuit in the scope of patent application item 33 is applied, the SCR is connected to-contact the diaphragm and a power supply line. ~ 40. If the circuit in the scope of patent application item 33 is applied, the SCR is connected to the phase $ power supply. Between lines 0 200522352 41. An integrated circuit for electrostatic discharge (ESD) protection, comprising:-a first-power line having a -th voltage level;-a second power line having a second voltage level-multiple Contact pads; multi-control rectifier IIW), each SCR includes _ η-type transistors' • and n-type transistors and SCR integrated molding; Γ-a control circuit, via p-type and n-type Transistors provide SCRs so that these SCRs do not lock up f 1 to _,,, and 2. P-type and n-type transistors provide a first-holding secret to the edge SCR to make these SCRs contact or contact. ESD period of pad _ turn _ 嶋. During the reading period 42 · If the patent application scope of item 41 is in the first-to-SCR, it also includes at least one connected contact pad material: == R '钱 复 嶋 于 一 _ 43 · If the patent application scope is 42 The circuit of this item is discharged from the contact pad to the first power supply line during the ESD period. 44. Rushen Eye patent band from the first-the power line is gradually relieved from the first 4: During the period, the original line is discharged to one of these contact pads. 45. As described in item 42 of the scope of the patent application, the connection of _ ^ __ by the __ during the ESD period, ESD ^, one of the industrial power supply line is discharged to another contact pad. 200522352 46. A circuit as claimed in item 41 of the patent application. The control circuit further includes a resistor-capacitor resistor 47. The circuit of item 41 in the scope of patent application, the control circuit is between each p-type and n-type transistor. υ output terminal is connected with 48 · — a method of electrostatic discharge protection, including ... providing a hybrid rectifier H (SCR) with age. Electricity has-electricity, two electricity, SCR, and two transistor voltages to increase the SCR, the first to the second and the second poles to improve the SCR holding the SCR without latching; and to raise {, the first L The first and second gates are used to reduce the holding voltage of the SCR so as to maintain the latched state. Hold-to make the method as described in Item 48, including raising the holding voltage of the SCR above a power supply voltage. For example, the method in the 48th scope of the patent application further includes reducing the holding voltage of the SCR to below the turtle source voltage. 51. If the method of applying for item 48 of the scope of patent application, further includes connecting the SCR between a contact pad 200522352 and a power line 52. If the method of applying for area 48 of the patent application. The method also includes connecting the SCR to a different power source. 53. Fishing ΓΓ has a method to protect against electrostatic discharge), including: & for one with a younger-lighter first-power line; one with a first The second power line with two voltage levels; Provides multiple contact pads; Provides multiple control rectifiers, A /-n-type heart p 4 female-Ge Qing all include-a 卩 -type transistor and ㈣-type ㈣ The P-type and η-type transistors are integrated with the SCR. Provided through the p-type and η-type transistors—the first protection, the SCR does not cause latchup; μ holds the voltage to the SCRs to make the t Γ crystals Mention H Yu face Wei et al chat to keep these in a locked state / see the ESD period of the younger-power cord contacts the entire piece-54. If the method of the scope of the patent application No. 53, also connected to the -Shoot 4 to SCR with the second electric test shoe, a SCR difficult piece and the second electric circuit / connect the rest of the SCR to—corresponding to— put it to the method '. In addition, include the ESD pulse by contacting the whole piece. The read line is discharged to the first-power line. • 20Ό522352%; 56. The method according to item 54 of the patent application scope, further comprising discharging the eSd pulse from the first to the second via the second power line to one of the contact pads. 57. ===== Foot Secret Follow