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TW200522318A - Leadless package - Google Patents

Leadless package Download PDF

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Publication number
TW200522318A
TW200522318A TW092137721A TW92137721A TW200522318A TW 200522318 A TW200522318 A TW 200522318A TW 092137721 A TW092137721 A TW 092137721A TW 92137721 A TW92137721 A TW 92137721A TW 200522318 A TW200522318 A TW 200522318A
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TW
Taiwan
Prior art keywords
post
scope
patent application
die
pin
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Application number
TW092137721A
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Chinese (zh)
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TWI229437B (en
Inventor
Chao-Ming Tseng
Original Assignee
Advanced Semiconductor Eng
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Priority to TW092137721A priority Critical patent/TWI229437B/en
Application granted granted Critical
Publication of TWI229437B publication Critical patent/TWI229437B/en
Publication of TW200522318A publication Critical patent/TW200522318A/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/32257—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the layer connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/183—Connection portion, e.g. seal
    • H01L2924/18301—Connection portion, e.g. seal being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

A leadless package mainly comprises a lead frame, a die, a silver paste and a plurality of electrically conductive wires. The lead frame includes a die paddle and a plurality of leads around the die paddle wherein the die paddle has a die disposal surface and at least one grounding stud protruded from the die disposal surface and disposed at the periphery of the die disposal surface. The die has a back surface and an active surface. The die is disposed on the die disposal surface so that the back surface of the die faces the die paddle and attached onto the die disposal surface via the silver paste. Moreover, the die is electrically connected to the leads. The grounding stud is at the periphery of the die disposal surface and protruded from the die disposal surface so as to prevent the silver paste from overflowing on the top of the grounding stud. Thus, the connecting area between the encapsulation and the lead frame will be increased so as to enhance the connection capability between the encapsulation and the lead frame.

Description

200522318 五、發明說明（1) (一）、【發明所屬之技術領域】 本發明係有關於一種無外引腳4 於-種可提昇晶片與導線架間電性2 f、、，。構丄特別是有關 與導線架間接合可靠度之無外引腳封=:罪度及封膠材 (二）、【先前技術】 近年來，由於行動電話、個人齡Am digital assistance，PDA)、及數 ^H(PerS〇nal 及數位相機等消費性電子產 : 口口之需未與曰倶增，因此封裝構造的型態係朝向於重量 輕、尺寸小，及訊號傳輸路徑短等方向來發展。 其中’由Matsushlta公司所開發之無夕;引腳封 (即四方扁平無引腳封裝結構（Quad Flat N〇lead pack QFN))，係為以導線架為構裝基材之晶片尺寸構裝（“Μ : frame based CSP)。由於無引腳型（leadless)的晶片尺 構裝具有訊號傳遞路徑（trace)短，降低訊號衰減的優點， 一直是低腳位（low pin count)半導體元件常用的構裝結 構0 〇 請參照圖1，其顯示習知無外引腳封裝結構的剖面示咅 圖。該無外引腳封裝結構的導線架11〇(如銅導線架）係由= 片座112(die pad)及其周緣多個引腳114(Uad)所組成。$ 中，晶片座112係包含晶片接合區J 12a及接地區1125，且^ 片120以其背面122藉由銀膠130(3][]^“1^31：6)與晶片座曰曰 112之晶片接合區ii2a貼合。晶片12〇之主動表面124 (active surface)上的銲墊i26(bonding pad)則透過導電 200522318 五、發明說明（2) 線140(如金線；gold wire)，分別與引腳114的頂面n4a連 接及晶片座112之接地區112b ’形成電性導通。而封膠材料 150(molding compound)包覆晶片120、導電線140、晶片座 1 1 2的晶片接合區1 1 2a及接地區11 2b及引腳11 4的頂面 114a，而暴露出晶片座112的底面112c及引腳114的底面 114b。透過引腳114的底面114b與外部的印刷電路板（未顯 示）連接。 承上所述，為使晶片1 2 0能與晶片座11 2緊密接合，常 需塗佈適量之銀膠1 3 0以作為連接之用；惟當晶片1 2 〇之尺^ 與晶片座112之尺寸相近’且晶片120週邊128距離導電線、 140與晶片座112之接地區112b小於6密爾（mils)時（即 mi Is)，過量之銀膠將溢入接地區1 12b，使得導電線無法與 晶片座11 2之接地區11 2b緊密地接合。也因此使得無外弓丨^ 封裝結構之產品可靠度降低。 有鑑於此，為避免前述無外引腳封裝結構之缺點，以 提升無外引腳封裝結構之封膠材與導線架間接合可靠度， 實為一重要的課題。 (三）、【發明内容】 有鍛於上述澤通’本發明之目的係提供一種無外引卿 封裝結構，用以提昇提昇晶片與導線架間電性接合之可a 度及封膠材與導線架間接合可靠度之無外引腳封裝結構# 緣是，為了達成上述目的，本發明係提供一種無外 腳封裝結構，主要包含一導線架、一晶片、一黏著層（液熊200522318 V. Description of the invention (1) (1), [Technical field to which the invention belongs] The present invention relates to a non-outer pin 4 which can improve the electrical conductivity between the chip and the lead frame. The structure is especially related to the reliability of joints with the lead frame. Outer pin seal =: crime and sealing material (2), [prior art] In recent years, due to mobile phones, personal age Am digital assistance (PDA), And consumer electronics such as PerS〇nal and digital cameras: the demand for the mouth has not increased, so the type of package structure is oriented toward light weight, small size, and short signal transmission paths. Development. Among them, 'Wu Xi developed by Matsshlta; lead package (Quad Flat No-lead pack QFN) is a chip size structure with lead frame as the substrate. ("M: frame based CSP). Because leadless chip scales have the advantages of short signal traces and reduced signal attenuation, they have always been low pin count semiconductor devices. Commonly used mounting structure 0 〇 Please refer to FIG. 1, which shows a cross-sectional view of a conventional non-lead package structure. The lead frame 11 (such as a copper lead frame) of the non-lead package structure is composed of = pieces Block 112 (die pad) and its multiple pins 114 (Uad ). In the $, the wafer holder 112 includes the wafer bonding area J 12a and the connection area 1125, and ^ the plate 120 with its back 122 and the silver glue 130 (3] [] ^ "1 ^ 31: 6) and the wafer The bonding area ii2a of the wafer 112 is bonded. The bonding pad i26 (bonding pad) on the active surface 124 of the wafer 120 is electrically conductive. 200522318 V. Description of the invention (2) Line 140 (such as gold wire; gold wire), which are respectively connected to the top surface n4a of the pin 114 and the connection area 112b 'of the wafer holder 112 to form electrical conduction. A molding compound 150 (molding compound) covers the wafer 120, the conductive wire 140, and the wafer holder 1 1 2 of the wafer bonding area 1 1 2a and the contact area 11 2b and the top surface 114a of the lead 114, and the bottom surface 112c of the wafer holder 112 and the bottom surface 114b of the lead 114 are exposed. The bottom surface 114b of the lead 114 and the external Printed circuit board (not shown) connection. According to the above, in order to make the wafer 120 can be tightly connected with the wafer holder 112, it is often necessary to apply an appropriate amount of silver glue 130 for connection; The size of 〇 ^ is close to the size of the wafer holder 112 'and the periphery of the wafer 120 is 128 away from the conductive line, and the area between the 140 and the wafer holder 112 is 11 When 2b is less than 6 mils (that is, mi Is), excess silver glue will overflow into the contact area 1 12b, so that the conductive wire cannot be tightly bonded to the contact area 11 2b of the chip holder 11 2. As a result, the reliability of products without an outer bow package structure is reduced. In view of this, in order to avoid the disadvantages of the above-mentioned outer-lead packaging structure, it is an important issue to improve the reliability of the bonding between the sealing material and the lead frame of the outer-lead packaging structure. (3) [Content of the invention] The purpose of the present invention is to provide a no-lead package structure for improving the degree of electrical connection between the chip and the lead frame and the sealing material and The outer-lead-free package structure for the reliability of the bonding between lead frames # The reason is that in order to achieve the above-mentioned purpose, the present invention provides a non-outer package structure, which mainly includes a lead frame, a chip, and an adhesive layer (liquid bear

200522318200522318

黏著膠或 及其周緣 於黏晶面 上。而晶 晶片座設 動面係藉 综上 之週邊上 晶片座之 柱接地導 座之接地 時，由於 架之接合 銀膠）及複數條導電線 多個引腳所組成，且晶 之接地柱，且該接地柱 片具有一背面及一主動 置於黏晶面上並藉由黏 複數條導電線分別與引 所述，由於晶片座之接 ’故銀膠塗佈於晶片之 接地柱頂面（接地區域） 通時，不會因銀膠之作 柱頂面之接合可靠度。 接地柱係突出於黏晶面 面積，以提昇封膠材與 。其中’導線架係由晶片座 片座具有黏晶面及一突出 係設置於黏晶面之週邊 面’且晶片係以背面面向 著層與晶片座接合，而主 腳電性接合。Adhesive or its periphery is on the crystal surface. The moving surface of the wafer base is based on the grounding of the pillar grounding base of the wafer base on the periphery, due to the bonding of the frame to the silver glue) and a plurality of conductive wires and multiple pins. And the ground pillar has a back surface and an actively placed on the surface of the sticky crystal, and is respectively connected with the lead through a plurality of conductive wires. Because of the connection of the chip holder, the silver glue is coated on the top surface of the ground pillar ( (Grounding area) When connected, it will not be connected to the top surface of the column due to the silver glue. The grounding column system protrudes from the area of the crystal surface to enhance the sealing material and. The 'lead frame is formed by a wafer holder. The wafer holder has a die-bonding surface and a protrusion is provided on the peripheral surface of the die-bond surface', and the wafer is bonded to the wafer holder with the back surface facing layer, and the main pins are electrically connected.

地4柱係突出設置於黏晶面 黏晶面時，銀膠不致溢入 ’故晶片藉導電線與晶片 用’而影響導電線與晶片 再者’當封膠材包覆晶片 ’故可增加封膠材與導線 導線架之接合能力。 (四）、【實施方式】 以下將參照相關圖式，說明依本發明較佳實施例之益 外弓丨腳封裝結構。 ”、、 鈐圖2A係顯示本發明之第一較佳實施例之無外引腳封裝 ^構。本發明之無外引腳封裝結構至少包含導線架21〇、晶 ^22〇、黏著層230 (液態黏著膠或銀膠）及複數條導電線 其中，請參考圖2B，其係繪示本實施例之無外引腳封 ^結構中之導線架2 1 〇之上視圖，導線架21 0 (如銅導線架） 係由晶片座2 1 2及其周緣多個引腳2 1 4所組成，且晶片座2 1 2 /、有一黏晶面2 1 2 a及一接地柱2 1 2 b設置於黏晶面2 1 2 a之週When the ground 4 pillar system is protrudingly set on the sticky crystal surface, the silver glue will not overflow 'so the chip uses conductive wires and wafers' to affect the conductive wires and the wafers, and 'when the sealing material covers the wafer', it can increase The bonding ability of the sealing material and the lead frame. (IV) [Embodiment] The following will describe the benefits of the outer bow package structure according to the preferred embodiment of the present invention with reference to the related drawings. ", Fig. 2A shows the outer leadless package structure of the first preferred embodiment of the present invention. The outer leadless package structure of the present invention includes at least a lead frame 21o, a crystal 22o, and an adhesive layer 230. (Liquid adhesive or silver glue) and a plurality of conductive wires, please refer to FIG. 2B, which is a top view of the lead frame 2 1 〇 in the non-outer pin seal structure of this embodiment, the lead frame 2 0 (Such as a copper lead frame) is composed of a wafer holder 2 1 2 and a plurality of pins 2 1 4 on its periphery, and the wafer holder 2 1 2 /, a sticky crystal surface 2 1 2 a, and a ground post 2 1 2 b Set on the periphery of the sticky crystal surface 2 1 2 a

200522318 五、發明說明（4) · 邊上。而晶片220具有一背面222及一主動面224，且晶片 ‘ 2 2 0係以背面2 2 2面向晶片座2 1 2設置於黏晶面2 1 2 a上中，藉 由黏著層230與晶片座210接合，而主動面224係藉複數條導 電線240分別與引腳214電性接合及接地柱21 2b接地導通。 此外’該引腳2 1 4係具有一頂面2 1 4 a且該引腳頂面2 1 4 a可與 该黏晶面212a共平面。 再者’本發明之無外引腳封裝結構更可包含封膠材料 250 (molding compound)，以包覆晶片 220、導電線240、晶 、 片座212的黏晶面2 12a及接地柱21 2b與引腳214的頂面200522318 V. Description of Invention (4) · On the side. The wafer 220 has a back surface 222 and an active surface 224, and the wafer '2 2 0 is arranged on the die-bonding surface 2 1 2 a with the back surface 2 2 2 facing the wafer holder 2 1 2, and the adhesive layer 230 and the wafer The base 210 is bonded, and the active surface 224 is electrically connected to the pin 214 through a plurality of conductive wires 240 and the grounding post 21 2b is grounded. In addition, the pin 2 1 4 has a top surface 2 1 4 a and the pin top surface 2 1 4 a may be coplanar with the die-bonding surface 212a. Furthermore, the outer-lead-free packaging structure of the present invention may further include a sealing compound 250 (molding compound) to cover the wafer 220, the conductive wire 240, the crystal, the die-bonding surface 2 12a of the chip holder 212, and the ground post 21 2b. Top surface with pin 214

214a ’而暴露出晶片座212的底面212c及引腳214的底面 讀I 214b，以使封裝結構可透過引腳21 4的底面21 4b及晶片座 2 1 2的底面2 1 2 c與外部的印刷電路板（未顯示）連接。值得注 意的是’封膠材料亦可部分包覆引腳而暴露出部分之引腳 頂面。 承上所述’利用蝕刻方式形成接地柱2丨2b及黏晶面 2 1 2a時，係藉由蝕刻阻罩之設計及控制蝕刻時間，使接地 柱之頂面21 2d大於與黏晶面接合之底面2〗2e。再者，更可 藉由接地柱側面2 1 2 f之傾斜設計，即該接地柱側面2 1 2 f係 與212e底面連接形成一角度，且該角度係大於9〇度，以使 封膠材2 5 0與導線架間之接合強度提昇。 一般而言，晶片220設置於黏晶面2 12a上時，由於晶片 , 座21 2之接地柱2 1 2 b域係突出設置於黏晶面2 1 2 a之週邊上， 故塗佈於晶片黏晶面21 2a中之液態黏著層230能適當地被控 制而不易溢入晶片座2 1 2之接地柱頂面2 1 2d，如此晶片2 2 0214a 'and expose the bottom surface 212c of the chip holder 212 and the bottom surface of the pin 214 to read I 214b, so that the package structure can pass through the bottom surface 21 4b of the pin 21 4 and the bottom surface 2 1 2 c of the chip holder 2 1 2 and the external Printed circuit board (not shown) connection. It is worth noting that the 'sealing material' can also partially cover the pins and expose part of the top surface of the pins. According to the above description, when the ground pillar 2 丨 2b and the sticky crystal surface 2 1 2a are formed by etching, the top surface 21 2d of the ground pillar is larger than the junction with the sticky crystal surface by the design of the etching mask and the control of the etching time. The bottom surface 2〗 2e. Furthermore, the inclination design of the side of the grounding post 2 1 2 f can also be adopted, that is, the side of the grounding post 2 1 2 f is connected to the bottom surface of 212e to form an angle, and the angle is greater than 90 degrees to make the sealing material The joint strength between 2 50 and the lead frame is improved. Generally speaking, when the wafer 220 is disposed on the die-bond surface 2 12a, the wafer 220 is grounded on the periphery of the die-bond surface 2 1 2 a because the ground pillar 2 1 2 b of the base 21 2 is protruded on the periphery. The liquid adhesive layer 230 in the sticky surface 21 2a can be properly controlled so as not to spill into the top surface 2 1 2d of the grounding post of the wafer holder 2 1 2, so that the wafer 2 2 0

第9頁 200522318 五、發明說明（5) 藉導電線2 4 0與晶片座2 1 2之接地柱2 1 2 b接地導通時，不會 因溢出液態黏著層230 (如銀膠）之作用，而影響導電線24〇 與晶片座2 1 2接地柱2 1 2 b之接合強度。此外，為加強接地柱 頂面21 2d與導電線240之接合強度，可於接地柱頂面設置一 銀金屬層260。再者，當封膠材2 5 0包覆晶片22〇時，由於接 地柱2 1 2 b係突出於黏晶面2 1 2 a，故可增加封膠材2 5 〇與導線 以提昇封膠材250與導線架21〇之接合能 架210之接合面積 力。 此外，如圖3 A所示係本發明第二較佳實施例，圖3 b所 示係其係繪示本實施例之無外引腳封裝結構中之導線架2工〇 之上視圖。其中，引腳214之設計亦可如接地柱2i2b之設計 一樣，亦即該引腳214更包含一打線接合柱2 14c突出於=引 腳214之頂面214a，且該打線接合柱2Uc之頂面面積係=於 該打f接合柱2 14c與引腳頂面2 14a接合之面積，以更 步提昇封膠材與導線架之接合能力。 了易：ί:施例之詳細說明中所提出之具體的實施例僅為 本發明之技術内容，而並非將本發明狹義地限 制於名貝施例，因此，在不超出本發明之精神 專利範圍之情況，可作種種變化實施。 明Page 9 200522318 V. Description of the invention (5) When the conducting wire 2 4 0 and the grounding post 2 1 2 b of the chip holder 2 1 2 are grounded and conducted, the liquid adhesive layer 230 (such as silver glue) will not overflow due to the effect of This affects the bonding strength between the conductive wire 24 and the wafer holder 2 1 2 grounding post 2 1 2 b. In addition, in order to strengthen the bonding strength between the top surface 21 2d of the ground pillar and the conductive wire 240, a silver metal layer 260 may be provided on the top surface of the ground pillar. Furthermore, when the sealing material 2 50 covers the wafer 22 °, since the grounding post 2 1 2 b protrudes from the sticky crystal surface 2 1 2 a, the sealing material 2 5 0 and wires can be added to improve the sealing glue. The bonding area between the material 250 and the lead frame 21 can be the bonding area force of the frame 210. In addition, as shown in FIG. 3A is a second preferred embodiment of the present invention, and FIG. 3b is a top view showing a lead frame 2 in the outer leadless package structure of this embodiment. The design of the pin 214 can also be the same as the design of the ground pin 2i2b, that is, the pin 214 further includes a wire bonding post 2 14c protruding from the top surface 214a of the pin 214, and the top of the wire bonding post 2Uc. The surface area is the area where the bonding post 2 14c and the top surface 2 14a of the f joint are bonded to further improve the bonding ability of the sealing material and the lead frame. Easy: The specific embodiments proposed in the detailed description of the examples are merely the technical content of the present invention, and are not narrowly limited to the examples of the present invention. Therefore, the spirit patent of the present invention is not exceeded. The scope of the situation can be implemented in various changes. Bright

第10頁 200522318 圖式簡單說明 (五）、【圖式之簡單說明】 圖1為一示意圖，顯示習知一種無外引腳封裝結構的剖 面示意圖。 圖2A為一示意圖，顯示本發明第一較佳實施例之無外 引腳封裝結構之剖面示意圖。 圖2B為一示意圖，顯示本發明第一較佳實施例中導線 架之上視示意圖。 圖3A為一示意圖，顯示本發明第二較佳實施例之無外 引腳封裝結構之剖面示意圖。 圖3B為一示意圖，顯示本發明第二較佳實施例中導線 架上視示意圖。 元件符號說明】 110 導線架 112 晶片座 112a 晶片接合區 112b 接地區 112c 晶片座底面 114 引腳 114a 引腳頂面 114b 引腳底面 120 晶片 122 晶片背面 124 晶片主動表Page 10 200522318 Brief description of the drawings (5), [Simplified description of the drawings] Fig. 1 is a schematic diagram showing a conventional cross-sectional view of a package structure without external pins. FIG. 2A is a schematic view showing a cross-sectional view of the outer leadless package structure of the first preferred embodiment of the present invention. Fig. 2B is a schematic view showing a top view of a lead frame in the first preferred embodiment of the present invention. FIG. 3A is a schematic view showing a cross-sectional view of an outer leadless package structure according to a second preferred embodiment of the present invention. Fig. 3B is a schematic view showing a top view of a lead frame in a second preferred embodiment of the present invention. Component symbol description] 110 lead frame 112 wafer holder 112a wafer bonding area 112b contact area 112c wafer holder bottom surface 114 pin 114a pin top surface 114b pin bottom surface 120 wafer 122 wafer back side 124 wafer active meter

第11頁 200522318 圖式簡單說明 126 晶 片 銲 墊 128 晶 片 週 邊 130 黏 著 層（銀膠） 140 導 電 線 150 封 膠 材 210 導 線 架 212 晶 片 座 212a 黏 晶 面 212b 接 地 柱 212c 晶 片 座 底 面 212d 接 地 柱 頂 面 212e 接 地 柱 底 面 212f 接 地 柱 側 面 214 引 腳 214a 引 腳 頂 面 214b 引 腳 底 面 214c 打 線 接 合 柱 220 晶 片 222 晶 片 背 面 224 晶 片 主 動 表面 230 黏 著 層 (銀膠） 240 導 電 線 250 封 膠 材 260 銀 金 屬 層Page 11 200522318 A brief description of the drawing 126 Wafer pads 128 Wafer periphery 130 Adhesive layer (silver glue) 140 Conductive wire 150 Sealing material 210 Lead frame 212 Wafer holder 212a Adhesive crystal surface 212b Grounding post 212c Wafer bottom surface 212d Grounding post top Surface 212e Grounding post bottom surface 212f Grounding post side 214 Pin 214a Pin top surface 214b Pin bottom surface 214c Wire bonding post 220 Wafer 222 Wafer back 224 Wafer active surface 230 Adhesive layer (silver glue) 240 Conductive wire 250 Sealant 260 silver Metal layer

第12頁Page 12

Claims (1)

200522318 六、申請專利範圍 1. 一種無外引腳封裝結構，包含： 一導線架，具有一晶片座及複數個引腳，其中該晶片座具 有一黏晶面及一突出於該黏晶面之接地柱，該等引腳係 環設於該晶片座週邊，且該接地柱係設置於該黏晶面之 週邊上； 一晶片，具有一主動表面及一背面，該背面係設置於該黏 晶面上； 至少一第一導電線，該第一導電線係連接該晶片與該晶片 座之該接地柱；以及200522318 VI. Scope of patent application 1. An external leadless package structure comprising: a lead frame having a wafer holder and a plurality of pins, wherein the wafer holder has a sticky crystal surface and a protrusion protruding from the sticky crystal surface A grounding post, the pins are ringed around the wafer holder, and the grounding post is placed on the periphery of the die attach surface; a chip has an active surface and a back face, and the back face is disposed on the die attach face On the surface; at least one first conductive line, the first conductive line is connected to the chip and the ground post of the chip holder; and 至少一第二導電線，該第二導電線係連接該晶片與該引腳 之一。 2. 如申請專利範圍第1項所述之無外引腳封裝結構，其中更 包含一黏著層，且該黏著層係設置於該黏晶面與該晶片間 用以接合該晶片及該黏晶面。 3. 如申請專利範圍第2項所述之無外引腳封裝結構，其中該 黏著層係為一銀膠。At least one second conductive wire, the second conductive wire is connected to one of the chip and the pin. 2. The outer-lead-free package structure described in item 1 of the scope of patent application, which further includes an adhesive layer, and the adhesive layer is disposed between the die-bonding surface and the wafer for bonding the wafer and the die-bond. surface. 3. The outer leadless package structure described in item 2 of the scope of patent application, wherein the adhesive layer is a silver glue. 4. 如申請專利範圍第1項所述之無外引腳封裝結構，其中該 第一導電線係包含金線。 5.如申請專利範圍第1項所述之無外引腳封裝結構，其中該 第二導電線係包含金線。4. The outer-lead-free package structure described in item 1 of the scope of the patent application, wherein the first conductive wire comprises a gold wire. 5. The outer leadless package structure according to item 1 of the scope of patent application, wherein the second conductive line comprises a gold line. 第13頁 200522318Page 13 200522318 六、申請專利範圍 6接 U°:?專利範圍第1項所述之無外引卿封裝結構，其中該 接也柱係具有一接地柱頂面及—接地柱底面，該接地/ :係與該第二導電線接合且該接地柱底面係與該黏晶面接 9_如申請專利範圍第7項所述之無外引腳封裝結構，盆 接地柱頂面係設置有一銀金屬層 ，、 I 〇 ·如申請專利範圍第1項所述之無外引腳封裝結構，該引 腳具有一引腳頂面且該引腳頂面係與該黏晶面共平面。 II ·如申請專利範圍第1項所述之無外引腳封裝結構，該引 腳更匕g 打線接合柱，且該打線接合柱係突出於該引腳 頂面。 ·如申請專利範圍第1 1項所述之無外引腳封裝結構，其中 該打線接合柱更具有一打線接合柱頂面及一打線接合柱底Sixth, the scope of the patent application is 6 ° U °: The non-inductive package structure described in the first scope of the patent scope, wherein the grounding column has a top surface of the grounding column and-the bottom surface of the grounding column, and the grounding /: is connected with The second conductive wire is bonded and the bottom surface of the grounding post is connected to the sticky crystal surface. 9_ As described in No. 7 of the scope of the patent application, the top surface of the basin grounding post is provided with a silver metal layer. 〇 According to the outer lead package structure described in item 1 of the patent application scope, the lead has a pin top surface and the pin top surface is coplanar with the die-bonding surface. II. The outer leadless package structure described in item 1 of the scope of the patent application, the pin is a wire bonding post, and the wire bonding post protrudes from the top surface of the pin. The outer leadless package structure as described in item 11 of the scope of patent application, wherein the wire bonding post further has a top surface of the wire bonding post and a bottom of the wire bonding post 第14頁 200522318 六、申請專利範圍 面，該打線接合柱頂面係與該第一導電線接合且該打線接 合柱底面係與該引腳頂面接合。 1 3 · —種無外引腳封裝導線架，包含： 一晶片座，該晶片座具有一黏晶面及一犬出於该黏晶面之 接地柱，其中該接地柱設置於該黏晶面之週邊上；及 複數個引腳，該等引腳係環繞設置於該晶片座週邊。 1 4 ·如申請專利範圍第丨3項所述之無外引腳封裝導線架，其 中該接地柱係為複數個且環設於該黏晶面之周邊上。 1 5·如申請專利範圍第丨3項所述之無外引腳封裝導線架，其 中該接地柱係為一上寬下窄之柱體。 1 6 ·如申請專利範圍第丨3項所述之無外引腳封裝導線架，其 中該接地柱係由一接地柱頂面、一接地柱側面及一接地柱 底面所、纟且成’該接地柱底面係與該黏晶面接合且該接地柱 側面係與該接地柱底面傾斜接合。 1 7·如申請專利範圍第1 6項所述之無外引腳封裝導線架，其 中該接地柱側面係與該接地枉底面形成一角度，且該角度 係大於90度。 β 又 18.如申請專利範圍第13項所述之無外引腳封裝導線架，該Page 14 200522318 Sixth, the scope of the patent application, the top surface of the wire bonding post is bonded to the first conductive wire and the bottom surface of the wire bonding post is bonded to the top surface of the pin. 1 3 · —A lead frame without outer pin package, comprising: a chip holder, the chip holder having a sticky crystal plane and a grounding post out of the sticky crystal plane, wherein the grounding post is arranged on the sticky crystal plane On the periphery; and a plurality of pins, which are arranged around the periphery of the chip holder. 1 4 · The lead-free package lead frame according to item 丨 3 of the scope of patent application, wherein the grounding post is a plurality of and is arranged on the periphery of the die-bonding plane. 15. The lead frame without outer pin package as described in item 丨 3 of the scope of patent application, wherein the grounding post is a column with an upper width and a lower width. 1 6 · The lead-free package lead frame as described in item 3 of the scope of the patent application, wherein the ground post is formed by a top surface of the ground post, a side surface of the ground post, and a bottom surface of the ground post. The bottom surface of the ground post is joined to the sticky crystal surface and the side surface of the ground post is obliquely joined to the bottom face of the ground post. 17. The leadless leadframe as described in item 16 of the scope of patent application, wherein the side surface of the grounding post forms an angle with the bottom surface of the ground pin, and the angle is greater than 90 degrees. β and 18. According to the outer lead package lead frame described in item 13 of the scope of patent application, the 200522318 六、申請專利範圍 引腳更包含一打線接合柱及一引腳頂面，且該打線接合柱 係突出於該引腳頂面。 1 9 ·如申請專利範圍第1 8項所述之無外引腳封裝導線架，其 中該打線接合柱係為一上寬下窄之柱體。 i 1 I 第16頁200522318 6. Scope of patent application The pin further includes a wire bonding post and a pin top surface, and the wire bonding post protrudes from the top surface of the pin. 19 · The leadless package lead frame as described in item 18 of the scope of patent application, wherein the wire bonding post is a column with an upper width and a lower width. i 1 I p. 16
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Cited By (1)

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Publication number Priority date Publication date Assignee Title
US9653408B2 (en) 2015-08-13 2017-05-16 Win Semiconductors Corp. High-frequency package

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9653408B2 (en) 2015-08-13 2017-05-16 Win Semiconductors Corp. High-frequency package
US9673152B2 (en) 2015-08-13 2017-06-06 Win Semiconductors Corp. High-frequency package
TWI627713B (en) * 2015-08-13 2018-06-21 穩懋半導體股份有限公司 High-frequency package

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