[go: up one dir, main page]

TW200514218A - Package stack module with vertical conductive wires inside molding compound - Google Patents

Package stack module with vertical conductive wires inside molding compound

Info

Publication number
TW200514218A
TW200514218A TW092127883A TW92127883A TW200514218A TW 200514218 A TW200514218 A TW 200514218A TW 092127883 A TW092127883 A TW 092127883A TW 92127883 A TW92127883 A TW 92127883A TW 200514218 A TW200514218 A TW 200514218A
Authority
TW
Taiwan
Prior art keywords
molding compound
conductive wires
vertical conductive
stack module
package stack
Prior art date
Application number
TW092127883A
Other languages
Chinese (zh)
Other versions
TWI223879B (en
Inventor
Yung-Li Lu
Ching-Hui Chang
Cheng-Yin Lee
Shih-Chang Lee
Original Assignee
Advanced Semiconductor Eng
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Semiconductor Eng filed Critical Advanced Semiconductor Eng
Priority to TW092127883A priority Critical patent/TWI223879B/en
Application granted granted Critical
Publication of TWI223879B publication Critical patent/TWI223879B/en
Publication of TW200514218A publication Critical patent/TW200514218A/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

A package stack module with vertical conductive wires inside molding compound comprises a plurality of stacking semiconductor packages and an anisotropic conductive film disposed between the semiconductor packages. One of the semiconductor packages includes a molding compound and a semiconductor chip sealed inside the molding compound. The molding compound has a topside surface and a backside surface forming. A plurality of contact pads are formed on the backside surface and electrically connected to the semiconductor chip. A plurality of vertical conductive wires are installed inside the molding compound. Each of the vertical conductive wires has one end bonding on the contact pad and another end exposing from the topside surface of the molding compound. The anisotropic conductive film is attached on the topside surface of the molding compound for electrically connecting another semiconductor package stacked on the molding compound.
TW092127883A 2003-10-07 2003-10-07 Package stack module with vertical conductive wires inside molding compound TWI223879B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW092127883A TWI223879B (en) 2003-10-07 2003-10-07 Package stack module with vertical conductive wires inside molding compound

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW092127883A TWI223879B (en) 2003-10-07 2003-10-07 Package stack module with vertical conductive wires inside molding compound

Publications (2)

Publication Number Publication Date
TWI223879B TWI223879B (en) 2004-11-11
TW200514218A true TW200514218A (en) 2005-04-16

Family

ID=34568543

Family Applications (1)

Application Number Title Priority Date Filing Date
TW092127883A TWI223879B (en) 2003-10-07 2003-10-07 Package stack module with vertical conductive wires inside molding compound

Country Status (1)

Country Link
TW (1) TWI223879B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI570877B (en) * 2012-12-11 2017-02-11 Silergy Semiconductor Tech (Hangzhou) Ltd Multi-component chip package structure

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113781921B (en) * 2020-11-10 2022-11-22 友达光电股份有限公司 Display device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI570877B (en) * 2012-12-11 2017-02-11 Silergy Semiconductor Tech (Hangzhou) Ltd Multi-component chip package structure

Also Published As

Publication number Publication date
TWI223879B (en) 2004-11-11

Similar Documents

Publication Publication Date Title
KR100731007B1 (en) Stacked Semiconductor Packages
TWI512849B (en) Integrated circuit packaging system with package-on-package and method of manufacture thereof
KR101542214B1 (en) Integrated circuit package system with shield
US20030189256A1 (en) Bond pad rerouting element, rerouted semiconductor devices including the rerouting element, stacked chip assemblies including the rerouted semiconductor devices, and methods
TW200504995A (en) Stacked chip semiconductor device and method for manufacturing the same
US6262479B1 (en) Semiconductor packaging structure
SG148851A1 (en) Stacked semiconductor packages
KR20090033141A (en) Integrated Circuit Package System with Leadframe Array
CN106470527B (en) Printed circuit board structure for forming enhanced fingerprint identification module
TWI225291B (en) Multi-chips module and manufacturing method thereof
SG137770A1 (en) Interconnect structure and formation for package stacking of molded plastic area array package
US20120241979A1 (en) Integrated circuit packaging system with step mold and method of manufacture thereof
TW200514218A (en) Package stack module with vertical conductive wires inside molding compound
CN102157502B (en) System-in-package structure
US7659620B2 (en) Integrated circuit package employing a flexible substrate
CN101290929A (en) Stack type chip packaging structure
TW202101729A (en) Semiconductor devices and methods for manufacturing the same
KR20100050981A (en) Semiconductor package and stack package using the same
KR100708050B1 (en) Semiconductor Package
KR100747996B1 (en) Semiconductor package
CN105742283B (en) It is inverted stack package
KR20010036630A (en) Stack chip package
CN117116922A (en) Packaging structure and packaging method
KR20030057189A (en) Semiconductor package
KR20030046794A (en) Multi stack chip package

Legal Events

Date Code Title Description
MK4A Expiration of patent term of an invention patent