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TW200504753A - Clock synchronous type semiconductor memory device - Google Patents

Clock synchronous type semiconductor memory device

Info

Publication number
TW200504753A
TW200504753A TW093105686A TW93105686A TW200504753A TW 200504753 A TW200504753 A TW 200504753A TW 093105686 A TW093105686 A TW 093105686A TW 93105686 A TW93105686 A TW 93105686A TW 200504753 A TW200504753 A TW 200504753A
Authority
TW
Taiwan
Prior art keywords
row address
signal
type semiconductor
memory device
semiconductor memory
Prior art date
Application number
TW093105686A
Other languages
English (en)
Other versions
TWI248081B (en
Inventor
Sachiko Edo
Original Assignee
Elpida Memory Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Elpida Memory Inc filed Critical Elpida Memory Inc
Publication of TW200504753A publication Critical patent/TW200504753A/zh
Application granted granted Critical
Publication of TWI248081B publication Critical patent/TWI248081B/zh

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2254—Calibration

Landscapes

  • Dram (AREA)
  • Static Random-Access Memory (AREA)
  • Read Only Memory (AREA)
TW093105686A 2003-03-07 2004-03-04 Clock synchronous type semiconductor memory device TWI248081B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2003061420A JP2004273008A (ja) 2003-03-07 2003-03-07 クロック同期式半導体記憶装置

Publications (2)

Publication Number Publication Date
TW200504753A true TW200504753A (en) 2005-02-01
TWI248081B TWI248081B (en) 2006-01-21

Family

ID=32923633

Family Applications (1)

Application Number Title Priority Date Filing Date
TW093105686A TWI248081B (en) 2003-03-07 2004-03-04 Clock synchronous type semiconductor memory device

Country Status (4)

Country Link
US (1) US6940763B2 (zh)
JP (1) JP2004273008A (zh)
CN (1) CN1527322B (zh)
TW (1) TWI248081B (zh)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100568546B1 (ko) * 2004-10-19 2006-04-07 삼성전자주식회사 메모리 시스템, 반도체 메모리 장치, 및 이 시스템과장치의 출력 데이터 스트로우브 신호 발생 방법
KR100641704B1 (ko) * 2004-10-30 2006-11-03 주식회사 하이닉스반도체 반도체 메모리 소자 및 그 비트라인 센스앰프 옵셋전압측정방법
JP2007141383A (ja) * 2005-11-18 2007-06-07 Elpida Memory Inc 半導体記憶装置
KR100735011B1 (ko) * 2006-01-23 2007-07-03 삼성전자주식회사 노어 플래시 메모리 및 그것의 읽기 방법
US7423928B2 (en) * 2007-01-30 2008-09-09 Atmel Corporation Clock circuitry for DDR-SDRAM memory controller
JP2012026950A (ja) * 2010-07-27 2012-02-09 Sony Corp 集積半導体装置
TW201315189A (zh) * 2011-09-27 2013-04-01 Princeton Technology Corp 具有串列傳輸介面設計並可接收兩通信規格的積體電路
CN114115437B (zh) 2020-08-26 2023-09-26 长鑫存储技术有限公司 存储器
CN114115439A (zh) 2020-08-26 2022-03-01 长鑫存储技术有限公司 存储器
US12190994B2 (en) * 2022-12-29 2025-01-07 Xilinx, Inc. Single port memory with multiple memory operations per clock cycle

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2970434B2 (ja) 1994-10-31 1999-11-02 日本電気株式会社 同期型半導体記憶装置およびセンス制御方法
JPH08221981A (ja) * 1994-12-15 1996-08-30 Mitsubishi Electric Corp 同期型半導体記憶装置
KR100232895B1 (ko) 1996-12-31 1999-12-01 김영환 센스앰프 인에이블 신호 발생 장치
JPH10334659A (ja) * 1997-05-29 1998-12-18 Mitsubishi Electric Corp 同期型半導体記憶装置
JPH1116349A (ja) * 1997-06-26 1999-01-22 Mitsubishi Electric Corp 同期型半導体記憶装置
US6029250A (en) * 1998-09-09 2000-02-22 Micron Technology, Inc. Method and apparatus for adaptively adjusting the timing offset between a clock signal and digital signals transmitted coincident with that clock signal, and memory device and system using same
KR100287542B1 (ko) * 1998-11-26 2001-04-16 윤종용 웨이브 파이프라인 스킴을 구비한 동기형 반도체 메모리 장치및 그것의 데이터 패스 제어 방법
JP2000285687A (ja) 1999-03-26 2000-10-13 Nec Corp 半導体記憶装置及びその内部回路を活性化する信号のタイミング発生方法

Also Published As

Publication number Publication date
US20040174751A1 (en) 2004-09-09
US6940763B2 (en) 2005-09-06
CN1527322A (zh) 2004-09-08
TWI248081B (en) 2006-01-21
JP2004273008A (ja) 2004-09-30
CN1527322B (zh) 2010-04-28

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees