[go: up one dir, main page]

TW200501355A - Stacked chip package structure - Google Patents

Stacked chip package structure

Info

Publication number
TW200501355A
TW200501355A TW092117781A TW92117781A TW200501355A TW 200501355 A TW200501355 A TW 200501355A TW 092117781 A TW092117781 A TW 092117781A TW 92117781 A TW92117781 A TW 92117781A TW 200501355 A TW200501355 A TW 200501355A
Authority
TW
Taiwan
Prior art keywords
chip package
package unit
conductive pins
package structure
stacked chip
Prior art date
Application number
TW092117781A
Other languages
Chinese (zh)
Other versions
TWI227553B (en
Inventor
Gwo-Liang Weng
Shih-Chang Lee
Su Tao
Ching-Hui Chang
Original Assignee
Advanced Semiconductor Eng
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Semiconductor Eng filed Critical Advanced Semiconductor Eng
Priority to TW092117781A priority Critical patent/TWI227553B/en
Publication of TW200501355A publication Critical patent/TW200501355A/en
Application granted granted Critical
Publication of TWI227553B publication Critical patent/TWI227553B/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Wire Bonding (AREA)

Abstract

A stacked chip package structure includes a first chip package unit, a second chip package unit stacked over the first chip package unit, and a tape carrier with a tape and a plurality of conductive pins. One end of the conductive pins is electrically connected with the first chip package unit, and the other end of the conductive pins is electrically connected with the second chip package unit. In addition, the second chip package unit includes a plurality of solder balls located under the base to connect with conductive pins correspondingly.
TW092117781A 2003-06-30 2003-06-30 Stacked chip package structure TWI227553B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW092117781A TWI227553B (en) 2003-06-30 2003-06-30 Stacked chip package structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW092117781A TWI227553B (en) 2003-06-30 2003-06-30 Stacked chip package structure

Publications (2)

Publication Number Publication Date
TW200501355A true TW200501355A (en) 2005-01-01
TWI227553B TWI227553B (en) 2005-02-01

Family

ID=35696413

Family Applications (1)

Application Number Title Priority Date Filing Date
TW092117781A TWI227553B (en) 2003-06-30 2003-06-30 Stacked chip package structure

Country Status (1)

Country Link
TW (1) TWI227553B (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI269420B (en) 2005-05-03 2006-12-21 Megica Corp Stacked chip package and process thereof
TW200917431A (en) 2007-10-05 2009-04-16 Advanced Semiconductor Eng Stacked-type chip package structure and method of fabricating the same
TWI419270B (en) * 2011-03-24 2013-12-11 Chipmos Technologies Inc Package on package structure

Also Published As

Publication number Publication date
TWI227553B (en) 2005-02-01

Similar Documents

Publication Publication Date Title
TW200501345A (en) Stacked-type semiconductor device
TW200703616A (en) Stacked type semiconductor device
ATE417357T1 (en) BGA PACKAGING WITH SOLDER BALLS NOT ELECTRICALLY CONNECTED
MY122959A (en) Stacked microelectronic packages
TW428258B (en) Semiconductor device with connection terminals in the form of a grid array
TW200627563A (en) Bump-less chip package
SG120069A1 (en) Semiconductor device assemblies and packages including multiple semiconductor devices and methods
TWI315571B (en) Integrated circuit packaging
TW200511612A (en) Mount for semiconductor light emitting device
CA2218307A1 (en) Three dimensional packaging configuration for multi-chip module assembly
EP1681717A4 (en) Electronic device and process for manufacturing same
CN203445108U (en) Chip packaging and switching board and circuit board with chip packaging and switching board
TW200620607A (en) Flip chip and wire bond semiconductor package
TW200507207A (en) Chip package structure
TW200620684A (en) Power LED package
TW200620585A (en) Semiconductor package structure and method for fabricating the same
TW200516732A (en) Semiconductor package
TW200501355A (en) Stacked chip package structure
TW200737445A (en) Chip package structure
DE60116378D1 (en) ELECTRONIC DATA CARRIER
TW200612529A (en) Cavity down stacked multi-chip package
TW200605371A (en) Integrated circuit package with improved power signal connection
TW200715586A (en) Universal chip package structure
TWI268602B (en) Semiconductor device featured with using micro bumps to connect the first semiconductor chip and the second semiconductor chip when stacking the first semiconductor chip and the second semiconductor chip together
CA2418683A1 (en) Area-array with low inductance connecting device

Legal Events

Date Code Title Description
MK4A Expiration of patent term of an invention patent