TW200423349A - Chip package structure - Google Patents

Abstract

A chip package structure is disclosed. The chip package structure essentially comprises a carrier, one or more chips, a heat sink and an encapsulating material layer. At least one of the chips is flip chip bonding to and electrically connects the carrier or other chips, and there is a flip chip bonding gap between the chip and the carrier or other chips. The heat sink is disposed over the top chip. The encapsulating material layer is filled with the flip chip bonding gap, and between the top chip and the heat sink. The part of surface of heat sink that far away the chip is exposed. The encapsulating material layer is composed of single encapsulating material. Otherwise, the gap between the top chip and the heat sink is between 0.03mm to 0.2mm for example. The thermal conductivity of encapsulating material layer is more than 1.2 W/m.K for example.

Description

200423349 V. Description of the invention (1) [Technical field to which the invention belongs]

The present invention relates to a structure (S structure), and in particular a package structure (chlP package.) [Related technology]-a kind of chip with excellent heat dissipation [prior technology] In a highly information society Today, the market share of (Portable electric devip, recognizing the ancient I attacking ice) is constantly growing. The chip packaging technology also needs to be matched with the digital set of electronic speed w-speed expanders, and the number of digital devices. The development of the trend of becoming more integrated, networked, regionally connected, and user-friendly. To enhance the high-speed processing, multifunctionalization, integration, miniaturization, and weight reduction of electronic components Therefore, the chip packaging technology is also developing towards miniaturization and high density. Among them: Flip Chip bonding (FVC bonding) technology is more familiar because it is bonded with bumps and Carriers. It is known that the wire bonding method greatly shortens the wiring length and helps to improve the signal transmission speed between the chip and the carrier. Therefore, it has gradually become the mainstream of high-density packaging. The important issue from the packaging technology is how to solve the heat dissipation problem of the chip packaging structure with high accumulation. Figure 1A is a cross-sectional view of a conventional chip packaging structure using wire connection. Please refer to section 1A In the figure, the wafer 20 has an active surface 22, and a plurality of solder pads (not shown) are further arranged on the active surface 22. The wafer 20 is arranged on the carrier board 30 with the active surface 22 facing upward. The surface of the carrier board 30 A plurality of contacts (not shown) are arranged on the two ends. The two ends of the plurality of wires 24 are connected to the pads of the chip 20 and the contacts of the carrier 30, respectively, and are electrically connected to the chip 20 and the carrier 30 .

11845twf.ptd Page 8 200423349 V. Description of the invention (2) Moreover, the surface of the carrier plate 30 away from the wafer 20 is further provided with a plurality of arrayed solder balls (S ο 1 derba 1 1) 3 2, which is the chip packaging structure. The 10 series adopts Ball Grid Array packaging (BGA packaging), so that the chip packaging structure can be electrically connected to a printed circuit board (PCB) (not shown) in the future. In addition, a packaging material layer 34 is disposed on the carrier board 30 and covers the chip 20 and the wires 24 to provide protection. However, this chip package structure 10 has the disadvantage of poor heat dissipation. dew. Package 1A The package conduction problem section between the good crystals 36 is connected to the dynamic table configuration 52. Therefore, the chip package structure with a heat sink (Heatsink) is revealed. Figure 1B shows the conventional method of installing a heat sink. A cross-sectional view of a wire-connected chip structure. Please refer to FIG. 1B. The chip package structure 丨 2 is based on the chip package structure 10 shown in the figure, and a heat sink 36 is added to improve the heat dissipation of the package structure 12. However, since there are wires 24 between the wafer 20 and the heat sink, the distance between the wafer 20 and the heat sink 36 cannot be shortened, and the distance is about 0.25 to 0.5 mm. In this way, the thicker material layer 34 will cause the poor performance of the active surface 22 to the diffuser wafer 36 of the wafer 20, which will also become the two important issues to be overcome in the high-power design of the wafer. Referring to FIG. 2 for spraying a conventional chip packaging structure using flip-chip bonding technology, the wafer 50 has an active surface 52 and a plurality of solder pads (not shown) are further arranged on the main body. 1ϋ contacts on the surface of the carrier plate 80 (not shown). The plurality of bumps 60 are arranged at the active surface point, and the bumps 60 are electrically connected between the wafer 50 and the carrier plate 80 through the pads of the wafer 50 and the carrier plate 80. Among them, the carrier board 8

200423349 V. Description of the invention (3) The surface far from the wafer 50 is further provided with a plurality of solder balls 60 arranged in an array. In order to protect the wafer 50 from being damaged by moisture, the bump 60 connecting the wafer 50 and the carrier board 80 is protected from being damaged by the shear force. Therefore, a packaging material layer 70 is formed. Between 50 and the carrier plate 80. Knowing the formation of the packaging material layer 70, a fine phenomenon, filling liquid crystal packaging materials with a lower viscosity into the crystal wafer '"== the flip-chip bonding gap between the two', and then hardening the packaging material. As mentioned above, the chip package structure 40 has better electrical performance than the connected chip package structure 10 shown in FIG. 1A and conforms to the thinning trend of the chip package structure. However, the package ^ yu ^ It takes a long time 'does not meet the industry's production requirements. Also, because the packaging material is based on natural capillary phenomenon, the gap between the people, the number of bumps 60 between the wafer 50 and the carrier board 80, ί ί ί 大小 The size of the gap will affect the flowability of the packaging material, ΐ (Reliability). Ordering with S 赖 Reliability In addition, because the 50 chip is directly exposed to the outside, the characteristics of the (Marking) chip are in the 5 chip. When the surface, or when you attach the chip 50 to move the chip package structure 40, it is 9 true damage. 4 To improve this shortcoming, another practice is created. Figures 3A and 3B show another A conventional mining method = a cross-section of a chip package structure Figure. Please refer to Figure 3A, which is based on the chip packaging structure 40 of Figure 2 and added an M structure 42 1 1 \ Γ7 η θ to seal the layer (0 verm〇ld) 72 to protect Wafer 50 is not subject to marking and movement \

Η 11845twf.ptd Page 10 ^ 0423349 V. Description of Invention (4) '一 "'-Bad. Production capacity ^ ί, the process time required to form the top mold layer 7 2 will be relatively easy to develop, and the interface between the packaging material layer 70 and the top mold layer 72 is also separated by the name of the surname / 面 面 ㈣ ㈣ ㈣ The phenomenon of ^^^^ 'further reduces the reliability of the chip π-structure 42. Therefore, the chip package structure 44 according to the crystal of FIG. 3A is also exposed. Since the chip package structure 44 covers the wafer 50 and the carrier board 80 and fills the seal, the interface peeling can be avoided. There is a disadvantage that the heat of the package 44 cannot be easily radiated above the chip 50. [Summary of the Invention] Therefore, the object of the present invention is to use a wafer for bonding in a chip packaging structure, while providing the wafer. Piece. The chip is electrically connected to the carrier board with an active surface orientation. The heat sink is filled between the chip and the carrier board and the surface away from the chip is formed at least partially by a single packaging material. The chip packaging structure 42 is improved. The third invention is disclosed in the invention of J P 3 9 2 6 9 8 and the packaging material layer 74 is formed at one time to cover the shortcomings of the distance between the wafer 50 and the carrier plate 80. However, this design still uses the material layer 74, which results in the chip package structure providing a chip package structure, which is suitable for flip-chip bonding technology with excellent electrical properties. The shock-absorbing structure has excellent heat dissipation. A chip packaging structure is proposed, which is mainly composed of a thermal sheet and a packaging material layer. A plurality of convex carrier plates are arranged on the active surface, and the flip chip is bonded to the carrier plates and arranged on the wafer. The packaging material layer is between the chip and the heat sink, and the heat sink is exposed to the outside, and the packaging material layer is

200423349 V. Description of the invention (5) Based on the above object, the present invention further proposes a chip packaging structure, which is mainly composed of a carrier board, a chip set, a heat sink and a packaging material layer. The chip set is disposed on the carrier board and is electrically connected to the carrier board. The wafer group is mainly composed of multiple wafers, and at least one of the wafers is bonded to a carrier board or other wafers, and a flip-chip bonding gap is maintained. The heat sink is disposed on the chipset. The packaging material layer is filled in the flip-chip bonding gap and between the chipset and the heat sink, and the surface of the heat sink away from the chipset is at least partially exposed to the outside, and the packaging material layer is formed of a single packaging material. In addition, the wafer set of this embodiment is mainly composed of a first wafer and a second wafer, for example. The first chip has a first active surface, and the first chip is disposed on the carrier board with the first active surface facing away from the carrier board. The second wafer has a second active surface, and a plurality of bumps are disposed on the second active surface. The second chip is flip-chip bonded to the first chip with the second active surface facing the first chip, and is electrically connected to the first chip. The bumps maintain the flip-chip bonding gap. In addition, the chipset further includes a plurality of wires, for example. The two ends of each wire are electrically connected to the first chip and the carrier board, respectively. In addition, the chip set of this embodiment may be mainly composed of a first chip, a second chip, and a third chip. The first wafer has a first active surface, and a plurality of first bumps are disposed on the first active surface. The first chip is flip-chip bonded to the carrier with the first active surface facing the carrier, and is electrically connected to the carrier. The second wafer has a second active surface, and the second wafer is disposed on the first wafer with the second active surface facing away from the first wafer.

11845twf.ptd Page 12 200423349 V. Description of Invention (6). The third wafer has a third active surface, and a plurality of second bumps are disposed on the third active surface. The third wafer is flip-chip bonded to the second wafer with the third active surface facing the second wafer, and is electrically connected to the second wafer. The first bump and the second bump maintain a flip-chip bonding gap. In addition, the chipset further includes a plurality of wires, for example. The two ends of each wire are electrically connected to the second chip and the carrier board, respectively. In the above two embodiments of the chip package structure, the distance between the chip and the heat sink is, for example, between 0.03 and 0.2 millimeters (m m). The thermal conductivity of the packaging material layer is, for example, greater than 1.2 Watts / meter-Kelvin (W / m. K), and the material is, for example, a resin. The material of the heat sink is, for example, metal. The chip package structure further includes, for example, a plurality of arrayed solder balls and at least one passive component. The solder balls are, for example, disposed on the surface of the carrier plate where no wafer is disposed. The passive element is, for example, disposed on the carrier board and electrically connected to the carrier board. The carrier board is, for example, a packaging substrate or a lead frame. In summary, according to the chip package structure proposed by the present invention, since a heat sink is arranged above the chip, it can provide an excellent heat dissipation path for the chip package structure, thereby improving the operational reliability of the chip package structure. In addition, since the thickness of the packaging material layer between the chip and the heat sink is optimized, the heat conduction efficiency between the chip and the heat sink can be greatly improved. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, preferred embodiments are described below in detail with the accompanying drawings, as follows. [Embodiment] FIG. 4 illustrates a first preferred embodiment according to the present invention.

11845twf.ptd Page 13 200423349 V. Description of the invention (7) A cross-sectional view of a chip package structure. Referring to FIG. 4, the chip package structure i 〇 ○ is mainly composed of a carrier board 180, a chip 150, a heat sink 140, and a material layer 170. Among them, the carrier board 180 is an packaging substrate such as an organic substrate, a ceramic substrate, a flexible substrate, or a flip chip quad flat non-leaded packaging (F / C QFN packaging). ), Etc. Lead frames used in packaging processes. The upper and lower surfaces of the carrier plate 180 have, for example, a plurality of contacts (not shown). The wafer 150 has an active surface 15 2, and the wafer 150 is bonded to the upper surface of the carrier plate 180 with the active surface 15 2 facing the carrier plate 180. For example, a plurality of solder pads (not shown) are arranged on the active surface of the wafer 150, and a plurality of bumps 160 are arranged on solder pads on the active surface 15 of the wafer 150. The wafer 150 is electrically connected to the carrier board 18 through the bump 160 on the bonding pad. That is, the wafer package structure 100 of this embodiment includes at least one wafer 150 ', and the wafer 150 is bonded to the upper surface of the carrier plate 180 using a flip-chip bonding technology. However, in addition to the chip 150, in this embodiment, other chips or other components (such as resistors, capacitors, and other passive components) may be provided on the carrier plate 180 in the package structure 100. The heat sink 140 is disposed on the chip 150, and an edge of the heat sink 140 is extended with a plurality of heat sink pins 42, for example. The heat-dissipating pin 142 extends, for example, from the edge of the heat-dissipating sheet 140 to the carrier plate 19, and the heat-dissipating pin 42 helps to accelerate the heat conduction between the thermal sheet 140 and the carrier plate 180. Moreover, the area of the heat sink ho is, for example, larger than the area of the chip 150 to obtain a better heat dissipation efficiency. However, the heat sink 140 is not limited to being integrally formed.

11845twf.ptd Page 14 200423349 V. Description of the invention (8) Consisting of independent heat sinks, this design is conducive to the flexible use of large-area chip packaging structures. In addition, the packaging material layer 170 is filled between the chip 150 and the carrier board 180 and between the chip 150 and the heat sink 140, but does not cover all the surfaces of the heat sink 140 far from the chip 150. The packaging material layer 170 is formed of a single packaging material. Please also refer to FIG. 4. In this embodiment, the distance between the chip 150 and the heat sink 140 is preferably 0.3 mm or less. If it exceeds 0.3 mm, the filling material layer 1 7 0 is filled. After the chip 150 and the heat sink 140, the heat dissipation will be less satisfactory. The distance between the chip 150 and the heat sink 140 is preferably between 0.3 and 0.2 mm. If it is less than 0.3 mm, it will be difficult to fill the packaging material layer 170 between the chip 150 and the chip 150. Between the heat sinks 140. The material of the packaging material layer 170 is, for example, a resin, and in order to ensure the heat dissipation effect, the thermal conductivity of the packaging material layer 1 70 is preferably greater than 1.2 Watts / meter-Kelvin temperature. The material of the heat sink 1 40 is, for example, metal. In the present invention, the heat sink 14 of a metal material, which has a much larger area than the wafer 150, is mainly used to diffuse the heat generated by the wafer 150 in a wide range, so the one with the best thermal conductivity is the best. Generally, for example, a copper plate, an aluminum plate, an iron plate, a nickel plate, or a gold-plated surface is used. In addition, since the heat sink 140 must be able to withstand the pressure during the packaging process, it is desirable to have a strength that is not easily bent. Although it varies depending on the type of metal, the heat sink 1 40 is preferably, for example, a thickness of 0.1 mm or more. In addition, in order to increase the tightness of the interface between the packaging material layer 170 and the heat sink 140, in addition to performing gold plating on the surface of the heat sink 140, for example,

11845twf.ptd Page 15 200423349 V. Description of the invention (9) The surface of the heat sink 140 may be subjected to, for example, surface chemical treatment or physical treatment. The encapsulation process is performed on the chip packaging structure 100 so that the mounting material layer 17 0 ′ ′ and the heat sink 14 4 must be fixed on the carrier plate 180 with, for example, an adhesive and soldering. As long as the adhesive can withstand the temperature production / pressure during packaging, the heat sink 140 will not be displaced. Therefore, ^ the shape of the heat sink 140 and the adhesion of the heat sink 140 to the carrier plate 180 are better considered. When selecting an adhesive, it is not necessary to use an adhesive to improve heat dissipation. In addition, the chip package structure 00 further includes, for example, a plurality of arrays = balls 190 and at least one passive element 195. Among them, the solder balls 9 are arranged on the contacts on the lower surface of the carrier board 180. The solder balls 19 〇 is provided for use after the crystal structure 100 for example for electrical connection with printed circuit boards. Passive # 元 $ 件》 195 is, for example, arranged on the upper surface of the carrier board 18 and is connected to the carrier board. It is worth noting What is more, the structure of the present invention, 'the wafer packaging junction system of the present invention, is' formed once', so interface peeling can be avoided. Different from the conventional wafer packaging structure 100 shown in FIG. 3A, the packaging materials of each part are divided. The interface 280 of the sub-molded packaging material. Figures 5 and 6 are cross-sectional views of the chip packaging structure according to the second preferred embodiment of the present invention. In the package structure of the example, the main reason is to add more than two crystals. The same points as the first preferred embodiment will not be repeated here. Please refer to Figure 5 and Figure 6 for chip packaging. Seismic structure 2000 is mainly composed of a carrier plate and a crystal Group 250, a heat sink with a sealing material layer 24〇 the configuration 27〇

200423349 V. Description of Invention (10). Among them, the wafer group 250 is mainly composed of multiple wafers, and at least one of the wafers is bonded to the carrier board 280 or other wafers by flip-chip bonding technology. Therefore, there exists at least one flip-chip bonding gap 2 5 6 in the 'wafer group 250'. The flip-chip bonding gap 2 56 is formed by bumps on the wafer using flip-chip bonding. The heat sink 240 is disposed on the chipset 250. The encapsulating material layer 270 is filled in the flip-chip bonding gap 256, and between the chipset 250 and the heat sink 240. ^ Moreover, the distance between the chip 250 and the heat sink 240 is preferably between 0.03 and 0.2 mm. The thermal conductivity of the packaging material layer 270 is, for example, preferably greater than 1.2 Watts / meter-Kelvin. Referring to FIG. 5, the chip set 250 of the preferred embodiment is mainly composed of a first wafer 250a and a second wafer 250b, for example. Among them, the arrangement relationship of each element is as follows. The first wafer 250a has a first active surface 252a, and the first wafer 250a is disposed on the carrier plate 280 with the first active surface 252a facing upward. The second wafer 250b has a second active surface 252b, and a plurality of bumps 260 are disposed on the second active surface 252b. The second wafer 2 50 b is flip-chip bonded to the first wafer 250 a with the second active surface 2 5 2 b facing the first wafer 250 a, and is electrically connected to the first wafer 250a. The bump 2 6 0 maintains the flip-chip bonding gap 2 5 6. In addition, the chipset 250 includes, for example, a plurality of wires 254b. For example, a plurality of contacts (not shown) are arranged on the surface of the carrier plate 280, and a plurality of solders are arranged on the first active surface 252a of the first wafer 250a and the second active surface 252b of the second wafer 250b, for example. Pad (not shown). The bump 2 6 0 of the second wafer 2 5 0 b maintains the flip-chip bonding gap 2 5 6 between the first wafer 2 5 0a and the second wafer.

11845twf.ptd Page 17 200423349 V. Description of the invention (11) Between 2 5 0 b. In other words, the second wafer 250b is bonded to the first active surface 252a of the first wafer 250a by a flip-chip bonding technique. The two ends of each wire 254b are, for example, electrically connected to the contacts of the soldering pad of the first chip 250a and the carrier 2800 respectively. Referring to FIG. 6, the chipset 250 of the preferred embodiment is composed of, for example, a first wafer 250a, a second wafer 250b, and a third wafer 250c. The chip set 2 5 0 further includes a plurality of wires 2 5 4b, for example. Among them, the arrangement relationship of each element is as follows. The first wafer 250a is disposed on the carrier board 2800, and the first wafer 250a has a first active surface 252a, and a plurality of first bumps 260a are disposed on the first active surface 252a. The first chip 250a is bonded to the carrier plate 280 with the first active surface 252a facing the carrier plate 280, and is electrically connected to the carrier plate 280. The second wafer 250b has a second active surface 252b, and the second active surface 252b faces away from the first wafer 250a. In addition, the plurality of wires 2 54b are connected to the bonding pads on the second active surface 2 5 2b of the second chip 250b and the contacts of the carrier board 280 to electrically connect the second chip 250b. With carrier plate 280. The third wafer 250c has a third active surface 252c. The third active surface 252c is provided with a plurality of second bumps 260b. The third wafer 250c is flip-chip bonded to the second wafer 250b with the third active surface 252c facing the second wafer 250b, and is electrically connected to the second wafer 250b. The first bump 2 6 0 a and the second bump 2 6 Ob maintain the flip-chip bonding gap 2 5 6. In other words, the third wafer 2 50 a is bonded to the second active surface 2 52 b of the second wafer 2 50 b by the flip-chip bonding technology, and the first wafer 25 0 a is bonded to the carrier plate 2 5 Ob by the flip-chip bonding technology. The surface. In the second preferred embodiment proposed by the present invention, it is the same as the first preferred embodiment.

Page 18 200423349 V. Description of the invention (12) The embodiment is mainly to increase the number of wafers, and at the same time, it is not limited that all wafers are bonded to the carrier board using flip-chip bonding technology. The most important feature of the present invention is that at least one wafer is included in the chip package structure, and the wafer is bonded to a carrier board or other wafers using a flip-chip bonding technology. Moreover, a heat sink is arranged above the chip. There is an encapsulation material layer between the heat sink and the wafer and in the flip-chip bonding gap. The encapsulation material layer is formed with the same "m white." As long as any implementation mode that meets the above main characteristics, it should fall within the scope of the present invention. Fig. 7A is a cross-sectional view of the finished product after the wafer packaging process is completed according to a preferred embodiment of the present invention. Fig. 7B is a preferred implementation of the present invention. The chip package structure of the example is a cross-sectional view of the finished product after the Yuancheng chip packaging process is cut. Please refer to Figures 7A and 7B together. In order to meet the needs of mass production, the packaging process of this preferred embodiment is being formed. After the packaging material layer 700, for example, dicing is performed along the cutting line L to form a plurality of wafer packaging structures 100. Among them, each wafer packaging structure 100 includes at least one wafer 150. In addition, Although the packaging material layer 170 shown in FIG. 7A is connected as a whole, the process mold can also be adjusted to form multiple independent packaging material layers 170, which is not shaped at the cutting line. The packaging material layer is used to reduce the time required for subsequent cutting. It is worth noting that 'in the process of mf: structure according to the preferred embodiment of the present invention, the method of forming the packaging material layer is, for example, decompression Transfer injection molding method. Decompression transfer injection molding method refers to placing the wafer structure to be packaged into a mold, and after the mold enters a reduced pressure state, it is placed in the mold.

200423349 V. Description of the invention (13) A method of introducing a hot-melt material and subjecting it to heat and pressure to harden the resin. The general transfer injection molding method is not decompressed, which may cause insufficient filling of the flip-chip bonding gap or the packaging material between the wafer and the heat sink. Right. Keep the pressure-relief complaint in the fixture at 20 mm. In the following, a better packaging effect can be obtained. The optimal value of the reduced pressure state is below 0 mm-mercury column =. FIG. 8 is a cross-sectional view of a chip packaging structure forming a packaging material layer in a reduced-pressure transfer injection molding mold according to a preferred embodiment of the present invention. Referring to FIG. 8, the transfer injection molding equipment (not shown) can place a suitable mold 300 according to the required package type. The mold 300 is mainly composed of an upper mold 310 and a lower mold 320. When the upper mold 31 and the lower mold 32 () are closed, in order to achieve a more efficient vacuum effect, the mold closing step is the first step. Then, a vacuum pump (not shown) is used to perform the vacuum treatment in the mold cavity 340 through the vacuum pump. Then, put into the cake production) within 35 ° of the pipeline, and maintain it for 2 5 seconds to raise the true second degree in the second room, and at the same time raise the temperature in the mold to melt the packaging material. Finally, the upper mold 3 丨 〇 and the lower mold ^ ^ are completely tightly closed, and at the same time, the column is pulled up to guide, heat, and melt the encapsulation material to fill the mold cavity 34. Min. When Men Fancheng's decompression transfer is performed, the forming temperature control is better, and the molding temperature is higher than that produced by the packaging material on the wafer 150. The decompression transfer injection molding is formed at a temperature of at least 5 degrees Celsius below the melting point of the bump 160. At this time, compared with the molten state during molding

11845twf.ptd Page 20 200423349 V. Description of the invention (14) The stress of life is not enough, and it is easy to fall. Moreover, the wafer is constructed to have a smaller particle size gap than the flip-chip junction or the wafer to scatter causing incomplete filling of the wafer surface. It is added in the sealed state of the peroxite, alumina, and material sheet overlay. The liquid flow is called the column and the surface, and the crystal is connected to the root to form a state seal process. Considering the production, "it's like the real liquid, so the joint packaging material can be air-printed and sealed at this time, block 160 pairs; ^ & k decompression transfer two Λ and the carrier plate 180 flip chip bonding strength transfer injection molding During the process, the chip J 50 is removed, and jj is mentioned: The maximum particle diameter t of the packaging material used for the chip packaging of the preferred embodiment is preferably doubled. If the packaging material used = When the cover b is 0.5 times the bonding gap, it is difficult to fill the packaging material between the plates, even the shape of the I. Moreover, the surface of the wafer may be damaged due to the packaging material filling. In order to reduce the heat-conducting filler of the reliable mounting material layer of the wafer, in addition to the conventionally used melting, Shi Xi ', in order to improve heat dissipation, you can also use crystalline Shi Xi silicon nitride, boron nitride, aluminum nitride and other thermal conduction Due to the higher hardness of the better thermally conductive packaging material, the maximum particle size of the thermally conductive filler added to the crystal is preferably not 1/5 times the super gap. The chip packaging process of the preferred embodiment of the invention is only Another method of the material layer is to decompress State, encapsulation materials at room temperature, and pressure, heat curing a two-step process the encapsulating material encapsulating materials may be encapsulated using plastic equipment, but it is preferable that the printing process can also use a commercial market, Brush "of the device. When the decompression state of the material during the packaging process is 2 mm-mercury, the filling material may be filled when the pressure exceeds 2 mm-mercury.

11845twf.ptd 200423349

Charge incomplete phenomenon. In addition, the filling and shaking of the skin u μ μ ^ test P ~ R eight packaging materials after the pressure heating and hardening process ^ on the 'common order to 2 ~ 5 kg / square centimeter ^ Shizhuang clothing T 々 A knife pressure As for heating, it depends on the hardening of the packaging material. For this chip packaging process, in the pressurized state before hardening, it is best to heat at a temperature above 40 degrees Celsius and below the hardening temperature for more than 3 minutes in advance. This will promote packaging before the viscosity of the packaging material increases. Material filling. For the packaging material used in this process, the maximum particle size of the liquid packaging material filler is preferably less than 1/3 times the flip-chip bonding gap and more than 95% by weight. When the particles larger than 1/3 are more than 5% by weight, The filling of the packaging material of the flip-chip bonding gap is liable to be blocked due to the large volume, resulting in incomplete filling of the packaging material. In addition to the conventionally used silicon dioxide in the molten state, the thermally conductive filler added to the encapsulation material layer can be used to improve heat dissipation. Crystal stones, oxides, nitrides, nitrides, nitrides Shao and other materials with better thermal conductivity. In addition, in order to reduce the stress in the chip packaging structure, and thus avoid the warpage of the carrier board, if the liquid packaging material used contains an elastic dispersion, the weight percentage of the elastic dispersion is better than ^, and it is non-existent. The large particle size of the dispersed product is preferably less than 1/3 p of the flip-chip bonding gap (application example of the invention) [Example 1] The area size is 8 mm X 8 mm, with 800 eutectic tin lead bumps Wafers (melting point: 183 ° C, pitch: 0.25 mm), thickness: 0 mm, bonded in a matrix arrangement on a packaging substrate with an area of 35 mm x 3 mm and a thickness of 0.4 mm (FR-5 )on. In order to make the current even and uniform

H845twf .ptd Page 22 200423349 V. Description of the invention (16), and add aluminum wiring on the surface of the chip. The flip-chip bonding gap is 50 to 75 microns. The heat sink is made of a 25 mm x 25 mm copper plate with a thickness of 0.2 mm and is fixed on the packaging substrate with a commercially available heat-resistant adhesive. The copper plate is plated with nickel, and the reverse surface is roughened to improve the bonding strength. In the process of copper plate processing, in order to make the exposed portion 22 mm, in addition to applying twist processing, other processing is also performed at the same time so that the height of st a n d-〇 f f reaches 0 · 8 mm. Decompression transfer injection molding equipment is used for decompression transfer molding. The vacuum in the mold cavity is about 丨 mm-Hg. The sealing material uses CV8710F2 (the maximum particle diameter of the filler is 20 microns, the average particle diameter is 5 microns, the filler material is all silicon, and the thermal conductivity is 0.9 W / m-Kelvin temperature). A layer thickness of 0.8 mm and an area of 29 mm X 29 mm. Forming was performed at 160 ° C and 70 kg / cm² for 2 minutes, and then a post-curing process of 175 ° C and 4 hours was performed to obtain a device with a structure as shown in FIG. 4. From the cross-section of the device, the gap between the chip and the heat sink after the heat sink is installed is about 0.23 mm. [Example 2] Except that the stand-off height and package thickness of Example 1 were changed to 0.7 mm, everything else was the same, and the device as shown in Figure 4 was completed. [Example 3] Except that the thickness of the copper material in Example 2 was changed to 0 · 27 mm, everything else was the same, and the device as shown in Figure 4 was completed. 'From the perspective of the cross-section of the device, the gap between the chip and the heat sink after the heat sink is installed is about 0.6 mm. [Example 4] Except that the thickness of the copper material in Example 1 was changed to 0 · 15 mm, and the stand-off height and package thickness were changed to 0.9 mm.

11845twf.ptd Page 23 200423349 V. Description of the invention (17) --- The device as shown in Figure 4. From the cross-section of the device, the clearance of the heat sink is about 0.38 mm. The silly sun film / political heat film ΓΓΛΛΛ will be the same as in Example 1 & 50% of the packaging material is molten silicon, and the other 5nm). Mi-Kelvin Winnipeg. Of the device. Material used [Example 6] Except the packaging material of Example 1% Filling material maximum particle size Conduction system ϊ = 9 watts as shown in Figure ^. Use the material's heat Λ solid tile H ί change the packaging material of Example 2 to Example 5 The thermal conductivity is shown in Figure 2. Except for the material of Hung's temperature, the others are equal, and the result is ΪΪΐ4 [Example 8] Except that the packaging material of Example 2 is changed to the material with the 图 temperature of the example, all others are the same, so = ΐί4 on 3 ^ 9] will be The heat sink of Example 7 was changed to aluminum and twisted, and JL was sealed; the structure was as shown in FIG. 4. The exposed part is 22 in the same way as in Example 7. The material and stand are also the same as in Example 7, and are about 0.7 mm. Isolate from the bottom] Use the wafer, packaging substrate of Example 1 and commercially available liquids 12 filling materials (Panasonic Electric Co., Ltd. CV5183F), and use a dispensing equipment to encapsulate ′ = 2 = gap. The Japanese-style chip packaging structure obtained after the filler is cured under certain conditions is shown in Figure 2.

200423349 V. Explanation of the invention (18) [Comparative Example 2] On the wafer packaging structure of Comparative Example 1, ie, the structure shown in Figure 2, the mold and packaging material as in Example 1 are used and covered, and the resulting wafer package structure is shown in Figure 3. As shown. [Comparative Example 3] The device of Example 1 is the same except that the copper material for heat dissipation is not used. The obtained chip package structure is shown in FIG. The test results of the chip packaging structures of the above examples and comparative examples are shown in FIG. 9. The chip packaging process of the preferred embodiment of the present invention uses the technology disclosed in Japanese Patent J P 3 9 2 6 98 in 2001. However, the present invention optimizes the package size and provides a heat sink so that the chip package structure has the best package reliability and heat dissipation. In summary, according to the chip package structure of the preferred embodiment of the present invention, because it contains a heat sink and the chip is covered with the same material at one time, compared with the conventional chip package structure, it has lower warpage and reliability. High and highly heat dissipation effect. If a high thermal conductivity packaging material is used, the heat dissipation effect is better. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and retouching without departing from the spirit and scope of the present invention. The scope of protection shall be determined by the scope of the attached patent application.

11845twf.ptd Page 25 200423349 Brief description of the drawings $ 1 A, which is a cross-sectional view of a conventional chip packaging structure using a wire connection type. FIG. 1B is a cross-sectional view of a conventional wire packaging chip package structure with a heat sink attached. FIG. 2 is a cross-sectional view of a chip package structure using a conventional flip-chip bonding technology. Figures 3A and 3B are cross-sectional views of another conventional chip packaging structure using flip-chip bonding technology. FIG. 4 is a cross-sectional view of a chip package structure according to a first preferred embodiment of the present invention. 5 and 6 are cross-sectional views of a chip package structure according to a second preferred embodiment of the present invention. FIG. 7A is a cross-sectional view of a finished product of the chip packaging structure 'according to the preferred embodiment of the present invention after the chip packaging process is completed. FIG. 7B shows a cross-sectional view of a finished product of the chip packaging structure ′ according to a preferred embodiment of the present invention after the chip packaging process is cut. FIG. 8 is a cross-sectional view of a chip packaging structure forming a packaging material layer in a reduced-pressure transfer injection molding mold according to a preferred embodiment of the present invention. Fig. 9 shows the test results of the chip package structure according to a preferred embodiment of the present invention, a comparative example '. [Schematic description] U, 12, 40, 42, 44: Chip package structure

11845twf.ptd Page 26 200423349 Brief description of drawings 2 0, 50: Chip 22, 52: Active surface 2 4: Wire 3 0, 8 0: Carrier 3 2, 9 0: Solder ball 3 4, 7 0, 7 4: Encapsulation material layer 36: Heat sink 6 0: Bump 7 2: Top mold layer 1 0 0, 2 0 0: Chip package structure 140, 2 4 0: Heat sink 142, 242: Heat sink pin 1 5 0: Wafer 1 52: Active surface 1 6 0, 2 6 0: Bump 1 7 0, 2 7 0: Packaging material layer 1 8 0, 2 8 0: Carrier board 1 0 0, 2 9 0: Solder ball 195 295: Passive element 250a: First wafer 250b: Second wafer 250c: Third wafer 252a: First active surface 252b: Second active surface

11845twf.ptd Page 27 200423349 Brief description of the drawings 252c: the third active surface 2 5 4 b: the wire 2 5 6: the flip-chip bonding gap 260 a: the first bump 2 6 0 b: the second bump 3 0 0: Mold 3 1 0: Upper mold 3 2 0: Lower mold 330: Vacuum rubber seal ring 3 4 0: Mold cavity 3 5 0 ·· Injection line 3 6 0: Plunger 370: Vacuum line L: Cutting line

11845twf.ptd Page 28

Claims (1)

200423349 VI. Scope of patent application 1 · A chip packaging structure including at least: a carrier board; a chip having an active surface, the active surface is provided with a plurality of bumps, and the chip is oriented with the active surface facing the carrier board The flip chip is bonded to the carrier board and electrically connected to the carrier board; a heat sink is disposed on the wafer; and a packaging material layer is filled between the wafer and the carrier board and between the wafer and the carrier board Between the heat sinks, a surface of the heat sink away from the chip is at least partially exposed to the outside, and the packaging material layer is formed of a single packaging material. 2. 3mm0。 Between the chip packaging structure described in the scope of the patent application No. 1 wherein the distance between the chip and the heat sink is between 0. 0 3 ~ 0. 2 mm. 3. The chip package structure described in item 1 of the scope of patent application, wherein the thermal conductivity of the packaging material layer is greater than 1.2 Watt / meter-Kelvin temperature. 4. The chip packaging structure according to item 1 of the scope of patent application, wherein the material of the packaging material layer includes resin. 5. The chip package structure according to item 1 of the scope of patent application, wherein the material of the heat sink comprises metal. 6. The chip package structure described in item 1 of the scope of patent application, further including a plurality of solder balls arranged in an array, arranged on the surface of the carrier board away from the wafer. 7. The chip described in item 1 of the scope of patent application The packaging structure further includes at least one passive component disposed on the carrier board and electrically connected to the carrier board. 11845twf.ptd Page 29 200423349 6. Scope of Patent Application 8. The chip package structure described in item 1 of the scope of patent application, wherein the carrier board includes one of a packaging substrate and a lead frame. 9. A chip packaging structure, comprising at least: a carrier board; a chip set disposed on the carrier board and electrically connected to the carrier board, the chip set includes a plurality of wafers, and at least one of the wafers is overlaid A die is bonded on one of the carrier board and the wafers, and maintains a flip-chip bonding gap; a heat sink is disposed on the chipset; and a packaging material layer is filled in the flip-chip bonding gap and the Between the chipset and the heat sink, the surface of the heat sink away from the chipset is at least partially exposed to the outside world, and the packaging material layer is formed of a single packaging material. 03.0〜2 毫米 之间。 1 0. The chip package structure described in claim 9 of the scope of the patent application, wherein the distance between the chipset and the heat sink is between 0. 03 ~ 0. 2 mm. 1 1. The chip packaging structure described in item 9 of the scope of patent application, wherein the thermal conductivity of the packaging material layer is greater than 1.2 Watts / meter-Kelvin temperature. 1 2. The chip package structure according to item 9 of the scope of patent application, wherein the chip set includes at least: a first chip having a first active surface, and the first chip faces away from the first active surface The carrier board is disposed on the carrier board; and a second wafer having a second active surface, the second active surface is provided with a plurality of bumps, and the second wafer faces the second active surface toward the carrier. Flip chip bonding on the first wafer and electrically connected to the first wafer 11845twf.ptd Page 30 200423349 6. Scope of Patent Application For the first wafer, the bumps maintain the flip-chip bonding gap. 1 3. The chip package structure according to item 12 of the scope of patent application, wherein the chip set further includes a plurality of wires, and both ends of the wires are electrically connected to the second chip and the carrier board, respectively. 1 4. The chip package structure according to item 9 of the scope of the patent application, wherein the chip set includes at least a first chip having a first active surface, and the first active surface is provided with a plurality of first bumps. The first chip is bonded to the carrier board with the first active surface facing the carrier board, and is electrically connected to the carrier board; a second chip having a second active surface, the second chip The wafer is disposed on the first wafer with the second active surface facing away from the first wafer; and a third wafer having a third active surface with a plurality of second bumps disposed on the third active surface The third wafer is flip-chip bonded to the second wafer with the third active surface facing the second wafer, and is electrically connected to the second wafer, wherein the first bumps and the second wafers are electrically connected to the second wafer. The bumps maintain the flip-chip bonding gap. 15. The chip package structure according to item 14 of the scope of patent application, wherein the chip set further includes a plurality of wires, and both ends of the wires are electrically connected to the first chip and the carrier board, respectively. 1 6. The chip packaging structure according to item 9 of the scope of patent application, wherein the material of the packaging material layer includes resin. 1 7. The chip package structure described in item 9 of the scope of patent application, wherein 11845twf.ptd Page 31 200423349 6. Scope of Patent Application The material of the heat sink includes metal. 1 8. The chip package structure described in item 9 of the scope of the patent application, further comprising a plurality of arrayed solder balls arranged on the surface of the carrier board away from the chipset. 19. The chip package structure according to item 9 of the scope of patent application, further comprising at least one passive component, which is disposed on the carrier board and is electrically connected to the carrier board. 20. The chip packaging structure according to item 9 of the scope of patent application, wherein the carrier board includes one of a packaging substrate and a lead frame. 11845twf.ptd Page 32