200408983 玖、發明說明： 【發明所屬之技術領域】 本發明係關於一種進行元件佈局用之佈局設計裝置、 佈局設計方法及佈局設計程式。 【先前技術】 在半導體積體電路之佈局設計中，藉由將該半導體積 體電路中所含的半導體元件作成元件單元，且按照電路圖 製作包含該元件單元之區塊單元，即玎進行半導體積體電 路之佈局。 弟1 6圖係顯示典型的半導體積 圖。在步驟S 1 00之系統設計步驟中，可決定電路規格、 製程及晶片尺寸等的系統基本概念。在步驟s丨之電路 設計步驟中，進行具體的電路構成、各種常數之決^ 步驟Sl〇4之區塊單元佈局設計步驟中，對用於電二 -兀件進行元件單元之佈局，之後，組合該 進行區塊單元之佈局。在步驟川6之全體佈局設計中， 錯由適當地配置區塊單元即可進行積體電 在步驟S 1 08之罩幕產生步驟中，拍 且之佈局 而製作對應於製程的罩幕。在步驟7積體電路之佈局， 使用罩秦進行實際的製程，以f 乂钵中 在t、f厂诗蛋-& 、D +導體積體元件。 在上述&塊早兀佈局步驟 一面參考電路設計步驟S1G2中所得的丄佈局設計者’倍 用電腦輔助設計CAD等之圖面輪：:電路圖’而-面使 構成元件之電極、絕緣層' 摻雜區& /支裝置，並藉由輸, /才' 。°域等的座標以進行元, 315104 5 200408983 單元之佈局。 此時’為了減輕佈局設計者之負擔，而可利用所謂標 準方式的料方法。在標準方式中，#由事先將頻繁使用 之標準7L件單兀之佈局而保持於記憶裝置中當作庫存館 (library)，且按照需要而從庫存館中選擇元件單元即可進 行區塊單元之佈局(例如，日本專利特開平mm]號公 報）。 ----肌，视 【發明内容】 (發明所欲解決之問題） +然而，在被定制化（CUst〇merized)元件較多的類比積㉗ 书路％中，所使用之元件構成要素的大 、、且 變化較多，無法使元件單元之佈局 …’狀及配置之 一 T平兀之佈局標準化，而 凡庫存館。因1^，有需要針對元件單元之夂女 早 輪入座標貢料以進行元件單元之佈局。 资京逐 又，在組合元件單元以進行區塊單元 生需要變更元件單元之佈局本身的情況。更且 會發 什之修正等，亦會發生需要變更 目電路設 佈局設計者就有必要對 兀的情形。此時’ -貝料，而有使佈局作業變得越來越 ；再-人“座 亦恐有座標資料之輸入錯誤變高之虞；…問題。更且， 又，在包含電容元件或電阻元件之 路中’常有為了調整積體電路整 ;"牛早元的積體電 電容值或電阻值的情形 ^ 4間而需要微調 而要再次輪入電容元件或電 3)5]〇4 6 阻元件之各構成要素的座標。 者> ^ t 、在忒佾況，會有對佈局設計 者曰加負擔，且開發時間變長的問題。 又，在隨著電容值或電阻 帝阳；从 ^ 之彳放蜩而變更電容元件或 免阻凡件之構成的情況中，合 卞飞 分的罩幕均需要㈣^ 程中所用之幾乎大部 成本之增加。 十製程帶來报大影響，導致製造 与鄉“：路之全體佈局會隨著元件單元之調整而受到 更且'、：有發生需要再次重新進行佈局作業的情況。 輕易地確認其佈局結果之適或系統設計者無法 與佈局設計者之間，很難獲；此’在電路設計者 時間延遲的原因。 一计之契合，而造成使開發 本明係有#於上述先前技術之問題而研發者，其目 的在於提供可減輕元件佈 Θ作業負擔的佈局設計裝置、佈 局以方法及佈局設計程式，以解決上述問題之至少/ 個。 (解決問題之手段） 、為：解決上述問題，本發明提供—種佈局設計方法， 用以^丁電容元件之佈卩，其特徵為包含有：取得規定電 容兀：之最大電容值及修整電容值之參數的步驟；以及根 據規疋上述最大電容值參 ' 、 /款向决疋電谷兀件之基本構 成’且根據規定上述修替 正电谷值之芩數而變更上述基本構 成之電極有效面積，以進行電容元件之佈局的步驟。 為了解決上述問題’本發明的另—樣態提供一種佈局 315104 7 200408983 又十破置，用以進行電容元件之佈局，其 蒼數取得機構，用以取得規定電容元件之最大電=有· 正電容值之夂數.以B -烛_立 取大书各值及校 參數取〜 早70產生機構，根據規定上诚 "#機構所取#的上述最大電容值之參 元件^基本構成，且根據規定上述參數取得機構;=容 =述杈正電容值之參數而變更上述基本 ::： 積，以進行電容元件之佈局。 ^有效面 為了 ％決上述問題，本發明的另— 設計程式，用以+ 奴心拾供一種佈局 行包含有如：：：：：谷元件之佈局，其特徵為使電腦執 值及校正電理：取得規定電容元件之最大電容 容值之心：;ΐ:數的步驟；以及根據規定上述最大電 /數而決疋電容元件之其太 校正電容值之夫數 "· ，且根據規定上述 積，以^-ί k更上職本構成之電極有效面 以進仃電容元件之佈局的步驟。 【實施方式】 本發明實施形態之佈届^^ 其基本構成包含有：控制；二° :，係如第1圖所示， 記憶部]“ '、輸入部12、輸出部14、 . 及匯流排1 8。押制邱1 η 认 及記憶部16係介由匯流 排18而連接成可傳遞資訊。 又’遠佈局設計裝置 透過介面部20,而與外 二3有:1面部2〇為佳。藉由 即可從奸罟 ，、路22連接成可傳遞資訊， 衣之外部接受佈局設計所需要纟夹 & 將佈局設計之处果於屮u “要的茶數寺貧料，或 …果知出至裝置外部之電腦上。 控制部]〇藉由勃） 储存於記憶部]6内之佈局設計程 315104 8 而從輪入部12或介面部2。取得佈局 以進订元件單元内之佈局設計。 之多數 輸入部12係用於輪佑 之資料，係介由匯流排18^= 要的資料。所輸力 .以輪入部12而 傳輸至控㈣10或記憶部 裝置或滑鼠、光筆、軌二鍵盤等之字元輸" /軌跡球寻的指示裝置來使用較宜。 輸出。p 1 4係用以題干你你& 夫數笑 ‘·，、員不攸佈局結果或輸入部12取得的 二寺。以輸出部14而言，以適當 字機等輸出裝置來使用較宜。 .…印 部㈣用於儲存及保持控制部iG所執行之佈局 ==式或從輸人部12所輸人之參數值。記憶部16之記 内谷、，係可依控制部10而適當地參考。以記憶部“而 二可！當地選擇例如半導體記憶體、硬碟、軟碟、光磁 碟或磁帶等來使用。 以下，參考第2圖之流程圖來詳細說明本實施形態之 佈局設計方法。在本實施形態之佈局設計方法中，係自動 產生積體電路中所含之元件作為元件單元，且組合該元件 单兀以進行區塊單元之佈局。 佈局設計方法之各步驟，係被轉換成可由 程式並保存於記憶部16中。該程式係由控制部二= 並執行。 事先在步驟S 1 0 0之系統設計及步驟s 1 〇 2之電路設計 步蒼考第1 6圖）中所設計的電路資料，係從連接於匯流 排1 8之外部資料庫中叫出。 315104 9 200408983 , _〜，…队刁I，黾路資訊 所含之各元件型式及在步驟S100中所指定之製程規則 的類別資料。佈局設計者係從輸入部12指定電路圖之 部位。接受設計部位之指定控制部1〇，則判別設計部^ ^件型^且參考事切存於記憶部16内之基本構成資料 庫，而讀出所指定之元件基本構成資料。 例如’在積體電路中包含有卿 3〇的情況中，如第3圖所示 戰子… υ ϋ貝出關於射極32、基極 ^集極36、射極摻雜區域31、基極摻㈣域 摻雜區域35等的形狀、大+ 及木桎 _ , -置之預設值（基準值）。關 灸包圍電晶體30之元件隔離區域咖37 )吞 的預設值。在輸入其他元件 …貝出適當 式處理。 ……，亦可以同樣方 該等的基本構力，係按照決定# Μ斗卜斗处發〆 取J、表見、设計耐壓、 叹计性此寺母一設計規則（製程規了土 在反映_矜佟正笼、)之^別而事先準備。 保存共通部分，而按照設計規則僅 可事先 適當地變更及輸出。 、、“間之差異點部分 在步驟S12中，控制部1〇 而取得所需要的參數。控制$ 1〇 ^動產生兀件單元 部]6中之參數資料庫，而讀_“二7保存於記憶 設值，且顯示於輸出部】4上，而芬數之形式及預 之變更。在有必要變f eg _ .布局設計者催促參數值 綱者即脚：^ 出部】4上的參數值時，佈 p使用知入部】2來變更參數值。 315104 10 2UU408983 在此’所謂參數係指為了變更元件單元中所含之 的基本構成而所用者。又，表含 牛 值或電_以甘A ，數。3用^周整（修整）電容 值者亦甚適宜。關於修整之參數將於後述。 4圖：：二電Γ中使用雙載子電晶體30的情況，就如第 Q所不，進仃如下⑷至⑴之變更，⑷基準 (E—LENGTH :射極异痄、…-从砂長度 隔離區域(即並聯配置於元件 =ISC)37所包圍的區域内）的元件數（E—MULTI :並 外兀數）、（c)集極之有無（C一OFF)、⑷射極之數 (E—安NUM)、⑷集極之位置（c—p〇sm〇N)、⑺電極之重覆 圖术^射極個數E_ROW、基極個數B_R〇w、及電極順朴 之射 ' 、 ^ °又疋值仏經5又计規則所決定的最小 並聯元件數E—則⑶，係顯示在單元内並聯 有益二數的參數，其設定為1以上的整數。⑷集極之 …- ，係顯不有無設置集極的參數，其在設置有隹 :的情,係設定，，〇N"，而在未設置集極的情況則擇—地： 定”〇FF’’。⑷射極之數E_NUM，係顯示射極之數的參數： 為设疋在1以上之整數。（e)集極電極之位置 C—POSITION，係顯示將集極設在基極側、射極側或雙方 F個的參數’其設在基極側的情況係設定” Τ〇ρ η，咬 在射=的情況係設定，’bottom”，或設在雙方的情況係 擇一=疋”B0TH”。⑴電極之重覆圖案，係在串聯配置元 牛、’員不兒極之配置圖案的參數，其包含有射極朝串 聯方向的數（射極個數E—ROW)、基極朝串聯方向的數（基 315104 11 200408983 極個數B ROW)、及帝托，佑产 - 兒極順序。在射極朝串聯方向的數 E ROW及朝基極串躐古a & 一 爭％方向的數B-Row上設定！以上的敕 數。在電極順序上擇-設定” E/B”或” B/E，，。 正 在/驟S 1 4中，根據被輸入之參數值及設計規則，控 制部1 0會變更元件夕^ + 件之A極或摻雜區域之形狀、大小及配置 寺的基本構成，以自動產生元件單元。 例如’在雙載子電晶體中，根據⑷射極長度 E一職3TH、（b)並聯元件數E—則如、⑷集極之有無 (C_〇FF)、⑷射極之數（E—num)、⑷集極之位置 (C—POSITIQN)及（f)電極之重覆圖案（射極個數e讀基 T個數B_ROW、及電極順序)之設定而變更元件之基本構 成以產生元件單元。 ⑷根據射極長度毛LENGTH之值，變更膨2之長 度d。例如第4圓所示，若設定為射極長度e一遍刪〜 就如第5圖（a)所示，射極32之長度^ 4_。 ^ ’對應上述變更，其他的電極及摻雜區域之尺寸亦會變 在本例中，係顯不將金屬電極與射極摻雜區域 <歐姆接觸的接觸孔之部分當作射極32,且射極32之 、'及大小直接反映成射極摻雜區域之形狀及大小的情 :二：了控制’在射極摻雜區域31之形狀 '大小及配置、 -孟蜀電極作歐姆接觸用之接觸孔的形狀、大小及配置， :者均有需要個別控制的製程中，可依其意旨適當變更參 之值’可變更並聯配置200408983 (1) Description of the invention: [Technical field to which the invention belongs] The present invention relates to a layout design device, layout design method, and layout design program for component layout. [Previous technology] In the layout design of a semiconductor integrated circuit, a semiconductor unit included in the semiconductor integrated circuit is used as an element unit, and a block unit including the element unit is produced according to a circuit diagram, that is, a semiconductor integrated circuit is performed. Body circuit layout. Brother 16 shows a typical semiconductor plot. In the system design step of step S 100, the basic system concepts such as circuit specifications, process and chip size can be determined. In the circuit design step of step s 丨, the specific circuit configuration and various constants are determined. In the block unit layout design step of step S104, the element units for the electrical components are laid out. After that, Assemble the layout of the block units. In the overall layout design of step S6, it is possible to perform integrated power by properly disposing the block units. In the mask generating step of step S 108, the layout is photographed to produce a mask corresponding to the manufacturing process. In step 7, the layout of the integrated circuit is carried out using the cover Qin to carry out the actual process, and in the f bowl, the t- and f-factor poem- & and D + lead volume components are used. Refer to the circuit design step S1G2 for the above-mentioned & block early layout steps. 丄 The layout designer 'doubled the CAD wheel and other graphics wheels :: circuit diagram', and the electrodes and insulation layers of the components are used. Doped region & device, and by the input, / cai '. ° field and other coordinates for element layout, 315104 5 200408983. In this case, in order to reduce the burden on the layout designer, a so-called standard method can be used. In the standard way, # keep the frequently used standard 7L unit layout in memory as a library in advance, and select component units from the library to perform block units as needed Layout (for example, Japanese Patent Laid-Open No. mm). ---- Muscle, [Content of the Invention] (Problems to be Solved by the Invention) + However, among the analog product stacks with a lot of customized components, the components of the components used Large, and there are many changes, can not make the layout of the component unit ... 'The shape and configuration of one T-shaped layout is standardized, and the inventory hall. Because of 1 ^, there is a need for the maiden of the element unit to enter the coordinates early for the layout of the element unit. In the case of combining component units for block units, it is necessary to change the layout of the component units themselves. What's more, there will be corrections, etc., and there will be cases where it is necessary to change the layout of the target circuit, and it is necessary for the designer to take action. At this time, it may make the layout work more and more; again, there is a risk that the input error of the coordinate data may become higher; ... the problem. Moreover, it also includes a capacitive element or a resistor In the component road, there are often situations in which the integrated circuit's integrated capacitance or resistance value is adjusted in order to adjust the integrated circuit's capacitance value or resistance value. 4 6 Coordinates of each constituent element of the resistance element. ^ T, In the current situation, there will be a problem that the layout designer will be burdened and the development time will be longer. In addition, with the capacitance value or resistance In the case of changing the composition of capacitive elements or non-impedance components from the release of ^, the combination of flying points requires almost all of the cost increase in the process. Large impact, resulting in manufacturing and township: "The overall layout of the road will be changed with the adjustment of the component unit," ": There may be cases where the layout operation needs to be carried out again. Easily confirm the appropriateness of the layout result or the system designer cannot communicate with the layout designer, which is difficult to obtain; this is the reason for the delay of the circuit designer. A coincidence has led to the development of developers who have problems with the above-mentioned prior technologies. The purpose is to provide a layout design device, layout method and layout design program that can reduce the burden on component layout Θ. At least / of the above issues. (Means for solving problems) In order to solve the above-mentioned problems, the present invention provides a layout design method for arranging the layout of capacitive elements, which is characterized by including: obtaining the maximum capacitance value of the prescribed capacitance: and trimming the capacitance. Steps of the parameter of the value; and according to the above-mentioned maximum capacitance value, refer to the basic configuration of the electric valley element according to the above paragraph, and change the basic constitution of the electrode according to the above-mentioned number of the positive electric valley value. The effective area is used to perform the layout of the capacitor element. In order to solve the above-mentioned problem, another aspect of the present invention provides a layout 315104 7 200408983, which is also used for the layout of capacitive elements. Its number acquisition mechanism is used to obtain the maximum electric capacity of a specified capacitive element = Yes. Positive Capacitance of capacitor value. Take B-candle_stand to take the value and calibration parameters of the book ~ 70 early generation mechanism, according to the provisions of the above-mentioned "capacity taken #" above the maximum capacitance of the reference element ^ basic composition, And according to the provisions of the above-mentioned parameter acquisition mechanism; = capacity = the parameter of the positive capacitance value to change the above basic ::: product to perform the layout of the capacitive element. ^ Effective surface In order to solve the above problems, another design program of the present invention is designed to provide a layout line including: :::: Valley element layout, which is characterized by the computer's value and electrical calibration. : Obtain the heart of the specified maximum capacitance value of the capacitive element :; 数: the number of steps; and determine the value of the capacitor's too-corrected capacitance value according to the above-mentioned maximum electric / number, and according to the above provisions In order to improve the layout of the capacitive element, the effective surface of the electrode constituted by ^ -ίk is updated. [Embodiment] The basic structure of the embodiment of the present invention ^^ The basic structure includes: control; two ° :, as shown in Figure 1, the memory unit] "', the input unit 12, the output unit 14, and the confluence Row 1 8. Hold Qiu 1 η Recognition and memory 16 is connected to transfer information through bus 18. Also, the remote layout design device passes the interface 20, and has the outer 2 and 3: 1 face 2 0 is With this, you can connect the road 22 and the road 22 to transmit information, and the outside of the clothing can receive the layout design needed. The layout design should be done in the “The Chashu Temple, or … Go to a computer external to the device. The control section] 〇 The layout design process 315104 8 stored in the memory section] 6 from the turn-in section 12 or the interface section 2. Get Layout to customize the layout design within the component unit. The majority of the input section 12 is used for the data of Lunyou, and it is the data required by the bus 18 ^ =. The input force is transmitted to the control unit 10 or the memory unit by the turn-in unit 12 or a character input device such as a mouse, a light pen, a track two keyboard, and a trackball seeker pointing device for use. Output. p 1 4 is used to answer questions about you & husband laugh ‘·, the staff does not care about layout results or the second temple obtained by the input department 12. The output unit 14 is preferably used with an output device such as a suitable word machine. .. The print section is used to store and maintain the layout == formula or the parameter value input from the input section 12 by the control section iG. The notes of the memory section 16 Uchiya, can be appropriately referred to the control section 10. Use the memory part, but you can choose local memory such as semiconductor memory, hard disk, floppy disk, magneto-optical disk, or magnetic tape. The layout design method of this embodiment will be described in detail below with reference to the flowchart in FIG. 2. In the layout design method of this embodiment, the components contained in the integrated circuit are automatically generated as component units, and the component units are combined to layout the block units. Each step of the layout design method is converted into The program can be saved in the memory section 16. This program is executed by the control section II =. The system design in step S 1 0 and the circuit design in step s 1 002 are shown in Figure 16). The designed circuit data is called from an external database connected to the bus 18. 315104 9 200408983, _ ~, ... Team I, Kushiro Information contains each component type and the one specified in step S100. Category data of process rules. The layout designer specifies the location of the circuit diagram from the input section 12. The design control section 10 that accepts the design section determines the design section ^ ^ type ^ and the reference is stored in the memory section 16 The basic composition database is read out, and the basic composition data of the specified component is read out. For example, in the case where the integrated circuit includes Qing 30, as shown in Fig. 3, the warrior ... The shape of the base ^ collector 36, emitter-doped region 31, base-doped region doped region 35, etc., and the preset values (reference values) of the large + and wooden 桎,-. Moxibustion surrounds the transistor The component isolation area 30 (30) default value of swallowing. After inputting other components ... appropriate processing ...., the same basic structural force can also be used in accordance with the decision # Μ 斗 卜 斗 处Take J, manifestation, design pressure resistance, exclamation and other characteristics of this temple design rule (manufactured in the process to reflect the _ 矜 佟 Zheng cage,) ^ different and prepare in advance. Save the common parts, and according to the design rules only It can be appropriately changed and output in advance. In the step S12, the control unit 10 obtains required parameters in step S12. Control the $ 1〇 ^ movement to generate the parameter database in the unit unit] 6, and read _ "2 7 is stored in the memory settings and displayed on the output unit] 4, and the form and pre-change of the fen number. When it is necessary to change f eg _. The layout designer urges the parameter values, that is, the feet: ^ Out]], the parameter value is used to change the parameter value. 315104 10 2UU408983 Here, the so-called parameters Refers to those who are used to change the basic composition contained in the element unit. Also, the table contains the value of cattle or electricity_A. A. It is also appropriate to use ^ weekly trimming (trimming) capacitor value. About trimming The parameters will be described later. Fig. 4: The case of using the two-transistor transistor 30 in the second power Γ, as shown in Q, the following changes from ⑷ to ⑷, the reference (E-LENGTH: emitter pole difference) , ...- the number of components (E-MULTI: parallel number) from the sand-length isolation area (that is, arranged in parallel in the area surrounded by component = ISC) 37, (c) the presence or absence of the collector (C-OFF) , The number of ⑷ emitters (E-Ann NUM), the position of the ⑷ collector (c-p0sm0N), the repeated mapping of ⑺ electrodes ^ the number of emitters E_ROW, the base The number of poles B_R0w, and the electrode's smooth shot ', ^ °, and the value of the minimum number of parallel elements E determined by the rule of 5 and counting E—then ⑶, it is a parameter that shows that the parallel connection in the unit is beneficial. It is set to an integer of 1 or more. ⑷ Collector's ...-, it shows whether there is a parameter that sets the collector. It is set with 隹:, system settings, 〇N ", and when the collector is not set. Then choose-ground: Set "0FF". The number of emitters E_NUM is a parameter showing the number of emitters: is an integer set to 1 or more. (E) The position of the collector electrode, C-POSITION, shows the parameters for setting the collector on the base side, the emitter side, or both sides. 'The case where it is set on the base side is set.' Τ〇ρ η, bite In the case of shooting = set, 'bottom', or one of the two cases is set = 疋 "B0TH". The repeating pattern of the rhenium electrode is a parameter of the arrangement pattern of the tandem and 'memberless poles' in series, which includes the number of emitters facing the series (the number of emitters E-ROW), and the base facing the series. Number (base 315104 11 200408983 number of poles B ROW), and Tito, Yuchan-son pole order. Set the number E ROW in the emitter direction in series and the number B-Row in the% direction toward the base string! The above number. Select-set "E / B" or "B / E" on the electrode sequence. In / S14, according to the input parameter values and design rules, the control unit 10 will change the components. The basic structure of the shape, size, and configuration of the A pole or doped region to automatically generate the element unit. For example, 'in a bipolar transistor, 3TH according to the length of the ⑷emitter emitter E, (b) the number of parallel elements E -Then, such as, the presence or absence of a collector (C_〇FF), the number of emitters (E-num), the position of the collector (C-POSITIQN), and (f) the repeated pattern of the electrode (emitter The number e reads the base T number B_ROW and the electrode sequence) to change the basic structure of the element to generate the element unit. ⑷ According to the value of the emitter length hair LENGTH, change the length d of the expansion 2. For example, as shown in the fourth circle If it is set to delete the emitter length e once ~ As shown in Figure 5 (a), the length of the emitter 32 ^ 4_. ^ 'Corresponding to the above changes, the size of other electrodes and doped regions will also be changed in this example In the display, the part of the contact hole of the metal electrode and the emitter doped region < ohmic contact is not regarded as the emitter 32, and It directly reflects the shape and size of the doped region of the emitter: Second: The size and configuration of the 'shape of the doped region 31 in the emitter' are controlled, and the shape, size and Configuration: In the process that requires individual control, the value of the parameters can be appropriately changed according to its purpose. 'Parallel configuration can be changed
(b)根據並聯元件數E MULTI 3)5104 】2 200408983 於單元内之基本構成30的數。例如第4圖所示，在設定為 並聯元件E_MULTI = 2次的情況’就如第5 所示，在 由同一元件隔離區域IS037所圍住之區域内，將電晶體形 成並聯排列的配置。此時，同時變更射極長度E_LEN(}th 與並聯元件數E—MULTI ’亦可同時變更元件之尺寸及並聯 配置數。 ⑷根據集極之有無C_OFF之設^，可決定是否刪除 集極36。例如，在集極之有無c —〇打為”〇N,，的情況，就 如第5圖（c)所示，形成具備集極36的元件構成。另一方 面’在集極之有無C_OFF^，〇FF”的情況，就如第5圖⑷ 所示，形成集極36被刪除的構成。此時，集極之摻雜區域 3 5亦與集極3 6 —起被刪除。 (d)根據射極之數e—NUM之設定，可決定射極之 數。在射極之數E—NUM為2的情況，就如第5圖（e)所示， 變更成在圖示X方向將射極32形成2個的構成，即相對於 共通之基極#雜區域3 3而將射極摻雜區域3丨形成2個的 構成。同樣地，亦可對集極36或基極34設定參數，且變 更電極數。 (e)根據集極之位置C—P〇sm〇N之設定，可變更集極 36之位置。在集極之位置c—P〇SITI〇N為"τ〇ρ，，的情況， 就如第6圖（a)所示，集極36配置在基極34側。在集極 位置C—POSITION為”B〇TT〇M”的情況，就如第6圖⑻所 示，集極3 6配置在射極3 2側。又，在集極之位置 C—POSITION為’’BOTH”的情況，就如第6圖⑷所示，集極 315104 200408983 36配置在基極34及射極32之雙方側。此時，集極之摻雜 區域35的位置亦會隨同集極36變更。 ⑴根據包極之重覆圖案(射極個數E—R〇w、基極 B—謂、及電極順序），可以朝集極36、基極34及射極 32之串聯方向的配置圖案。例如，在射極個數E—R0W=2、 -u w 2及兒極順序=，’B/E，，的情況，就如第7 圖⑷所示，依集極36、第1基極34a1 i射極32a、第2 基極34b及第2射極32b之順序配置電極。在電極順序 = ’’e/b”的情況’就如第7圖(b)所示，依集極％、第：射極 32a、第i基極34a、第2射極⑽及第2基極3仆之順序 配置電極。在射極個數E_RQW與基極個數 相等的情況，例如，在射極個數一2及基極：：不 B—謂=3之情況’就如第7圖(c)所示，依集極％、第上 基極343、第1射極仏、第2基極糾、第2射極32b、 弟3基極34e之順序配置。反之，在射極個數£ 及基極個數B —R0W=2之情況’就如第7圖⑷所示，依集 極36、弟\射極323、第1基極仏、第2射極32b、第2 基極34b、第3基極34c之順序配置。此時，附隨各電極 雜區域31a、31b、31c、33之圖案，亦與各電極之圖 案變更同時作變更。 在此，雖舉雙載子電晶體為例而進行說明，但是即使 在其他的元件型式中’亦可同樣地按照參數之設定值變更 事先決定之元件的基本構成，以自動產生元件單元。 在步驟S16中，控制部10係將自動產生之元件單元 315104 ]4 顯示於輸出部14上 、 自佈局設計者輪人之^ΓΓ局設計者催促確認，且接受來 回到步驟Sl2,若貝讯，若在元件單元中有問題則 '又有問題則移行至步驟S 1 8處理。 在此，如第8图 - 元之產生結果-併g : ’设計規則及各參數值與元件單 就連系統設計者=:::宜。藉此’不僅有佈局設計者， -之產生的設計規則及各參數值之匹配性或妥當性广 , 為可在確認晝面上變更設計規則及各袁數 值，且依該變更而盅；太丄— ^级 一人生兀件單元並使之顯示。藉此， I 確認設計規及各參數值之變更與元件單元之產 生的關係，且可迅速地進行元件單元之產生。 產 在v驟S 1 8中，控制部i 〇係利用既有之c ad等編輯 工：：使佈局設計者在區塊單元内以手動或自動來佈局元 件單70例如，可利用使用數位轉換器（dizitizer)等之既有 的編輯工具。 在步‘ S20中，控制部i 0係將區塊單元之佈局結果 择貝不於輸出部i 4上，以催促佈局設計者輸入是否有必要變 更兀件單元之確認資訊。在佈局設計者需要變更元件單元 之情況，就使處理回到步驟S 12，而在不需要變更的情況， 就將處理移行至步驟S 2 2。 在步驟S22中，控制部10係使佈局設計者進行區塊 單元内之元件間的配線。例如，可使用具備袖珍工具 (compaction Tool)之既有的配線支援工具。又，亦可使用 自動配線工具。 15 315104 200408983 在步驟S24中，控制部10係對區塊單元之佈局及配 線之結果，使用既有之設計規則檢查（DRC)與自動校對驗 證（LVS)方法，並判斷區塊單元是否符合設計規則。若未適 合設計規則，就使處理回到步驟S18，若符合設計規則， 就結束區塊單元之佈局設計。 在積體電路包含有複數個區塊單元的情況，藉由重複 執行佈局方法，以進行必要的區塊單元之佈局。(b) According to the number of parallel elements E MULTI 3) 5104] 2 200408983 The number of 30 in the unit. For example, as shown in Fig. 4, when the parallel element E_MULTI = 2 times is set, as shown in Fig. 5, the transistors are arranged in parallel in an area surrounded by the same element isolation area IS037. At this time, you can change the emitter length E_LEN (} th and the number of parallel components E_MULTI 'at the same time. You can also change the size of the components and the number of parallel configurations at the same time. ⑷ According to the setting of the collector C_OFF ^, you can decide whether to delete the collector 36 For example, in the case of the presence or absence of a collector, "c-0" is "0N,", as shown in Fig. 5 (c), a component structure having a collector 36 is formed. On the other hand, 'is there a collector? In the case of C_OFF ^, 0FF ", as shown in Fig. 5 (a), the collector 36 is deleted. At this time, the doped region 35 of the collector is also deleted together with the collector 36. d) According to the setting of the number of emitters e-NUM, the number of emitters can be determined. When the number of emitters E-NUM is 2, as shown in Figure 5 (e), change to X in the figure The emitter 32 is formed in two directions in the direction, that is, the emitter doped region 3 is formed in two with respect to the common base #hetero region 3 3. Similarly, the collector 36 or the base may be formed. 34 Set the parameters and change the number of electrodes. (E) According to the setting of the position of the collector C-P0smON, the position of the collector 36 can be changed. At the position of the collector c-P0SITION In the case of τ〇ρ ,, as shown in FIG. 6 (a), the collector 36 is arranged on the base 34 side. When the collector position C_POSITION is "BOTTOM", As shown in FIG. 6 (a), the collector 36 is arranged on the emitter 32 side. Also, when the position of the collector C-POSITION is “BOTH”, as shown in FIG. 6 (a), the collector 315104 200408983 36 is arranged on both sides of the base 34 and the emitter 32. At this time, the position of the doped region 35 of the collector will also change with the collector 36. ⑴ According to the repeated pattern of the wrapper (number of emitters E- R0w, base B—predetermined, and electrode sequence) can be arranged in a series direction of the collector 36, base 34 and emitter 32. For example, the number of emitters E—R0W = 2, -uw In the case of the order of 2 and children =, 'B / E ,,' as shown in Fig. 7 (b), according to the collector 36, the first base 34a1, the i emitter 32a, the second base 34b, and the second emitter The electrodes are arranged in the order of 32b. In the case of the electrode sequence = "e / b", as shown in Fig. 7 (b), according to the collector%, the first: the emitter 32a, the i-th base 34a, and the second emitter The electrodes are arranged in the order of the pole and the second base electrode. When E_RQW is equal to the number of bases, for example, when the number of emitters is 2 and the base :: not B-predicate = 3 ', as shown in Fig. 7 (c), according to The upper base 343, the first emitter 仏, the second base correction, the second emitter 32b, and the third base 34e are arranged in order. On the contrary, the number of emitters £ and the number of bases B — R0W = 2 The situation is as shown in FIG. 7 (a), and is arranged in the order of the collector 36, the brother \ emitter 323, the first base electrode 仏, the second emitter 32b, the second base 34b, and the third base 34c. At this time, the patterns accompanying the electrode miscellaneous regions 31a, 31b, 31c, and 33 are also changed at the same time as the pattern of each electrode is changed. Here, although a description is given by taking a bipolar transistor as an example, even in other element types, the basic structure of a previously determined element can be similarly changed according to a parameter setting value to automatically generate an element unit. In step S16, the control unit 10 displays the automatically generated component unit 315104] 4 on the output unit 14, and the self-layout designer turns the person ^ ΓΓ. The designer urges confirmation, and accepts to return to step S12. If there is a problem in the element unit, then 'if there is a problem, go to step S 1 8 for processing. Here, as shown in Figure 8-the result of the generation-and g: ’design rules and parameters and components list even the system designer = ::: 宜. By this, not only the layout designer, but also the generated design rules and the wide compatibility or appropriateness of the various parameter values, so that the design rules and the values of the various yuans can be changed on the confirmation day, and based on the changes; too丄 — ^ grade one life piece unit and display it. With this, I confirms the relationship between the changes in design specifications and the values of various parameters and the generation of component units, and can quickly generate component units. Produced in step S 18, the control unit i 〇 uses the existing editors such as c ad :: enables the layout designer to manually or automatically lay out the component list 70 in the block unit. For example, digital conversion can be used. Editor (dizitizer) and other existing editing tools. In step ′ S20, the control unit i 0 selects the layout result of the block unit on the output unit i 4 to urge the layout designer to input confirmation information as to whether it is necessary to change the component unit. When the layout designer needs to change the element unit, the process is returned to step S12, and when it is not necessary to change, the process is shifted to step S2. In step S22, the control unit 10 causes the layout designer to perform wiring between the elements in the block unit. For example, you can use existing wiring support tools with compact tools. It is also possible to use an automatic wiring tool. 15 315104 200408983 In step S24, the control unit 10 uses the existing design rule check (DRC) and automatic proof verification (LVS) methods for the layout and wiring of the block units, and determines whether the block units meet the design rule. If the design rules are not met, the process is returned to step S18. If the design rules are met, the layout design of the block unit is ended. In the case where the integrated circuit includes a plurality of block units, the layout method is repeatedly performed to perform the necessary block unit layout.
如以上所述，依據本實施形態，則藉由根據設計規則 及參數來變更事先決定的元件之基本構成，料無須逐丄 輸入元件構成要素的座標資料，而自動產生元件單元。因 而，可減低佈局設計者必須輸入的資料量，且可減輕佈局 汉计之負擔。尤其是’如常規IC多的類比積體電路般报難 使單元標準化，且在無法利用單元庫存館之積體電路的係 局設計中很有效。 ％ 又由方、。又β十規則及各參數值可以與元件單元之產 結果-併以比較的態樣來顯示’戶斤以非為佈局設計之專= 的系統設計者或電路設計者亦可輕易地確認佈局設計之: 果，且可輕易地回授至系統設計或電路設計。 〜 <變化例1 > ‘小ty圔 電容兀件40之元件單元的自動產生加以說明。 在以下之說明中，主要係以進行電容值之微調的 進行說明，而就與上述實施形態同樣處理的步驟^數 明。 合况 3 】51〇4 16 200408983 在步驟S 1 0中，佈局設計者係指定電容元件40作為 元件型式。在此，形成具有金屬一氮化石夕膜一多晶石夕電極 之構造的Μ Ο S電容元件。具有設於底層之多晶石夕電極上 的絕緣膜上設有使多晶矽電極表面露出的開口部分，且氮 化矽膜被覆於開口部分，進而金屬電極被覆在氮化矽膜上 的構成。電容值係以上述開口部分之面積與氮化矽膜之膜 厚所決定。因而上述開口部分之面積會變成電容之有效面 積。 控制部1 0係接受以電容元件40為意旨之指定，而從 基本構成資料庫讀出電容元件4 0之基本構成的預設值。 在步驟S 1 2中，接受元件型式為電容元件40，而控制 部10係從參數資料庫讀出最大電容值（CMAX)、最大電極 寬度（WMAX)、最大電極長度（LMAX)、修正電容值（C)、 修整電極寬度（W)及修整電極長度（L)之預設值並顯示於輸 出部1 4上，以對佈局設計者催促變更參數值。 在此，使用關係式（1)及（2)，藉由輸入最大電容值 (CMAX)、最大電極寬度（WMAX)及最大電極長度（LMAX) 中之任2個值、以及修整電容值（C)、修整電極寬度（W)及 修整電極長度（L)中之任2個值，以自動地算出其餘的參數 值者較宜。 [數1]As described above, according to this embodiment, by changing the basic structure of a component determined in advance according to design rules and parameters, it is not necessary to input the coordinate data of component components one by one, and automatically generate a component unit. Therefore, the amount of data that a layout designer must enter can be reduced, and the burden of layout design can be reduced. In particular, 'it is difficult to standardize the unit as there are many analog integrated circuits like conventional ICs, and it is very effective in designing a system where integrated circuits of a cell library cannot be used. % By Fang. The β-ten rule and the values of various parameters can be compared with the production results of the component units-and displayed in a comparative form. The system designer or circuit designer who is specialized in layout design can easily confirm the layout design. The result: and can be easily fed back to system design or circuit design. ~ ≪ Modification 1 > ‘Small ty 圔 The automatic generation of the element unit of the capacitor element 40 will be described. In the following description, the fine adjustment of the capacitance value will be mainly described, and the steps of the same processing as in the above embodiment will be described. Case 3] 5104 16 200408983 In step S 10, the layout designer specifies the capacitive element 40 as the element type. Here, a MOS capacitor element having a structure of a metal-nitride film-polycrystalline oxide electrode is formed. The insulating film provided on the bottom polycrystalline silicon electrode is provided with an opening portion exposing the surface of the polycrystalline silicon electrode, a silicon nitride film is coated on the opening portion, and a metal electrode is coated on the silicon nitride film. The capacitance value is determined by the area of the opening and the thickness of the silicon nitride film. Therefore, the area of the opening portion becomes the effective area of the capacitor. The control unit 10 accepts the designation with the capacitor element 40 in mind, and reads the preset value of the basic structure of the capacitor element 40 from the basic structure database. In step S 12, the type of the receiving element is a capacitive element 40, and the control unit 10 reads the maximum capacitance value (CMAX), the maximum electrode width (WMAX), the maximum electrode length (LMAX), and the corrected capacitance value from the parameter database. (C), preset values of the trimming electrode width (W) and the trimming electrode length (L) are displayed on the output section 14 to urge the layout designer to change the parameter value. Here, the relational expressions (1) and (2) are used to input any two values of the maximum capacitance value (CMAX), the maximum electrode width (WMAX), and the maximum electrode length (LMAX), and the trimming capacitance value (C ), Any two values of the trimming electrode width (W) and the trimming electrode length (L), and it is better to automatically calculate the remaining parameter values. [Number 1]
CMAX ε·WMAX·LMAX - C:CMAX ε · WMAX · LMAX-C:
W · L (1) (2) 315104 465 200408983 其中： d :絕緣膜之厚度 ε :絕緣膜之介電常數。 例如，在對MOS電容元件，輸入最大電容值CMAX= 13.8pF、最大電極寬度WMAX=10 // m、修整電容值C = 6.9pF 及修整電極寬度W= 1 0 // m的情況，就變成最大電極長度 LMAX=10// m及修整電極長度L = 5/z m。另夕卜，上述之最 大電極長度LM AX及最大電極寬度WM AX，係意指上述電 容之有效面積部分的尺寸。 關係式（1)及（2)，係在電容元件具有平行電極之構成時 有效，而在具有溝渠型等複雜的構成時，從經驗式算出參 數者較佳。 在步驟S 1 4中，可根據參數值，自動產生電容元件之 元件單元。有箭根據多數等-------般性參數所進行的元件單元 自動產生部分將省略說明，而根據電容元件特有之參數所 進行的元件單元之產生加以詳細說明。 在修整電容值C與最大電容值CMAX為相等的情況， 就如第10圖（a)所示，以變成最大電容值CMAX的方式來 變更元件之基本構成各部的尺寸及配置。亦即，將氧化矽 膜上部電極之開口部分42的大小設為最大電極寬度 WMAX及最大電極長度LMAX，而其他的基本構成則配合 最大電極寬度WMAX及最大電極長度LMAX來變更。 另一方面，在修整電容值C與最大電容值CMAX為不 相等的情況，則如第10圖（b)所示，只變更開口部分42a 18 315104 200408983 二寸’以使電容元件變成修整電容值c。亦即，將門口 仏設為修整電極寬"及修整電 丄 :之：容“於係以氧切膜之開口部分的有效面：：: 外之構“會從相對於最大電:: 明，==!中，雖係就M0S構造之電容元件進行說 -疋就具有其他構成之電容元件而言亦可同樣處理。 口以上所述，藉由輸入修整電容值 修整電極長度作Λ灸奴 L正电極鬼度及 亡又作為芩數，即可只變更開口部份之 生具有所希望之電容值的。 、產 隨著命蹊μ呌 、 兀。因而，即使在電容值 〜二 變更而改變的情況，亦可-面將編整 幕二:…最終階段中所用之金屬電極進行開嘴^ 幕圖水之修正，即可對應佈局設計之變更。 <變化例2 > 阻要ΪΓ月：：施形態的變化例2參考第11圖，就包含電 要，τ'之兀件早兀的自動產生加以說明。 數為：以下之說明中，係以電阻元件之佈局中所固有的參 的ΐΓ'而進ί丁說明，而就進行與上述實施形態同樣處理 令V驟將省略說明。 在步驟S 1 0中，佈届今外去 帀乃汁者备、尨定電阻元件作為元件 / 制部10係接受電阻元件之意旨指定，而從基本構 成貝料庫中讀出電阻元件之基本構成的預設值。 在步驟SU巾’接受元件型式為電阻元件之情形，控 315104 19 200408983 制部1 0係從參數資料庫中讀出總電阻值（R)、單位電阻值 (RUNIT)、連接型式（RCONN)、並聯配置數（PARA_N)、串 聯配置數（SERI_N)、配線圖案之變更（ECO)及靜電破壞對 策之有無（ESD)的内定（defamlt)值，並顯示於輸出部14 上，以對佈局設計者催促參數值之變更。又，亦可與上述 實施形態同樣地進行基準部分之長度、並聯配置數、電極 之重覆圖案等參數的設定。 總電卩且值R係顯示元件單元中所含之電阻元件的總電 阻值之參數，且輸入0以上之值。該值能以電路圖中之1 個電阻元件的值而辨識。單位電阻值RUNIT係顯示分割元 件單元中所含之電阻元件的單位電阻5 2之每一電阻值的 參數。連接型式RCONN係顯示元件單元内之單位電阻52 之連接關係的參數，並擇一設定’’PARALLEL”、 ” PARALLEL_SERIAL”、"ZIGZAG，，或，，SERIAL” 中之任一 個。並聯配置數PARA—N，係顯示在元件單元内並聯配置 之單位電阻5 2之數的參數，其設定1以上的整數。串聯配 置數SERI_N，係顯示在元件單元内串聯配置之單位電阻 5 2之數的參數，其設定1以上的整數。配線圖案之變更 ECO，係在欲變更由連接型式RCONN而決定之元件單元 的構成來調整電阻值的情況所設的參數，其在進行調整的 情況係設定η〇ΝΠ，而在未進行調整的情況則設定為 ’’OFF’，。在該配線圖案之變更ECO中設定”〇Ν”白勺情況，就 有必要設定新的參數，而有關於此部分將於後述。靜電破 壞對策之有無ESD，係為了選擇通常之電阻要素54或絕 20 315104 200408983 緣耐性高之電阻要素5 4而用的參數，在高絕緣耐性之電阻 要素54的情況係設定η〇Νπ，而在通常之電阻要素54的情 況係設定"OFF”。 在上述中，在配線圖案之變更ECO為’’ON"的情況， 就進一步催促輸入修整並聯配置數（ECO_PARA_N)、修整 串聯配置數（EC〇_SERI_N)、修整連接型式 (EC〇_RC〇NN)。 該等參數，係用於變更一旦設定之單位電阻52之連接 關係的情況中。修整並聯配置數ECO—PARA—N，係指定在 變更配線圖案之情況並聯連接單位電阻52之數的參數，其 設定1以上的整數。修整串聯配置數EC〇_SERI_N，係指 定在變更配線圖案之情況串聯連接單位電阻5 2之數的參 數，其設定1以上的整數。修整連接型式EC〇_RC〇NN， 係顯示單元内之單位電阻52之連接的參數，並擇一設定 ”PARALLEL，，、，，PARALLEL_SERIAL”、"ZIGZAG”或 ’’SERIAL，，中之任一個。 在步驟S 14中，根據參數值，自動產生電阻元件之元 件單元。就根據多數等一般性參數所進行的元件單元之自 動產生將省略說明，而就根據電阻元件特有之參數所進行 的元件單元之產生加以詳細說明。 例如，在内定值中，總電阻值R與單位電阻值RUNIT 之值為相同的情況中，可決定單位電阻5 2之電極5 0間的 距離d，且產生由如第1 1圖所示之1個單位電阻5 2所構 成的元件單元。 上 ‘Ό 21 315104 ή C 7 200408983 薄片電阻值rs及摻 路的特性等中決 距離d係可從數學式（3)中導出。W · L (1) (2) 315104 465 200408983 where: d: thickness of the insulating film ε: dielectric constant of the insulating film. For example, when inputting the maximum capacitance value CMAX = 13.8pF, the maximum electrode width WMAX = 10 // m, the trimmed capacitance value C = 6.9pF, and the trimmed electrode width W = 1 0 // m for a MOS capacitor element, it becomes Maximum electrode length LMAX = 10 // m and trimming electrode length L = 5 / zm. In addition, the above-mentioned maximum electrode length LM AX and maximum electrode width WM AX mean the dimensions of the effective area portion of the capacitor. Relational expressions (1) and (2) are effective when the capacitor has a structure with parallel electrodes, and when it has a complicated structure such as a trench type, it is better to calculate the parameters from the empirical formula. In step S1, the element unit of the capacitive element may be automatically generated according to the parameter value. The automatic generation of the element units based on the general parameters such as the majority of the parameters will be omitted, and the generation of the element units based on the parameters specific to the capacitive element will be described in detail. When the trimming capacitance value C is equal to the maximum capacitance value CMAX, as shown in FIG. 10 (a), the size and arrangement of each component of the basic component of the element are changed in such a manner as to become the maximum capacitance value CMAX. That is, the size of the opening portion 42 of the upper electrode of the silicon oxide film is set to the maximum electrode width WMAX and the maximum electrode length LMAX, and other basic configurations are changed in accordance with the maximum electrode width WMAX and the maximum electrode length LMAX. On the other hand, when the trimming capacitance value C is not equal to the maximum capacitance value CMAX, as shown in FIG. 10 (b), only the opening portion 42a 18 315104 200408983 two inches' is changed so that the capacitance element becomes a trimming capacitance value. c. That is, the door opening is set to the trimming electrode width " and the trimming electrode ::: the effective surface of the "opening part of the oxygen cutting film :: external structure" will be compared with the maximum electric :: Ming In the case of == !, although the capacitor element with M0S structure is mentioned, the same can be done for capacitor elements with other structures. As mentioned above, by inputting the trimming capacitor value and trimming the electrode length as Λ moxibustion L positive electrode ghostness and death as the unit number, you can only change the opening to have the desired capacitance value. 、 产 With life 蹊 μ 呌, Wu Wu. Therefore, even in the case where the capacitance value is changed by ~ 2, you can edit the screen. 2: The metal electrode used in the final stage can be opened. ^ The screen water can be modified to correspond to the layout design change. < Modification 2 > Obstacles: 的 Modification 2 of the application form With reference to Fig. 11, the automatic generation of the components including electricity and τ 'will be described. The number is as follows: In the following description, description is made with reference to the parameters inherent in the layout of the resistive element, and the same processing as in the above embodiment is performed. Therefore, the description of step V will be omitted. In step S 10, the manufacturer of the present and the present, prepares a fixed resistance element as the element / system. The system 10 accepts the designation of the resistance element, and reads out the basic of the resistance element from the basic component shell. Composition of the preset value. In the case where the type of the receiving element is a resistive element, the control unit 315104 19 200408983 control unit 10 reads the total resistance value (R), unit resistance value (RUNIT), connection type (RCONN), The number of parallel configurations (PARA_N), series configurations (SERI_N), wiring pattern changes (ECO), and the presence or absence of electrostatic discharge countermeasures (ESD) are determined (defamlt) and displayed on the output section 14 to the layout designer. Urge changes in parameter values. The parameters such as the length of the reference portion, the number of parallel arrangements, and the overlapping pattern of the electrodes can be set in the same manner as in the above-mentioned embodiment. The total electrical resistance value R is a parameter showing the total resistance value of the resistance element included in the element unit, and a value of 0 or more is input. This value can be identified by the value of one resistance element in the circuit diagram. The unit resistance value RUNIT is a parameter showing each resistance value of the unit resistance 5 2 of the resistance element included in the divided element unit. The connection type RCONN is a parameter showing the connection relationship of the unit resistance 52 in the element unit, and one of them is set to ‘PARALLEL”, ”PARALLEL_SERIAL”, “ZIGZAG, or, SERIAL”. The number of parallel arrangement PARA-N is a parameter showing the number of unit resistances 5 and 2 arranged in parallel in the element unit, and it is set to an integer of 1 or more. The series arrangement number SERI_N is a parameter showing the number of unit resistances 5 and 2 arranged in series in the element unit, and it is set to an integer of 1 or more. Wiring pattern change ECO is a parameter that is set when the resistance value is adjusted by changing the structure of the element unit determined by the connection type RCONN. When adjustment is made, ηΝΠ is set. In this case, it is set to "OFF". When setting "ON" in the ECO for changing the wiring pattern, it is necessary to set new parameters, and this part will be described later. The presence or absence of ESD countermeasures against static electricity is a parameter used to select normal resistance elements 54 or 20 20 315104 200408983 resistance element 5 4 with high edge resistance. In the case of high insulation resistance resistance element 54, η〇Νπ is set, and In the case of the normal resistance element 54, "OFF" is set. In the above case, when the wiring pattern is changed to "ON", the number of trimming parallel arrangement (ECO_PARA_N) and trimming serial arrangement ( EC〇_SERI_N), trimming connection type (EC〇_RC〇NN). These parameters are used to change the connection relationship of the unit resistance 52 once set. The number of trimming parallel configuration ECO-PARA-N, is A parameter that specifies the number of unit resistors 52 connected in parallel when the wiring pattern is changed. It is an integer greater than 1. The number of trimmed series configuration EC0_SERI_N specifies the number of unit resistors 52 that are connected in series when the wiring pattern is changed. Parameter, which is set to an integer of 1 or more. Trimming the connection type EC0_RC〇NN is a parameter for the connection of the unit resistance 52 in the display unit, and select one of the settings "PARALLEL ,,,, PARALLEL_SERIAL ", " ZIGZAG" or '' in any of a SERIAL ,,. In step S14, the element unit of the resistance element is automatically generated according to the parameter value. The description of automatic generation of element units based on most general parameters will be omitted, and the generation of element units based on parameters specific to resistance elements will be described in detail. For example, in the case where the total resistance value R and the unit resistance value RUNIT are the same in the default value, the distance d between the electrodes 50 of the unit resistance 5 2 can be determined, and An element unit composed of one unit resistance 52. The above-mentioned distance d, such as the sheet resistance value rs and the characteristics of the doped circuit, can be derived from the mathematical formula (3).
層之寬度w係可從作為對象之積體電 定。 [數2] R= rThe width w of the layer can be electrically determined from the target product. [Number 2] R = r
(3) 在此，rs為薄片電阻值（Ω/[=]) 在單位電阻值RUNIT小於總電阻值 並聯配置數PARA N弋虫⑭ 的十月況’或在 、、兄，w : 並聯數SERI-N被指定的情 被指定之參數而產生複數個單位電阻52,且 決定該等的配置及配線之連接關係。 且可 例如’在連接型式⑽勝”parallelserial，，、 己置數PARA-㈣及串聯配置數咖—㈣的情況， 就12圖⑷所示，形成並聯配置3個單位電阻52而成 亚聯連接，進而串聯連接2個單位電阻U的構成。 、，在此，例如，若為連接型式RC〇NN = "pARALLELt，、 並聯配置數PARA,3，則如第12 _所示，成為並聯 配置3個單位電阻52而成並聯連接的構成。又，若為連接 垔式RCONN- ZIGZAG”、串聯配置數SERI—N；=3，則如第 2圖（c)所不，成為並聯配置3個單位電阻u而串聯連接 成曲折的構成。又，若為連接型式、串 聯配置數SERI，2，則如第12圖⑷所示，成為並聯配置 2個單位電阻52而作串聯連接的構成。同樣地，藉由變更 連接型式RCONN、並聯配置數pARA—N及串聯配置數 315104 22 200408983 SERI_N之值，即可適當地變更元件單元内之單位電阻的 連接。 又，根據靜電破壞對策之有無的設定，可變更單位電 阻52之電極50的尺寸。在靜電破壞對策之有無ESD = ’’ONM 的情況，就如第1 3圖所示，變更成將一方之電極5 0增大 至指定的尺寸並緩和電場集中的構成。此時，為了滿足設 計規則，而自動調整通常的電阻要素彼此間、靜電破壞對 策之電阻要素彼此間，即通常的電阻與靜電破壞對策之電 阻要素彼此間之間隔為較宜。 更且，若配線圖案之變更ECO設定為”〇N’’，則可進 行以修正總電阻值R為目的之元件單元54的修整。首先， 根據修整連接型式EC〇_RC〇NN、修整並聯配置數 EC〇__PARA_N及修整串聯配置數ECO__SERI_N之設定，來 變更單位電阻5 2彼此間之連接。亦即，單位電阻5 2之基 本的配置係依連接型式RCONN、並聯配置數PARA—N及 串聯配置數SERI_N來決定，且在保持該配置之狀態下直 接根據修整連接型式EC〇_RC〇NN、修整並聯配置數 ECO—PARA—N及修整串聯配置數ECO —SERI—N，而只變更 單位電阻52之連接關係。 例如，連接型式RCONN為”PARALLEL”、並聯配置數 PARA—N為5，如第14圖（a)所示，可產生5個單位電阻52 全部並聯之元件單元54。在修整連接型式ECO —RCONN設 定nPARALLEL_SERIALn、在子务整並聯配置數EC〇_PARA_ N設定2及在修整串聯配置數EC〇_SERI_N設定2的情 23 315104 200408983 況，就如第14圖(b)所示，可變更成並聯連接 電阻52，進而串聯連接有 個早位 牧旁2個早位電阻52之亓杜一 在第14圖（b)之例中，在#或c 件早7L 54。 、；例T係成為5個單位電阻中 。 電阻5 2 a並未被連接，而叮 個單位 木被運接，而可使電阻值達到總電 4:5。若增大單位電阻52之個數即總電阻值R之分= 小能調整之電阻值的值。藉由驅使該等盘串m 之組合，即可達成調整電路常數之電阻值修整:串亚： 於並非變更元件單元54 而且，由 在固定狀離下造〜 '貝本身，所以周邊之圖案係可 位電阻52% 阻值的修正，更且即使未被連接之單 、, &存圖案上，亦可藉由使全部單位電阻52 群組化而在電子資料上去 52 十田作1個電阻元件來處理。 除了以上所述，亦可具有能修正】個單位電 阻值本身的參數。此係 。 之％ 丁 J〜用固疋早位電阻52 修正電極50間之距離（1來達成。 大小，且 百先，除了上述參數，亦具有是否允許修正 間距離的開關USE、固定罝μ + 兒。 — 固疋早位電阻52之參 位電阻最大值RUNIT_MAX作為參數。 ^ •早 =位電阻最大值RUNIT—ΜΑχ與單位電阻值 Γ ，並不進行電極50間之距離“"周整。在單位 电阻值RUNIT小於單位雷p日m + & 早位 拉 早位电阻取大值RUNIT MAX的情況， 係可使用作為重新從數學式 — 〕[月况 的信…+ )中寺出電極50間之距離d 的值之早位電阻52來進行佈 ,_ 可 屯極5 〇間之路μ d及與其關連的電極 [數3] ㈠外之構成亚未被變更。 315104 24 200408983 (4) KUN I T_MAX: 例如，在設定單位電阻最大值RUNIT—ΜΑχ=6〇 Ω及單 位電阻值RUNIT = 50 Ω的情況，就如第！ 5圖所示，電極5〇 間之距離d可縮短成原來距離d之5/6來配置單位電阻 52。單位電阻52之面積由於係固定，所以不會隨著電阻值 修正（修整）而對周邊圖案造成影響。 如以上所述，藉由根據參數來決定電極間之連接，則 不用逐一輸入座標資料， _ 卞向了自動產生包含電阻元件之元 什旱元。 又，藉由 連接、電極間 單元。因而， 況，亦可一面 得必要的電阻 屬電極之罩幕 (發明效果） 依據本發 用進行繁雜的 局 〇 [圖式簡單說 第1圖係 可設定關於修整之參數，即可變更電極間 隔之長度，以自動產生變更電阻值後的元 即使在電阻值U電路設計之變更而改變的 將對佈局全體之影響抑制在最小限，一面 值。又’只要修正製程最終階段中使用的 圖案即可對應佈局設計之變更。 明’則在半導體積體電路之佈局設計中， 座標資料輸人，而可自動地進行元件之佈 明】 圖 本發明實施形態之佈局設計裝置的構成方: 第2圖係顯示本發明實施形態之佈局設計方法的流: 315104 25 200408983 圖。 第3圖（a)及（b)係本發明實施形態之電晶體的基本構 成例示圖。 第4圖係本發明實施形態之參數的設定輸入晝面示意 圖。 第5圖（a)至（e)係本發明實施形態之元件單元的自動 產生說明圖。 第6圖（a)至（c)係本發明實施形態之元件單元的自動 產生說明圖。 第7圖（a)至（d)係本發明實施形態之元件單元的自動 產生說明圖。 第8圖係本發明實施形態之元件單元之產生結果的顯 示晝面說明圖。 第9圖（a)及（b)係本發明變化例1之電容元件的基本構 成例示圖。 第10圖（a)及（b)係本發明變化例1之電容元件之元件 單元的自動產生說明圖。 第1 1圖（a)及（b)本發明變化例2之電阻元件的基本構 成例示圖。 第12圖（a)至（d)係本發明變化例2之電阻元件之元件 單元的自動產生說明圖。 第1 3圖係本發明變化例2之電阻元件之元件單元的自 動產生說明圖。 第14圖（a)及（b)係本發明變化例2之電阻元件之元件 26 315104 200408983 單元的自動產生說明圖。 第1 5圖係本發明變化例2之電阻元件之元件單元的自 動產生說明圖。 第1 6圖係顯示積體電路之佈局設計的流程圖。 10 控制部 12 輸入部 14 輸出部 16 記憶部 18 匯流排 20 介面部 22 網路 30 電晶體之基本構成 31 > 31a、 31b、 31c 射極摻雜區域 32、 32a、32b、32c 射極 33 基極摻雜區域 34、 34a、34b、34c 基極 35 集極摻雜區域 36 集極 40 電容元件 42 > 42a上部電極 50 電極 52、 52a單位電阻 54 電阻元件 27 315104(3) Here, rs is the sheet resistance value (Ω / [=]). In October, the unit configuration value RUNIT is less than the total resistance value, and the number of parallel configurations of PARA N is the number of parallel connections. SERI-N is specified, and a plurality of unit resistors 52 are generated according to the specified parameters, and determines the configuration and connection relationship of the wiring. For example, in the case of 'parallelserial' in the connection type, the number of PARA-㈣ and the number of coffee-㈣ arranged in series, as shown in Fig. 12, three unit resistors 52 are connected in parallel to form an Asian Union connection. , And further a configuration in which two unit resistors U are connected in series. Here, for example, if it is a connection type RC〇NN = " pARALLELt, and the number of parallel arrangements PARA, 3, it is a parallel arrangement as shown in Section 12_. Three unit resistors 52 are connected in parallel. If it is a connection type RCONN-ZIGZAG ", the number of serially arranged SERI-N; = 3, as shown in Figure 2 (c), three paralleled arrangements The unit resistance u is connected in series in a meandering configuration. In addition, if it is a connection type and the number of serially arranged SERI, 2, as shown in FIG. 12 (a), two unit resistors 52 are arranged in parallel and connected in series. Similarly, by changing the values of the connection type RCONN, the number of parallel arrangements pARA-N, and the number of serial arrangements 315104 22 200408983 SERI_N, the unit resistance connection in the element unit can be appropriately changed. In addition, the size of the electrode 50 of the unit resistor 52 can be changed according to the setting of the presence or absence of a countermeasure against static electricity. When ESD = 'ONM is present as a countermeasure against static electricity, as shown in FIG. 13, it is changed to a configuration in which one of the electrodes 50 is increased to a predetermined size and the electric field concentration is relaxed. In this case, in order to satisfy the design rule, it is preferable to automatically adjust the interval between the normal resistance elements and the resistance element of the electrostatic destruction countermeasure, that is, the interval between the normal resistance and the resistance element of the electrostatic destruction countermeasure. Furthermore, if the change of the wiring pattern ECO is set to "ON", the trimming of the element unit 54 for the purpose of correcting the total resistance value R can be performed. First, according to the trimming connection type EC0_RC〇NN, trimming in parallel The configuration number EC〇__PARA_N and the setting of the series configuration number ECO__SERI_N are used to change the connection between the unit resistances 52. That is, the basic configuration of the unit resistance 52 is based on the connection type RCONN, the parallel configuration number The number of series configuration SERI_N is determined, and in the state of maintaining this configuration, it is directly based on the trimming connection type EC0_RC〇NN, the number of trimming parallel configurations ECO-PARA-N, and the number of trimming serial configurations ECO-SERI-N, and only changes The connection relationship of the unit resistance 52. For example, the connection type RCONN is "PARALLEL", and the number of parallel arrangement PARA-N is 5, as shown in Fig. 14 (a), five element units 54 having all unit resistances 52 connected in parallel can be generated. Setting nPARALLEL_SERIALn in the trimming connection type ECO-RCONN, setting the number of parallel configuration EC0_PARA_N to 2 and setting the number of trimming series configuration EC0_SERI_N to 2 23 315104 200408983 As shown in Fig. 14 (b), it can be changed to a parallel connection resistor 52, and then two early resistors 52 are connected in series. In the example of Fig. 14 (b), # or c As early as 7L, 54 pieces. For example, the T series becomes 5 unit resistances. The resistance 5 2 a is not connected, but a unit of wood is connected, so that the resistance value can reach 4: 5. If it is increased The number of unit resistances 52 is the total resistance value R = the value of the small adjustable resistance value. By driving the combination of these disk strings m, the resistance value adjustment of the circuit constant can be achieved: string sub: Yu not Change the element unit 54. Also, it is made in a fixed shape ~ 'Bei itself, so the surrounding pattern is a correction of the potential resistance of 52%, and even if it is not connected to the unit, & It can be processed by grouping all the unit resistances 52 in the electronic data. 52. Juda as a resistance element. In addition to the above, it can also have parameters that can modify the unit resistance value itself. This series. % 丁 J ~ Correct the distance between the electrodes 50 (1 to achieve by using the solid early resistance 52. The size, and First of all, in addition to the above parameters, there is also a switch USE that allows the distance to be corrected, and fixed 罝 μ +. — Fix the maximum value of the parameter resistance RUNIT_MAX of the early resistance 52 as a parameter. ^ • early = maximum resistance of the resistance RUNIT — The distance between ΜΑχ and the unit resistance value Γ is not "rounded." When the unit resistance value RUNIT is less than the unit thunder m + m, & early pull early resistance takes a large value RUNIT MAX, It can be distributed by using the early resistance 52 which is the value of the distance d between the electrode 50 in the temple from the mathematical formula-] [letter of the month… +] The path between the electrode 50 and the μ μ The composition of the related electrode [Enum. 3] is unchanged. 315104 24 200408983 (4) KUN I T_MAX: For example, when setting the unit resistance maximum value RUNIT—ΜΑχ = 60 Ω and unit resistance value RUNIT = 50 Ω, just like the first! As shown in Fig. 5, the distance d between the electrodes 50 can be shortened to 5/6 of the original distance d to configure the unit resistance 52. Since the area of the unit resistance 52 is fixed, it does not affect the surrounding pattern as the resistance value is modified (trimmed). As described above, by determining the connection between the electrodes according to the parameters, it is not necessary to input the coordinate data one by one, and the _ 卞 direction automatically generates the element including the resistance element, and even the dry element. In addition, the connection and inter-electrode unit are provided. Therefore, it is also possible to obtain the necessary screen of the resistance-generating electrode (inventive effect). According to the present application, a complicated process can be performed. [The diagram is briefly described. The first picture can set parameters for trimming, and the electrode interval can be changed. The length of the element is automatically generated after the resistance value is changed. Even if the resistance value U circuit design is changed, the influence on the overall layout is suppressed to a minimum, a face value. Also, as long as the pattern used in the final stage of the process is modified, the layout design can be changed. Ming 'is used in the layout design of the semiconductor integrated circuit, the coordinate data is entered, and the components can be automatically specified. Figure 2 shows the layout of the layout design device according to the embodiment of the present invention. Figure 2 shows the embodiment of the present invention. The flow of the layout design method: 315104 25 200408983 Figure. Fig. 3 (a) and (b) are diagrams illustrating an example of a basic configuration of a transistor according to an embodiment of the present invention. Fig. 4 is a schematic diagram of the setting input of the parameters of the embodiment of the present invention. Figures 5 (a) to (e) are explanatory diagrams of automatic generation of element units according to the embodiment of the present invention. Figs. 6 (a) to (c) are explanatory diagrams of automatically generating a component unit according to an embodiment of the present invention. Figures 7 (a) to (d) are explanatory diagrams of automatic generation of element units according to the embodiment of the present invention. Fig. 8 is an explanatory diagram showing the day-to-day results of the generation of the element unit according to the embodiment of the present invention. Figures 9 (a) and (b) are diagrams illustrating the basic configuration of a capacitor element according to a first modification of the present invention. Figs. 10 (a) and (b) are explanatory diagrams of automatically generating element units of a capacitor element according to a first modification of the present invention. 11 (a) and (b) are diagrams illustrating an example of a basic configuration of a resistance element according to a second modification of the present invention. Figures 12 (a) to (d) are explanatory diagrams of automatic generation of the element unit of the resistance element according to the modification 2 of the present invention. Fig. 13 is an explanatory diagram of automatic generation of the element unit of the resistance element according to the second modification of the present invention. Figures 14 (a) and (b) are illustrations of automatic generation of the element of the resistive element according to the second modification of the present invention. Fig. 15 is an explanatory diagram of the automatic generation of the element unit of the resistance element according to the second modification of the present invention. Figure 16 is a flowchart showing the layout design of the integrated circuit. 10 Control section 12 Input section 14 Output section 16 Memory section 18 Bus 20 Interface surface 22 Network 30 Basic structure of transistor 31 &31; 31a, 31b, 31c Emitter doped regions 32, 32a, 32b, 32c Emitter 33 Base doped regions 34, 34a, 34b, 34c Base 35 collector doped regions 36 collector 40 Capacitive element 42 > 42a upper electrode 50 electrode 52, 52a unit resistance 54 resistive element 27 315104