TW200308096A - Insulation gate type semiconductor device - Google Patents

Abstract

The invention is primarily featured with providing high-speed performance for power MOSFET and having the capability of suppressing the switching noise. The solving means is to have the followings: plural p-base layers 12, which are selectively formed on the surface portion of n- drifting layer 11; n+ source layers 12, which are individually formed on each p-base layer 12; n+ drifting layers 15 formed on the backside of n- drifting layer 11; the drain 21 connected to n+ drain layer 15; plural sources 22 connected to p-base layer 12 and n<+ source layer 13; the gate 24, which is formed between the sources 22 through the gate insulation film 23; and the p layer 14, which is selectively formed on the surface portion of the n- drifting layer 11 located below the gate 24 and has impurity lower than that of p-base layer except the one connected to p-base layer 12.

Description

200308096 (1) Description of the invention [Technical field to which the invention belongs] The present invention relates to an insulated gate semiconductor device used for power control, and particularly to a switching power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) or MOS (Insulated Gate Bipolar Transistor) MOS gate element. [Prior Art] In order to miniaturize power supply circuits such as switching power supplies, the switching frequency can be increased. That is, it is possible to reduce the passive components such as inductance or capacitance in the power supply circuit. However, as the switching frequency is increased, the switching loss of switching elements such as MOSFETs or IGBTs increases. An increase in switching loss results in reduced power efficiency. Therefore, when the power supply circuit is miniaturized, it is indispensable to reduce the loss of the switching element by increasing the speed of the switching element. [Summary of the Invention] (Problems to be Solved by the Invention) MOSFETs, IGBTs, etc. that are currently used as switching elements The MOS gate element shortens the length of the gate, thereby reducing the area of the gate and the drain opposite to each other. In this way, the gate-drain capacitance can be reduced to achieve high-speed M0S gate devices. However, when the gate-drain capacitance is reduced in order to achieve high speed, a parasitic inductance in the wiring and the switching element capacitance will cause a total of -6-(2) (2) 200308096 vibration. This becomes a major cause of high-frequency noise (switching noise) during switching. In order to suppress such switching noise, it is necessary to perform a soft switch (soft switch). Either a filter circuit must be set up or the gate drive circuit must be improved. However, in order to suppress the switching noise, the cost will increase. As described above, in the past, users who have achieved high speed by reducing the gate-drain capacitance must suppress switching noise. Therefore, they have to perform soft switching or use external circuits such as filter circuits. Here, an object of the present invention is to provide an insulated gate type semiconductor device capable of suppressing switching noise at high speed without using an external circuit. (Means for Solving the Problems) In order to achieve the above-mentioned object, the insulated gate semiconductor device of the present invention is characterized by comprising: a first semiconductor layer of a first conductivity type; and selectively formed on the first of the first conductivity type. A plurality of second semiconductor layers of the second conductivity type on the surface portion of the semiconductor layer; a third semiconductor of the first conductivity type that is formed on at least one of the surface portions of the plurality of second conductivity types of the second semiconductor layer; Layers; a plurality of first main electrodes respectively connected to the plurality of second conductive layers of the second conductivity type and the at least one third conductive layer of the first conductivity type; formed on the first conductivity type (3) (3) 200308096 fourth semiconductor layer on the back side of the first semiconductor layer; a second main electrode connected to the fourth semiconductor layer; formed on the plurality of second conductive types via a gate insulating film A second semiconductor layer, a third semiconductor layer of the at least one first conductivity type, and a control electrode on each surface of the first semiconductor layer of the first conductivity type; and a first electrode of the first conductivity type provided above Semiconductor layer, and At least one of the second semiconductor layers of the second conductivity type is connected to the second semiconductor layer of the second conductivity type having a lower impurity concentration than the second semiconductor layer of the plurality of second conductivity types. Semiconductor layer. The insulated gate semiconductor device according to the present invention includes: a first semiconductor layer of a first conductivity type; and a plurality of selectively formed on a surface portion of the first semiconductor layer of the first conductivity type. A second semiconductor layer of the second conductivity type; a third semiconductor layer of the first conductivity type formed on at least one of the surface portions of the second semiconductor layer of the plurality of second conductivity types; a third semiconductor layer of the first conductivity type; A plurality of first main electrodes of the second semiconductor layer of the second conductivity type and the third semiconductor layer of the at least one first conductivity type; and formed on the back side of the first semiconductor layer of the first conductivity type A fourth semiconductor layer; a second main electrode connected to the fourth semiconductor layer; and a second -8-(4) (4) 200308096 semiconductor layer formed on the plurality of second conductivity types via a gate insulating film, The third semiconductor layer of the at least one first conductivity type, the control electrode on each surface of the first semiconductor layer of the first conductivity type, and the first semiconductor layer of the first conductivity type, and are connected to each other To the second half of the plurality of second conductivity types A fifth semiconductor layer of the second conductivity type having at least one of the conductive layers and a second conductivity type having a lower impurity concentration than the second semiconductor layer of the plurality of second conductivity types is applied with a voltage to the second main The capacitance between the control electrode and the second main electrode at the time of the electrode is configured to be reduced at a low voltage and constant or increased at a high voltage. The insulated gate semiconductor device according to the present invention includes: a first semiconductor layer of a first conductivity type; and a plurality of selectively formed on a surface portion of the first semiconductor layer of the first conductivity type. A second semiconductor layer of the second conductivity type; a third semiconductor layer of the first conductivity type formed on at least one of the surface portions of the second semiconductor layer of the plurality of second conductivity types; a third semiconductor layer of the first conductivity type; A plurality of first main electrodes of the second semiconductor layer of the second conductivity type and the third semiconductor layer of the at least one first conductivity type; and formed on the back side of the first semiconductor layer of the first conductivity type A fourth semiconductor layer; a second main electrode connected to the fourth semiconductor layer; and a second -9- (5) (5) 200308096 semiconductor layer formed on the plurality of second conductivity types via a gate insulating film, The third semiconductor layer of the at least one first conductivity type, the control electrode on each surface of the first semiconductor layer of the first conductivity type, and the first semiconductor layer of the first conductivity type, and are connected to each other To the second half of the plurality of second conductivity types When the voltage applied to the second main electrode is at least one of the bulk layers, and the fifth semiconductor layer of the second conductivity type has a lower impurity concentration than the second semiconductor layer of the plurality of second conductivity types, When W3 to 2/3 of the rated voltage ', then the capacitance between the control electrode and the second main electrode will start to increase. The insulated gate semiconductor device according to the present invention includes: a first semiconductor layer of a first conductivity type; and a plurality of selectively formed on a surface portion of the first semiconductor layer of the first conductivity type. A second semiconductor layer of the second conductivity type; a third semiconductor layer of the first conductivity type formed on at least one of the surface portions of the second semiconductor layer of the plurality of second conductivity types; a third semiconductor layer of the first conductivity type; A plurality of first main electrodes of the second semiconductor layer of the second conductivity type and the third semiconductor layer of the at least one first conductivity type; and formed on the back side of the first semiconductor layer of the first conductivity type A fourth semiconductor layer; a second main electrode connected to the fourth semiconductor layer; a second -10- (6) 200308096 semiconductor layer formed on the plurality of second conductivity types via a gate insulating film, at least one of the above The third semiconductor layer of the first conductivity type, and the control electrode on each surface of the first semiconductor layer of the first conductivity type, and the first semiconductor layer of the first conductivity type is provided and is connected to the plurality of 2nd semiconductor of 2nd conductivity type When the voltage applied to the second main electrode is at least one of the bulk layers, and the fifth semiconductor layer of the second conductivity type has a lower impurity concentration than the second semiconductor layer of the plurality of second conductivity types, When it is 1/3 to 2/3 of the rated voltage, the at least one fifth semiconductor layer of the second conductivity type is completely empty. The insulated gate semiconductor device according to the present invention includes: a first unit including at least: a plurality of first portions which are selectively formed on a surface portion of the first semiconductor layer of the first conductivity type; The second semiconductor layer of the second conductivity type is a third semiconductor layer of the first conductivity type formed on at least one of the surface portions of the plurality of second semiconductor layers of the second conductivity type, and a third semiconductor layer connected to the plurality of second conductivity layers. A plurality of first main electrodes of the second semiconductor layer of the second conductivity type and the third semiconductor layer of the at least one first conductivity type; and a second unit including at least: selectively formed on the first conductivity The second semiconductor layer of the second conductivity type on the surface portion of the first semiconductor layer of the semiconductor type is provided between the second semiconductor layer of the second conductivity type adjacent to the second semiconductor layer and has a plurality of The second semiconductor layer of the two conductivity type is a fifth semiconductor layer of the second conductivity type having a low impurity concentration. -11- (7) (7) 200308096 The insulated gate semiconductor device of the present invention is characterized by comprising: a first unit including at least: a first semiconductor selectively formed in a first conductivity type; The second semiconductor layer of the second conductivity type on the surface portion of the layer is a third semiconductor layer of the first conductivity type formed on at least one of the surface portions of the plurality of second semiconductor layers of the second conductivity type. And a plurality of first main electrodes connected to the second semiconductor layer of the plurality of second conductivity types and the third semiconductor layer of the at least one first conductivity type; A plurality of second semiconductor layers of the second conductivity type which are formed on the surface portion of the first semiconductor layer of the first conductivity type are provided between the second semiconductor layers of the second conductivity type adjacent to each other. And a fifth semiconductor layer of the second conductivity type having a lower impurity concentration than the second semiconductor layer of the plurality of second conductivity types, and the first semiconductor layer of the first conductivity type is provided with a The first semiconductor layer of the 1 conductivity type has the first conductivity of a high impurity concentration Type low-resistance layer, a first conductivity type having a lower impurity concentration than the low-resistance layer of the first conductivity type is provided between the second semiconductor layers of the second conductivity type adjacent to the first unit. 7th semiconductor layer. The insulated gate semiconductor device of the present invention includes: a first semiconductor layer of a first conductivity type; and a semiconductor layer provided on the first semiconductor layer of the first conductivity type. 8) (8) 200308096 The first semiconductor layer of the first conductivity type is a low-resistance layer of the first conductivity type having a high impurity concentration; and a large number of selectively formed on a surface portion of the low-resistance layer of the first conductivity type. Second semiconductor layers of the second conductivity type; third semiconductor layers of the first conductivity type formed on at least one of the surface portions of the plurality of second semiconductor layers of the second conductivity type; and third semiconductor layers of the first conductivity type; The plurality of second conductive layers of the second conductivity type and the plurality of first main electrodes of the at least one first conductivity type of the third semiconductor layer are formed on the back surface of the first conductivity type first semiconductor layer. A fourth semiconductor layer on the side; a second main electrode connected to the fourth semiconductor layer; a second semiconductor layer formed on the plurality of second conductivity types via a gate insulating film, and at least one of the first conductivity types The third semiconductor layer, and the above-mentioned first conductive layer The control electrodes on each surface of the low-resistance layer and the low-resistance layer provided on the first conductivity type are connected to adjacent second semiconductor layers of the second conductivity type, respectively, and have a plurality of The second-conductivity-type second semiconductor layer is a plurality of second-conductivity-type fifth semiconductor layers having a low impurity concentration. The low-resistance layer of the one conductivity type is a seventh semiconductor layer of the first conductivity type having a low impurity concentration. The insulated gate semiconductor device of the present invention is characterized in that: -13- (9) (9) 200308096 includes: a first semiconductor layer of a first conductivity type; and a first semiconductor layer of the first conductivity type A low-resistance layer of the first conductivity type having a higher impurity concentration than the first semiconductor layer of the first conductivity type; a plurality of selectively formed on a surface portion of the low-resistance layer of the first conductivity type; A second semiconductor layer of the second conductivity type; a third semiconductor layer of the first conductivity type formed on at least one of the surface portions of the plurality of second semiconductor layers of the second conductivity type; a third semiconductor layer of the first conductivity type; A plurality of first main electrodes of the second semiconductor layer of the second conductivity type and the third semiconductor layer of the at least one first conductivity type; and formed on the back surface side of the first semiconductor layer of the first conductivity type A fourth semiconductor layer; a second main electrode connected to the fourth semiconductor layer; a second semiconductor layer formed of the plurality of second conductivity types through a gate insulating film; and at least one of the first conductivity type A third semiconductor layer, and the first conductive layer Control electrodes and 9 on each surface of the low-resistance layer of the type are provided on the first semiconductor layer of the first conductivity type, and are connected to the second semiconductor layers of the plurality of second conductivity types, respectively, and have more than The second semiconductor layer of the second conductivity type is a fifth semiconductor layer of the second conductivity type having a low impurity concentration. According to the insulated gate semiconductor device of the present invention, by applying a high voltage of a certain range of 14- (10) 200308096 degrees, the fifth semiconductor layer of the second conductivity type can be made empty when it is turned off. This can suppress the rebound of the voltage at turnoff without compromising high-speed performance. [Embodiment] (First Embodiment) Fig. 1 shows a configuration example of a vertical power MOSFET of a first embodiment of the present invention. In FIG. 1, the drift layer 11 as the first semiconductor layer is provided with an η low-resistance layer 11a on one side (surface) by diffusion. On the surface portion of the η low-resistance layer 11a, a plurality of P base layers 12 as a second semiconductor layer are selectively formed by diffusion. Each p base layer 12 is arranged in a line shape in a first direction orthogonal to the front surface of the element. A plurality of n + source layers 13 as a third semiconductor layer are selectively formed on the surface of each P base layer 12 by diffusion. In addition, on the surface portion of the η low-resistance layer 1 1 a located between two adjacent P base layers 12, a P layer 14 as a fifth semiconductor layer is selectively formed by diffusion. In this embodiment, the P layers 14 are arranged in a line shape along the first direction of the P base layer 12 described above. In addition, it is connected to the p base layer 12 of one of the two adjacent P base layers. The p layer 14 is formed to have a lower impurity concentration than the P base layer 12 described above. On the other side (back surface) of the aforementioned ITO drift layer 11, an n + drain layer 15 is formed as a fourth semiconductor layer. A drain electrode 21 serving as a second main electrode is connected to the η + drain layer 115 'across the entire surface of -15- (11) (11) 200308096. On the other hand, the source electrode 22 as the first main electrode is formed on the p-type base layer 12 including a part of the n + source layer 13. Each source electrode 22 is arranged in a line shape in the first direction. Between the source electrodes 22, a gate electrode 24 is formed as a control electrode via a gate insulating film (for example, a silicon (s) oxide film) 23. That is, the gate electrode 24 having a planar structure is formed from the n + source layer 13 in one of the p base layers 12 through the η low-resistance layer 11a and the p layer 14. It reaches the area of the n + source layer 13 in another p base layer 12. The film thickness of the gate insulating film 23 is set to about 0.1 μm. Here, a substrate for forming the η_drift layer 11 and the η + drain layer 15 is formed by, for example, epitaxial growth. A substrate n in which an n − layer is formed on a low-resistance Si substrate, or a substrate in which an n + layer is formed on a Si substrate by diffusion. As described above, a P layer is hereinafter disposed on the surface portion of the η low-resistance layer 1 1 a below the gate 24 between the adjacent p base layers 12 (hereinafter referred to as the p-layer under the gate) 14. The p layer 14 has a lower impurity concentration than the p base layer 12 described above. The p-layer 14 is depleted when a high voltage is applied. This enables a high-speed and low-noise switching characteristic in the MOSFET. That is, a MOSFET having a structure related to this embodiment (hereinafter, simply referred to as the structure of this embodiment) uses a gate. Capacitance between the drains will increase according to the characteristics of the drain voltage to achieve high-speed and low-noise switching characteristics. 16- (12) (12) 200308096. The reason 2 is an explanation in which the dependence of the inter-electrode / drain-capacitance capacitance on the source-drain voltage in the MO SFET structured in this embodiment is compared with a conventionally constructed MOSFET (not shown). Illustration. As shown by the dotted line in FIG. 2, when the MOSFET (B) is a conventional structure, the capacitance between the gate and the drain continuously decreases in proportion to the voltage between the source and the drain. In contrast, as shown in FIG. 2, the gate-drain capacitance of the MOSFET (A) constructed in this embodiment increases when the source-drain voltage becomes high. That is, if the source-drain voltage is low, the gate-drain capacitance gradually decreases. In addition, as the source-drain voltage becomes high, the gate-drain capacitance increases. This is because the P layer 14 under the gate is depleted due to the increase in the voltage between the source and the drain (high drain voltage). Therefore, the appearance of the gate layer becomes longer as well as the gate length becomes longer. The opposing area of the gate electrode 24 and the drain electrode 21 will increase. Here, the switching speed of the MOSFET becomes faster as the gate-drain capacitance becomes smaller. However, when the capacitance of the MOSFET is completely OFF, the rebound voltage when the MOSFET is turned off will increase. Therefore, the capacitance of the MOSFET is finally small at the beginning of the OFF state, that is, in a state where the drain voltage is low, and at the end of the OFF state, that is, the capacitance is large at a state where the drain voltage is high. With a conventionally constructed MOSFET (B), the narrower the interval between the p base layers, the smaller the counter electrode between the gate and the drain becomes. In other words, the gate electrode -17- (13) (13) 200308096 decreases the capacitance between the drain electrodes. In addition, when a drain voltage is applied, an empty layer extending from the p base layer is extended. Therefore, the capacitance between the gate and the drain will decrease. In order to achieve high-speed and low-noise switching, a driver circuit is required. In addition, complicated control is required such that the gate current gradually decreases. As such, the MOSFET (A) structured in this embodiment uses a characteristic that a capacitance between a gate and a drain increases according to a drain voltage. That is, at the point when the MOSFET starts to turn off, the interval between the p-base layers 12 becomes narrower due to the lower drain voltage rather than depletion of the p-layer under the gate. In this way, the opposing area between the gate 24 and the drain 21 can be reduced, and the capacitance between the gate and the drain can be reduced. This can ensure high-speed switching characteristics. On the other hand, when the p-layer under the gate is depleted due to the high drain voltage at the time when the OFF is completed, the appearance of the P-base layer 12 becomes wider. This can suppress the rebound of the drain voltage and reduce switching noise. In this way, high-speed and low-noise switching characteristics are achieved without external circuits or complicated control. FIG. 3 is an explanatory diagram showing a comparison between a drain voltage (Vds) waveform and a drain current (Id) waveform of a MOSFET structured according to the present embodiment at the time of turning off and a conventionally constructed MOSFET. In the case of a conventionally constructed MOSFET (B), as described earlier, the switching characteristics are shortened and the speed is increased by shortening the gate length. As shown by the dotted line in FIG. 3, the bounce voltage (drain voltage Vds) at the time of OFF increases in proportion to it. After the drain voltage Vds also oscillates greatly, it is quite unstable. -18- (14) (14) 200308096 Compared to this, the mosfet (a) structure of this embodiment will reduce the gate-drain capacitance at low drain voltage, and at high drain voltage At this time, the capacitance between the gate and the drain becomes larger. Thereby, high-speed performance can be maintained, and the bounce voltage such as shown by the solid line in FIG. 3 will be less than half of the conventional case, and a switching characteristic in which the oscillation of the drain voltage Vds will also be suppressed. In the case of the MOSFET structured in this embodiment, as shown in FIG. 1, a structure in which the lower gate P layer 14 is provided on only one of two adjacent p base layers 12 is shown. In addition, it is not limited to this. For example, as shown in FIG. 4, a structure in which the p-layer 14 under the gate is respectively provided on two adjacent p-base layers 12 may be used. In addition, the gate P layer 14 is not limited to being formed shallower than the p base layer 12. That is, as long as the P layer 14 under the gate can be depleted due to the high drain voltage in operation. Therefore, the junction depth of the p-layer 14 under the gate can be the same as or deeper than that of the p-base layer 12. However, if the P layer 14 under the gate is formed shallow, the increase in the area of the opposing area of the gate 24 and the drain 21, which is actually effective when the P layer 14 is completely empty, will become larger. Therefore, the change in the capacitance between the gate and the drain compared to the increase in the drain voltage becomes larger, and a great effect of reducing noise is obtained. Therefore, the P layer 14 under the gate is preferably shallower than the p base layer 12. In the MOSFET structured in this embodiment shown in FIG. 1, the η low-resistance layer 1 1 a is provided to reduce the resistance between the adjacent p-base layers 12. That is, the η low-resistance layer 11 a is formed deeper than the P base layer 12. This can suppress the resistance from expanding from the narrow -19-(15) (15) 200308096 JFET (Junction FET) area supported by the p base layer 12 to the wide n-drift layer 11. In order to reduce the ON resistance, the η low-resistance layer 1 1 a may be formed shallower than the P base layer 12. As such, the η low-resistance layer 1 1 a does not directly affect the switching characteristics of high speed and low noise. Therefore, as shown in FIG. 5, the formation of the η low-resistance layer may be omitted (the MOSFET structured in this embodiment shown in FIG. 4 is also the same). Not only high-speed performance, but when ON resistance is also noticed, the capacitance that usually indicates high-speed performance is also proportional to area, while ON resistance is inversely proportional to area. Therefore, the so-called high speed and low ON resistance become a frade-off relationship. However, in the MOSFET structured in this embodiment, it is only necessary to slightly increase the channel resistance or the resistance in the FFET field, which can greatly increase the speed. This can improve the relationship between fred-off of high speed and low ON resistance. Therefore, a lower ON resistance can be set while maintaining the switching speed. Normally, the rated voltage (component withstand voltage) of the switching element can be selected from 1 to 5 times to 3 times the power supply voltage. Therefore, the voltage of the gate / drain capacitor relative to the power supply voltage should be large. That is, it is preferable that the switching element has a characteristic in which the capacitance between the gate and the drain starts to increase according to a voltage of 1/3 to 2/3 of the rated voltage. If the P layer 14 under the gate is completely empty, the area of the gate 24 and the drain 21 facing each other will increase greatly, and the capacitance between the gate and the drain will increase. Therefore, it is preferable that the p-layer 14 under the gate can be completely depleted according to a voltage of 1/3 to 2/3 of the rated voltage. -20- (16) (16) 200308096 In addition, when the p-layer 14 under the gate is completely empty, the capacitance between the gate and the drain increases (see Figure 2). However, when the capacitance between the gate and the drain has not increased, that is, when the capacitance no longer decreases to become a certain capacitance, or when the decrease in capacitance can be suppressed, the capacitance at the time of OFF is also more customary. The known MOSFET is large. Therefore, since the switching noise can be suppressed, the p-layer 14 under the gate may not be completely blanked, but may be partially blanked. Fig. 6 is an explanatory diagram showing a turn-off waveform of a MOSFET (A) structured in this embodiment and a turn-off waveform of a conventionally-configured MO SFET (B). In the state of low drain voltage, the gate-drain capacitance becomes smaller because of the p-layer 14, so it has a high-speed switching characteristic. On the other hand, in a state of high drain voltage, the p-layer 14 becomes empty. As a result, the gate length becomes longer and the gate-drain capacitance becomes larger. Therefore, the rebound voltage can be suppressed. As can be seen from Fig. 6, as the area of the p-layers 14 to be vacant between the p-base layers 12 under the gate 24 increases, the switching characteristics become faster. Fig. 7 is an explanatory diagram showing a change in turn-off loss (Eoff) when the area of the P layer 14 under the gate is changed in the MOSFET structured in this embodiment. In addition, the horizontal axis is the proportion of the p-layer 14 which is made empty with respect to the area between the p-base layers 12 under the gate 24. The vertical axis is the turn off loss in an induced load.

As shown in Fig. 7, when the area ratio 値 is more than 30%, it is estimated to contribute to high speed, and even the turn-off loss is higher than that of the conventional structure M0SFET -21-: (30%) (17) 200308096 (About 1.35mJ) is small. Therefore, it is preferable that the area ratio be a 値 larger than the 値. FIG. 8 is a diagram illustrating a change when the net doping amount (effective doping amount) of the P-layer 14 under the gate changes off in the MOSFET structured in this embodiment. The so-called net doping amount is not an actual ion fluence, but a carrier amount (concentration) corresponding to the part existing in the P layer 14, which is a subtraction between the p-type impurity and the existence between p3 The heterogeneity of the n-type heterogeneity. When the net doping amount is small, the effect of high speed is small because the P layer 14 is depleted due to low total ground void. When the net doping amount is as described above, the p-layer 14 is aged when a high voltage is applied, and the capacitance does not increase. In this case, since a high turn-off loss can be performed, the switching impurities become larger in the same manner as in a normal high-speed operation. Therefore, it is preferable that the P layer 14 is less than about 1 to 3.2 x 1012cnT2. When actually manufacturing the MOSFET, the respective low-resistance and dopants of the p-layer 14 under the gate are set to phosphorus (P),. At this time, the η low-resistance layer 1 a and the gate lower p layer 14 can be formed by simultaneous diffusion due to differences in the factors. Since the high-concentration η low-resistance layers 1 1 a and ρ layers 1 4 are not shown in FIG. 8, the net doping amount and the impurity amount of the actual ion implantation are not shown. The impurity amount of the ion implantation can be adjusted to be the most appropriate. Miscellaneous mass. In the case where the number of impurities in the g electrode layer 12 at the time of the turn is turned on, the voltage will be eliminated to a certain extent, and the speed do not become empty. The net doping amount layer 1 1 a often overlaps with boron (B) as the diffusion. Because of the same. As shown in the figure, the net doping amount is -22- (18) 200308096. Fig. 9 shows the distance Lj between the adjacent base layers 12 and the lower gate 14 effective for low noise in the MO SFET structured in this embodiment. An explanatory diagram of the relationship between the maximum net doping amount NpO. In addition, the case where the depth Xj of the P base layer 12 is set to 4 μm is shown. The maximum net doping amount NpO is a maximum net doping amount at which the gate layer 14 is depleted when a high voltage is applied. When it is larger than this, the P layer 14 under the gate will not be empty, and the gate capacitance will not increase, and noise will increase. Therefore, the net doping amount of the p-layer 14 under the gate is suppressed to the maximum below the maximum net doping amount NpO. As shown in FIG. 9, the maximum net doping amount NpO is approximately proportional to the distance Lj between the p groups 12. Therefore, the ratio of the maximum net doping amount N p 0 to the distance Lj between the electrode layers (NpO / Nj) is preferably set to 1 0 15 c πΓ 3 or less. Also, when the depth of the p base layer 12 becomes deeper, a drain voltage becomes applied to the p layer 14 under the gate and it becomes difficult to be depleted. Because the maximum net doping amount NpO will be inverse to the depth Xj of the ρ base layer 12 as shown in FIG. 9, when the depth Xj of the ρ base layer 12 is set to ', then the maximum net doping amount NpO and ρ base The ratio (Np0 / (Lj · Xj)) of the product of the depth Xj and the interval Lj of the layer 12 is preferably set below 1018cnT4. (Second Embodiment) FIG. 0 shows an example of a power MOSFET according to a second embodiment of the present invention. In addition, the same parts as the MOSFET shown in Figure 1

The PP layer here is P, so it is fortunate that the polar layer P group 2 X is difficult to add this, 〇 4 μιη and 5 X structure with the same symbol -23- (19) (19) 200308096, and its detailed Instructions. Only the different parts will be explained here. FIG. 10 illustrates a case where the formation of the η low-resistance layer is omitted. In FIG. 10, the p-layers 14 which are the fifth semiconductor layers have a structure embedded in the? -Drift layer 11 respectively. That is, in this embodiment, two of the p-layers 14 are disposed below each of the p-base layers 12 described above. In addition, the two p-layers are connected to two adjacent p-base layers 12 respectively. In addition, the respective p-layers 14 are arranged in a matrix shape along the first direction of the p-base layer 12. The p-layers 14 each have a lower impurity concentration than the p-base layers 12 described above. In the MOSFET structured in this embodiment, for example, the p-layer 14A is made empty by applying a high drain voltage similarly to the MOSFET structured as shown in FIG. In addition, the capacitance between the gate and the drain also increases due to the increase in the area where the gate 24 and the drain 21 face each other. This enables high-speed and low-noise switching characteristics. As described above, if the p-layer 14A is present between the gate 24 and the drain 21, the same effect as that in the case of the first embodiment described above can be obtained. Therefore, the p-layer that is depleted by the high drain voltage does not necessarily have to be formed on the surface of the ITO drift layer (or η low-resistance layer).

In the case of the MOSFET structured in this embodiment, the manufacturing process is somewhat more complicated than that of the MOSFET structured in FIG. That is, simply forming the ρ layer 14A inside the ITO drift layer 11 will cause the process to become complicated. However, the concentration point of the electric field when a high voltage is applied becomes closer to the bottom of the P base layer 12. And this point will increase its damage tolerance more than the MOSFET -24- (20) (20) 200308096 with the structure shown in Figure 1. (Third Embodiment) Fig. 11 shows a configuration example of a power MOSFET according to a third embodiment of the present invention. In addition, the same parts as those of the MOSFET shown in FIG. 1 are assigned the same reference numerals, and detailed descriptions thereof are omitted. In addition, only the different parts will be described here. Fig. 11 shows an example in which the formation of a low-resistance layer is omitted. In FIG. 11, a gate electrode 24a as a control electrode is buried in a surface portion of the n-drift layer 11 via a gate insulating film 23a. That is, in this embodiment, the gates 24a of a deep trench structure are provided in a line shape between two adjacent p base layers 12 of each other. A p-layer 14B as a fifth semiconductor layer is formed around the trench gate 24a. In addition, the p-layer 14B is connected to at least one of the p-layers 12. The p-layer 14B has a lower impurity concentration than each of the P-base layers 12 described above. For the MOSFET having the structure of this embodiment having such a deep trench gate 24a, the p-layer 14B does not become empty under the low drain voltage and remains. As a result, the capacitance between the gate and the drain becomes smaller, enabling high-speed switching. On the other hand, when a high drain voltage is applied, the p-layer 14B is depleted. As a result, the gate area in appearance will increase and the gate-drain capacitance will increase, so it will become a low noise, and it can realize a situation similar to a MOSFET with a gate with a planar structure as shown in Figure 1. About the same effect, that is, high-speed and low-noise switching characteristics. • 25 · (21) (21) 200308096 In addition, when the MOSFET is constructed in this embodiment, the ratio of the number of deep trench gates 24a surrounded by the P layer 14B and the area of the p layer 14B with respect to the deep trench gate 24a can be changed ratio. Thereby, in the MOSFET constructed as shown in Fig. 1, the same effect as that obtained when the area ratio of the p-layer is changed can be obtained. Further, as shown in FIG. 12, the P layer 14B / may be formed like a side wall and a bottom portion surrounding one side of the deep trench gate 24a. That is, the p-layer 14B / can be formed in addition to a part of the side wall of the deep trench gate 24a. In this case, since a channel through which no current flows at all is not made, a low ON resistance can be achieved. (Fourth Embodiment) Fig. 13 is a configuration example of a power MOSFET according to a fourth embodiment of the present invention. In addition, the same reference numerals are assigned to the same parts as those of the MOSFET shown in FIG. 1, and detailed descriptions thereof are omitted. Fig. 13 shows a case where an η low-resistance layer is formed. In Fig. 13, the gate electrode 24b as a control electrode has a split gate structure. In this embodiment, a lower gate p-layer 14 is formed on the surface of the η low-resistance layer 1 1 a as two fifth semiconductor layers. The two lower p-layers 14 are connected to the adjacent p-base layer 12. In addition, the P layer has a lower impurity concentration than each of the p base layers 12 described above. Generally, by setting the interpretation structure to a split interpretation structure, speeding up switching characteristics can be achieved by reducing the interpretation capacitance. Therefore, when the p-layer 14 under the gate is formed, high-speed switching characteristics can be achieved. -26- (22) (22) 200308096 In addition, in the process for manufacturing the MO SFET of this embodiment, the gate 24b (splitting) can be formed after the P layer 14 under the gate is formed. The gate electrode 24b is formed after the gate lower p layer 14 is formed on the entire surface of the η low-resistance layer 11a. Alternatively, the gate electrode 24b may be used as a mask to form the η low-resistance layer 11a (the p-layer 14 is divided). The gate structure is not limited to the gate electrode 24b of the above-mentioned divided structure. As shown in Fig. 14, a gate (control electrode) 24c of the structure can be explained using a terrain. At this time, approximately the same effect as that of the above-mentioned split gate structure can be obtained. (Fifth Embodiment) Fig. 15 is a configuration example of a power MOSFET according to a fifth embodiment of the present invention. In addition, the same reference numerals are assigned to the same parts as those of the MOSFET shown in FIG. 1, and detailed descriptions thereof are omitted. Fig. 15 shows an example in which a low-resistance layer is formed. In FIG. 15, a plurality of p base layers 12a as the second semiconductor layer are formed in a line shape in a first direction orthogonal to the front surface of the element. On the other hand, the plurality of lower gate p-layers 14 as the fifth semiconductor layer are formed in a line shape in a second direction orthogonal to each of the p-base layers 12 described above. According to the MOSFET structured in this embodiment, not only the same effect as that of the structure shown in Fig. 1 can be obtained, but also other effects can be expected. For example, there is no effect of misalignment, and a p-layer can be formed to be depleted. -27- (23) (23) 200308096 (Sixth Embodiment) Fig. 16 is a configuration example of a power MOSFET according to a sixth embodiment of the present invention. In addition, the same parts as those of the MOSFET shown in FIG. 1 are assigned the same reference numerals, and detailed descriptions thereof are omitted. In addition, FIG. 16 illustrates a case where an η low-resistance layer is formed. In FIG. 16, a plurality of p base layers 12a as the second semiconductor layer are arranged on the surface of the n low-resistance layer na in a lattice (or zigzag) manner. In addition, a plurality of lower gate p-layers 14a as the fifth semiconductor layer are arranged in a rectangular shape between four adjacent p-base layers 12a, respectively. Further, a plurality of Π + source layers 13a as the third semiconductor layer are formed in a ring shape on the surface portion of each of the p base layers 12a, and are respectively connected to the p base layer 12a and the n + source. A rectangular source electrode 22a is provided as a first main electrode at a corresponding portion of the electrode layer 13a. The gate electrode 24d as a control electrode is provided at a position other than the above-mentioned respective source electrodes 2 2a through the insulating film 23d. According to the MOSFET structured in this embodiment, approximately the same effects as those of the MOSFET structure shown in FIG. 1 can be obtained. Furthermore, since the electric field in the corners of each of the p base layers 12a is further alleviated, it is possible to suppress a decrease in withstand voltage. As shown in Fig. 16, the interval Wp between the adjacent lower p-layers 14a is set to be narrower than the interval Wj between the adjacent p-base layers 12a. As a result, the same effect as that obtained when the area of the? Base layer 12a is reduced is obtained. Thereby, the electric field combined between the P base layer 12a and the η low-resistance layer 11a can be relaxed, and a reduction in withstand voltage can be suppressed. This effect can be obtained even in a structure in which each p base layer 12 is formed in a line shape as shown in Fig. 15. Fig. 17 shows an example in which the arrangement of the p-layer 14a under the gate and the η low-resistance layer 11a are reversed in the power MOSFET having the structure shown in Fig. 16. That is, a plurality of p base layers i2a as the second semiconductor layer are arranged in a lattice (or zigzag) manner on the surface portion of the n low-resistance layer 11a. In addition, the p-layers 14 a below the gate, which are the fifth semiconductor layers, are each arranged in a rectangular shape between two adjacent p-base layers 12 a. Even with such a structure, the same effect as that of the MOSFET shown in FIG. 16 can be obtained. Fig. 18 shows an example when the P layer under the gate is arranged in a line shape in the power MOSFET having the structure shown in Fig. 16. That is, a plurality of p base layers 12 as the second semiconductor layer are arranged in a lattice (or zigzag) manner on the surface portion of the n low-resistance layer 11a. Further, a plurality of lower gate p-layers 14b as the fifth semiconductor layer are arranged in a line shape between adjacent P-base layers 12a. With this structure, the same effect as that of the MOSFET shown in FIG. 16 can be obtained. Fig. 19 to Fig. 21 are further examples of other configurations in the power MOSFET according to the sixth embodiment. FIG. 19 is an example of an arrangement pattern of the P layer under the gate when the p base layer is arranged in a lattice (or zigzag) shape. At this time, a plurality of p-layers 14c under the gate, which are a plurality of fifth semiconductor layers, are disposed on the p-base layer 12a as a fifth semiconductor layer, such as to surround a plurality of p-base layers 12a as -29- (25) (25) 200308096. Lines in one direction. Fig. 21 shows still another example of the arrangement pattern of the P layer under the gate when the p base layer is arranged in a lattice (or zigzag) pattern. At this time, the plurality of lower gate P layers 14c as the fifth semiconductor layer are arranged in a line shape in two directions as if the P base layers 12a as the second semiconductor layer are surrounded. As shown in FIGS. 19 to 21 respectively, the MOSFET of this embodiment can be easily realized regardless of the structure. (Seventh Embodiment) Fig. 22 shows a seventh embodiment of the present invention, and is an example when applied to an IGBT. In addition, the same parts as those of the MOSFET shown in FIG. 1 are assigned the same reference numerals, and detailed descriptions thereof are omitted. In addition, only the different parts will be explained. Fig. 22 is a table showing an example in which the formation of the? -Low-resistance layer is omitted. In FIG. 22, the IGBT (non-breakdown Non Punch Through structure) constructed in this embodiment has approximately the same structure as the MOSFET when the η low-resistance layer shown in FIG. 5 is omitted. That is, a plurality of p base layers 12 as the second semiconductor layer are selectively formed on one surface (surface) of the ITO drift layer 1 1 as the first semiconductor layer by diffusion. Each p base layer 12 is arranged in a line shape in a first direction facing inward from the front of the drawing. In addition, the η + source layer 13, which is at least one of the third semiconductor layers, is selectively formed on the surface portion of each p base layer 12 by -30- (26) 200308096. The p-layer 14 as the fifth semiconductor layer is selectively formed on the surface portion of the η-drift layer 11 between two adjacent p-base layers 12 by diffusion. In this embodiment, the p-layers 14 are arranged in a line shape in a first direction along the p-base layer 12. In addition, it is connected to the p-base layer 12 in one of two adjacent p-base layers 12. The p-layer 14 has a lower impurity concentration than the p-base layer 12 described above. On the other side (back surface) of the η-drift layer 11, a chirped drain layer 31 as a fourth semiconductor layer is formed. The drain 21 as the second main electrode is connected to the entire surface of the P + drain layer 31. On the other hand, a source 22 as a first main electrode is formed on each of the P base layers 12 including a part of the η + source layer 13. Each source electrode 22 is arranged in a line shape in the first direction. The gate electrode 24, which is a control electrode, is formed between the source electrodes 22 through the insulating film 23. That is, the gate electrode 24 having a planar structure is formed in the η + source layer 13 in the ρ base layer 12 from one of them, and reaches the other via the η-drift layer 11 and the ρ layer 14. In the above-mentioned ρ base layer 12 within the above-mentioned η + source layer 13. The gate insulating film 23 has a film thickness of about 0.1 μm. As such, in the IGBT structured in this embodiment, the portion of the n + drift layer 15 in the MOSFET is composed of the P + drain layer 31. This allows it to operate as an IGBT. In general, if it is a MOS device, its switching characteristics are roughly -31-(27) (27) 200308096 is determined based on the capacitance determined by the MOS device structure. Therefore, for the IGBT, the MOS structure of this embodiment is effective. In addition, the IGBT is not limited to a non-punch through structure, as shown in FIG. 23, and can also be applied to an IGBT with a punch through structure. In the case of an IGBT having a punch-through structure, an 11+ buffer layer 32 as a sixth semiconductor layer is provided between the ITO drift layer Π and the P + drain layer 31. Fig. 24 shows still another example of the IGBT according to the seventh embodiment of the present invention. In addition, the same parts as those of the IGBT shown in FIG. 23 are assigned the same reference numerals, and detailed descriptions thereof are omitted. Only the different parts will be explained here. In addition, FIG. 20 shows a case where an η low-resistance layer is formed. Furthermore, this is an example when applied to an IGBT of a punch-through structure. As shown in FIG. 24, the IGBT has a dummy cell (second cell) 41 in which a part of a source contact (source 22A) is thinned out. The modulation of the conductivity of the η-drift layer 1 1 can be enhanced by performing thinning on the source contacts. In the IGBT having this structure, the dummy cell 41 is formed with a lower gate p layer 14d as a fifth semiconductor layer. At this time, the p-layer 14d is formed so as to completely cover the surface portion of the? -Low-resistance layer 11a. On the other hand, in the normal cell (the first cell) 42 where the source contact (source 22) is usually formed on both sides, the lower gate p layer 14d is not formed. Therefore, at low drain voltages, the gate-drain capacitance becomes smaller and high-speed switching is possible, while at high drain voltages, the gate-drain capacitance increases and becomes a low-switching noise. -32- (28) 200308096 In addition, the IGBT structured in this embodiment is not limited to a planar MOS structure as shown in Figs. 22 to 24, and can be similarly implemented in a trench MOS structure. (Eighth Embodiment) Fig. 25 is an example of a power MOSFET according to an eighth embodiment of the present invention. In addition, the same parts as those of the IGBT shown in FIG. 24 are assigned the same reference numerals, and detailed descriptions thereof are omitted. In addition, only the parts that are not described will be explained. FIG. 25 is a case where the η low-resistance layer is formed. As shown in FIG. 25, the MOSFET is a MOS cell (second cell) 5 having a p-layer 14d under the gate as a fifth conductor layer. 5] A cell structure mixed with a MOS cell (first cell) in which the p-layer 14d under the gate is not formed. The p-layer 14d under the gate is formed, for example, by completely covering the surface portion of the low-resistance layer 11a. In the MOSFET structured in this embodiment, the density (number) of the MOS cells 51 provided with the p-layer 14d under the gate is changed. In this way, the same effect as that obtained when the area ratio of the p-layer 14d under the gate is changed can be obtained. That is, the ratio of the number of cells 51 to the number of cells 5] 52 in the entire device is equivalent to the product ratio of the p-layers 14 under the gate shown in FIG. In addition, compared with the IGBT (see FIG. 24) that implements the inter-distribution of the source contacts described above, the manufacturing process can be simplified and the manufacturing is very advantageous. Here, the pole 24 in the MOS cell 52 that is not inserted into the p-layer below the gate is set to a split structure, and the deep structure with the p-layer 14d below the gate inserted is added to the Λ plane of the same half-52 covered electrode -33- (29) 200308096 The gate 24 in the MO S unit 51 is provided in a usual structure. Therefore, when the voltage is applied, since the capacitance is determined according to the area of the MOS cell 52, the capacitance between the gate and the drain becomes small and becomes high speed. On the other hand, when the voltage is high, the area of the gate 24 of the MOS cell 51 becomes large and a noise is low. In addition, the lower gate P layer 14d does not necessarily completely cover the surface portion of the n low layer 11a. The same effect can be obtained even in a structure in which the surface portion of the η low-resistance layer 11a partially covers the under-gate P layer 14d. In addition, the most important thing is to design the element according to the ratio of the total area of the element to the gate product (such as the surface area of the η low-resistance layer 1 1 a). . Furthermore, it is not limited to the MOSFET, as shown in FIG. 26, it can also be applied to an IGBT with a breakdown structure (or a non-breakdown IGBT (not shown)). (Ninth Embodiment) Fig. 27 is an example of a power MOSFET according to a ninth embodiment of the present invention. In addition, the same reference numerals are given to the same parts as those of the MOSFET shown in FIG. 25, and detailed descriptions thereof are omitted. Only a part of the explanation will be given here. In the MOSFET structured in this embodiment, as shown in FIG. 27, each of the cells (first cell) 51a provided with the p-layer 14d under the gate as the fifth semiconductor layer does not have the electrode layer 1 as the third semiconductor layer. . Low power is due to the effect of the resistance set. The structure of the sample structure shows that the MOS n + source -34- (30) (30) 200308096 can increase the damage tolerance of the MO SFET in this structure. That is, since there is no path through which electrons flow even when a voltage is applied to the gate electrode 24, it does not operate. In other words, the MOS unit 51a only has a function of increasing the capacitance between the gate and the drain when the drain voltage is high. Therefore, even if the n + source layer 13 is removed, the ON resistance is not affected. Since there is no n + source layer 13, no parasitic dual-port transistor exists in the MOS cell 51a. Therefore, even in the case where avalanche drops occur when a high voltage is applied, the generated holes can be quickly discharged. This not only enables high-speed and low-noise switching characteristics, but also improves avalanche tolerance. In addition, in the MOSFET shown in FIG. 27, the gate lengths of the MOS cell 52 and the MOS cell 51a are set to the same length. In contrast, as shown in FIG. 28, the gate length of the gate 24B of the MOS unit 51b is increased, and the gate length of the spring 24A of the MOS unit 52a is shortened. With this, the effect of high-speed and low-switching noise becomes stronger. That is, at a low voltage, only the gate capacitance of the MOS cell 52a becomes the gate capacitance of the entire device. Therefore, by shortening the gate length of the MOS cell 52a, a high speed can be achieved. At high voltage, the p-layer 14d under the gate becomes empty. Therefore, the gate capacitance of the MOS cell 51b is added to the gate capacitance of the MOS cell 52a. For example, by increasing the gate length of the MOS cell 5 1 b, the increase in the gate capacitance can be increased, and as a result, the switching noise can be greatly reduced. (10th embodiment) -35 · (31) 200308096 Here, the impurity amount of the p-layer below the gate will be described in more detail. Here, the MOSFET structure shown in FIG. 1 is taken as an example for explanation. In the MOSFET of the first embodiment, the capacitance between the gate and the drain changes due to the emptying of the P layer 14 under the gate. This is helpful for high speed and low noise of MOSFET. Therefore, the p-layer 14 under the gate must have a sufficient amount of impurities to cause emptying when a high drain voltage is applied. As such, the maximum amount of impurities present in the p-layer 14 under the gate is the limit for the generation of depletion. The maximum impurity level of the P layer 14 under the gate is determined according to the degree of depletion of the p layer 14 under the gate. The degree of emptying is affected by the magnitude of the electric field applied to the P layer 14 under the gate. That is, the maximum impurity amount of the p-layer 14 under the gate is related to the size of each part of the MOSFET or the concentration of each part. Specifically, it is related to the size of the p-layer 14 under the gate, the interval (distance) of the p-base layer 12, the concentration of the η low-resistance layer 11a, the depth of the p-base layer 12, and the like. Therefore, under the design gate! The most important factor for the impurity level of the three layers 14 is the size and concentration of each part of the MOSFET. The n low-resistance layer 11a has a higher impurity concentration than the n_drift layer 11a. In the case of the MOSFET shown in Fig. 1, the lower gate p-layer 14 is formed on the same surface as the η low-resistance layer 11a. Therefore, the impurity amount of the p-layer 14 under the gate must be reviewed based on the net doping amount. The so-called net doping amount is an amount obtained by subtracting an n-type impurity amount from a p-type impurity amount corresponding to the amount of a positive hole. In the following description, the impurity amount of the p-layer 14 under the gate indicates the net doping amount of the p-layer 14 under the gate -36- (32) 200308096. The unit of the impurity mass is the concentration per unit area where the concentration is integrated in the depth direction (Cm FIG. 29 shows the size (area ratio Ap) of the gate 14 in the MOSFET of the first embodiment and the P-layer 14 under the gate. An explanatory diagram of the relationship of the maximum NpO. However, the case where the doping amount (Nn) of n 11a is set to 4xl012cm_2 and the p base spacer (Lj) is set to 6 μm is shown here. The so-called P layer under the gate The area ratio Ap (Apl + Ap2) of 14 refers to the ratio of the area (Apl + Ap2) of the P layer 14 under the gate to the area (Apl + Ap2) between the electrode layers 12. As shown in Figure 1, When the electrode layers 1 2 and η + the source layer 1 3 ′ form a line shape with the P layer 14, the area between the P base layers 12 and the interval Lj between the base layers 12 are proportional. Similarly, the P area under the gate is similar. It is approximately proportional to the length Lgp of the p-layer 14 under the pole. The area ratio Ap of the p-layer 14 under the pole can be equal to the ratio of the length Lgp of the p-layer 14 under the gate (Ap = Lgp). / Lj). As shown in Figure 29, the maximum net doping of the p-layer 14 under the gate is approximately the inverse of the area ratio Ap with the p-layer 14 under the gate, which changes the area of the p-layer 14 under the gate. , You can generate the gate The total net doping amount Np of the P layer 14 does not include the amount of impurity Np per unit area. Therefore, as the area of the gate electrode becomes larger, the net doping amount Np also becomes smaller. If the area ratio of the p layer 14 under the gate is the inverse of Ap (the relationship between the maximum net doping amount NpO is expressed by a first-order approximation using the impurity • 2). The P layer under the electrode is a large net doped low-resistance layer 1 2 Time = Apl / (for the P base, when the gate is approximately the same as P layer 14, the gate is separated by Lj and. The amount of miscellaneous NpO is proportional. That is, the change of depletion. Net FP layer I / Αρ) Then it becomes -37- (33) (33) 200308096 as shown in the following formula (1).

Np0 = 9xl 01 VAp + l. 2x1 012cm'2 (1) Therefore, the net doping amount Np of the p-layer 14 under the gate is preferably smaller than the maximum net doping amount N p 0. The relationship between the net doping amount Np of the p-layer 14 under the gate and the interval Lj of the p-base layer 12 is approximately proportional to that shown in FIG. 9, for example. This is because when the interval Lj of the P base layer 12 is narrowed, the power line from the drain electrode is blocked by the P base layer 12, and therefore, the p layer 14 under the gate becomes difficult to become empty, resulting in Caused by a decrease in the maximum net doping amount NpO. According to this proportional relationship, when the above formula (1) is transformed into the following formula (2)

Np0 / Lj = 1.7x1 015 / Ap + 2xl 015cm · 3 (2) Therefore, the net doping amount Np of the P layer 14 under the gate is preferably smaller than the maximum net doping amount NpO. FIG. 30 shows the relationship between the depth Xj of the p base layer 12 and the maximum net doping amount NpO of the p layer 14 under the gate in the MOSFET structured in the first embodiment. However, it means that the doping amount of the η low-resistance layer 1 la is set to 4 X 1012cnT2, the area ratio (Ap) of the p-layer 14 under the gate is set to 50%, and the interval between the p-base layers 12 is 12 (L) is set to 2 μm.

As shown in FIG. 30, the maximum net doping amount of the p-layer 14 under the gate NpO -38- (34) (34) 200308096 is approximately inversely proportional to the depth Xj of the p-base layer 12. That is, the maximum net doping amount NpO of the p-layer 14 under the gate is approximately proportional to the inverse of the depth Xj of the p-base layer 12. This is because when the depth Xj of the P base layer 12 becomes deeper, the power lines from the drain electrode will be blocked by the P base layer 12, so the P layer 14 under the gate becomes difficult to be empty, resulting in the largest Caused by a smaller net doping amount NpO. According to this inverse relationship, when the above formula (1) is modified, it becomes as shown in the following formula (3).

NpO · Xj = 3 · 6 X 1 08 / Ap + 4 · 8 X 1 08 cm · 1 (3) Therefore, the net doping amount Np of p layer 14 under the gate is preferably smaller than the maximum net doping amount NpO . As shown in FIG. 9, the maximum net doping amount n p 0 of the p-layer 14 under the gate is approximately proportional to the interval between the p-base layer 12. Here, according to this proportional relationship, when the above formula (3) is deformed, it becomes the following formula (4):

NpO · Xj / Lj = 6xl011 / Ap + 8xl011cm · 2 (4) Therefore, the net doping amount Np of the p-layer 14 under the gate is preferably smaller than the maximum net doping amount NpO. FIG. 31 shows the relationship between the doping amount Nη of the n low-resistance layer 11a and the maximum net doping of the p-layer 14 under the gate -39- (35) (35) 200308096 amount NpO in the MOSFET constructed in the first embodiment. . As shown in FIG. 31, the maximum net doping amount NpO of the p-layer 14 under the gate is approximately proportional to the doping amount of the η low-resistance layer 11a, and therefore, the η low-resistance layer 11a becomes highly concentrated. Therefore, since the p-layer 14 under the gate is easily depleted, its maximum net doping amount NpO will increase. If the relationship between the doping amount Nil of the η low-resistance layer 11a and the maximum net doping amount NpO is expressed by a first-order approximation, it becomes as shown in the following formula (5),

Np0 = 0.37Nn + 1.6xl012cm * 2 (5) If this formula (5) is combined with the above formula (1) to change to the form including the area ratio Ap of the p layer 14 under the gate, the following formula becomes (6).

Np0 = 8.4xl011 / Ap + 0.34Nn + 0.015Nn / Ap-1.2xl011cm · 2 (6) Therefore, the net doping amount Np of the P layer 14 under the gate is preferably smaller than the maximum net doping amount NpO. As shown in FIG. 9, the maximum net doping amount NpO of the p-layer 14 under the gate is approximately proportional to the interval Lj of the p-base layer 12. Based on this relationship, when the above formula (6) is modified, the following formula (7) is obtained.

Np / Lj = 1.4 xl015 / Ap + 570Nn + 25Nn / Ap-2 xl014cm_3 (1 -40- (36) 200308096 Therefore, the net doping amount N p of the P layer 14 under the gate is better than the net doping amount N p 0 is small. As shown in FIG. 30, the maximum net doping amount of p layer 14 under the gate is approximately inversely proportional to the depth Xj of P base layer 12. When the above formula (7) is deformed according to this relationship, Becomes the following formula (8)

Np · Xj / Lj = 5.6x 10 1 1 / Αρ + 0.2 2 8Νη + 0.01Νη / Αρ-8 χ 1 〇1 Therefore, the net doping amount Nρ of the ρ layer 14 under the gate is preferably better than the net doping amount N ρ 0 is small. On the other hand, when the net doping amount Nρ of the p-layer 14 under the gate changes and the p-layer 14 under the gate becomes completely empty due to the low drain voltage, the effect that the p-layer 14 under the gate has been inserted cannot be obtained. That is, when the net doping amount of the lower p-layer 14 is too small, as shown in Fig. 8, the switching loss of the conventional MOSFET is equivalent. Therefore, the net doping amount ρ of the p layer under the gate must be a heterogeneous mass that will become empty when a high level of drain voltage is applied. As such, there exists a minimum chirp in the quantity of the p-layer 14 under the gate, which is most suitable for depletion. When the minimum net doping amount of the p-layer 14 under the gate is set to an equivalent amount of switching loss of the previous MOSFET, the minimum net doping amount of the gate layer 14 becomes 1 / of the maximum net doping amount. 4 to 1/3 of the maximum NpO, when the maximum is small, the gate and impurities at a pressure of 4 and the following P are about -41-200308096 (37) (for example, refer to FIG. 8). The maximum net doping amount of the p-layer 14 under the gate is determined by the degree of depletion of the p-layer 14 under the gate in the same manner as in the case of the maximum net doping amount. That is, the minimum net doping amount of the P layer 14 under the gate is related to the size of each part of the MOSFET or the concentration of each part. Therefore, when designing the impurities of the P layer 14 under the gate, it is most important to consider the size of each part of the MOSFET and the concentration of each part. Fig. 32 shows the relationship between the size (area ratio Ap) of the P layer 14 under the gate and the maximum net doping amount Np_min of the p layer 14 under the gate in the MOSFET of the first embodiment structure. However, it is shown here that the doping amount (Nη) of the η low-resistance layer 11a is set to 4 × 1012 cm · 2, and the interval (Lj) of the ρ base layer 12 is set to 6 μm. As shown in Figure 32, the minimum net doping amount Np_min of the p-layer 14 under the gate is approximately proportional to the inverse of the area ratio Ap of the p-layer 14 under the gate. As in the case of the maximum net doping amount NpO, if the relationship between the minimum net doping amount Np_min and the inverse number of the area ratio Ap of the p-layer 14 under the gate (WAp) is expressed as a first-order approximation, then As shown in the following formula (9),

Np-mir ^ .SxlOH / Ap + SJxloHcm · 2 (9) Therefore, the net doping amount Np of the p-layer 14 under the gate is preferably larger than the minimum net doping amount Np_min.

FIG. 33 shows the relationship between P-42- (38) (38) 200308096 of the base layer 12 and the minimum net doping amount Np-min of the p-layer 14 under the gate in the MOSFET constructed in the first embodiment. . However, it is shown here that the doping amount (Nn) of the n low-resistance layer ila is set to 4xlOI2cnT2, and the area ratio A p g of the p-layer 14 under the gate is 50%. As in the case of the above-mentioned maximum net doping amount NpO, the minimum net doping amount Np_min of the p-layer 14 under the gate is approximately proportional to the interval of the p-base layer 12. According to this proportional relationship, when the above formula (a) is deformed, it becomes as shown in the following formula (10),

Np —min / Lj = 4 · 2 X 1 0 1 4 / Αρ +8 · 8 X 1 0 1 4cm · 3 (10) Therefore, the net doping amount Np of the P layer 14 under the gate is preferably the smallest The net doping amount Np_min is large. FIG. 34 shows the relationship between the depth Xj of the p base layer 12 and the maximum net doping amount Np_min of the p layer 14 under the gate in the MOSFET of the first embodiment. However, it is shown here that the doping amount (Nn) of the η low-resistance layer 1 1 a is set to 4 X 1012cnT2, the area ratio Ap of the p-layer 14 under the gate is set to 50%, and the interval between the p-base layers 12 is 12 When Lj is set to 2 μm. As in the case of the above-mentioned maximum net doping amount NpO, the minimum net doping amount Np_min of the p layer 4 under the gate is approximately inversely proportional to the depth of the p base layer 12 (and the depth of the p base layer 12). The inverse of the magic number is approximately proportional) ° 锒 According to the inverse relationship 'when the above formula (9) is deformed', it becomes as shown in the following formula (1 1), • 43- (39) (39) 200308096

Np —miη · Xj = 1 χ 1 08 / Ap + 2.1 x 1 08cm · 1 (11) Therefore, the net doping amount Np of the P layer 14 under the gate is preferably larger than the minimum net doping amount Np_min. As shown in FIG. 3, the maximum net doping amount Np_min of the p-layer 14 under the gate is approximately proportional to the interval Lj of the p-base layer 12. Based on this relationship, when the above formula (11) is modified, it becomes as shown in the following formula (12),

Np —min · Xj / Lj = 1.7xlO &quot; / Ap + 3.5xlO &quot; cm · 2 (12) Therefore, the net doping amount Np of the P layer 14 under the gate is preferably larger than the minimum net doping amount NpO . FIG. 35 shows the relationship between the net doping amount Nil of the η low-resistance layer 1 1 a and the minimum net doping amount Np_min of the p-layer 14 under the gate in the MOSFET structured in the first embodiment. However, here is a case where the depth Xj of the p-base layer 12 is 4 μm, the area ratio Ap of the p-layer 14 under the gate is 50%, and the interval Lj of the p-base layer 12 is 6 μm. As shown in FIG. 35, the minimum net doping amount Np-m i η of the ρ layer 14 under the gate is approximately proportional to the doping amount of the η low-resistance layer 1 1 a. Therefore, the η low-resistance layer 1 1 a will High concentration. Therefore, since the p layer 14 under the gate is easily depleted, its minimum net doping amount Np_min will increase. If the relationship between the doping amount Nn of the η low-resistance layer 11a and the minimum net doping amount Np_min is expressed by a first-order approximation, it becomes the following formula (-44- (40) 200308096 1 3),

Np —min = 0 · 2Nn +3 · 4x 1 0 1 1 cm · 2 (13) If this formula (13) is further combined with the above formula (9), the area ratio A p of the p-layer 1 4 under the gate is The internal form is shown in formula (14).

Np_min = -4xl010 / Ap + 0.03 75Nn + 0.0 7 5Nn / Ap + 4xl0 &quot; cm Therefore, the net doping amount Np of the P layer 14 under the gate is preferably the doping amount Np_min is large. As shown in FIG. 33, the minimum Np_min of the p-layer 14 under the gate is approximately proportional to the interval Lj of the p-base layer 12, and when the above formula (14) is deformed, it becomes as shown below).

Np / Lj = -6.7xl013 / Ap + 62.5Nn + 125Nn / Ap + 6.7xl014cnT3 Therefore, the net doping amount Np of the P layer 14 under the gate is the largest net doping amount Np_min. As shown in Figure 34, the minimum Np_min of the p-layer 14 under the gate is approximately inversely proportional to the depth Xj of the p-base layer 12, and when the above formula (1 5) is deformed, it becomes the following transformation into a package into the following 2 (14) Lower net contention. According to the formula (15 (15) is better than the minimum content of doping. According to the formula (16 -45 · (41) (41) 200308096),

Np · Xj / Lj = -2.7xl010 / Ap + 0.225Nn + 0.05Nn / Ap + 2.7xl0u cm · 2 (16) Therefore, the net doping amount Np of the P layer 14 under the gate is better than the smallest net doping The amount Np_min is large. (Embodiment 11) FIG. 36 shows a configuration example of a power MOSFET according to an eleventh embodiment of the present invention. In addition, the same parts as those of the MOSFET shown in FIG. 18 are assigned the same reference numerals, and detailed descriptions thereof are omitted. Only the different parts are explained here. Fig. 36 shows an example when the first gate 24A and the second gate 24B having different gate lengths are used as the gate 24d in the power MOSFET having the configuration shown in Fig. 18. That is, a plurality of p base layers 12a as the second semiconductor layer are arranged in a lattice (or zigzag) manner on the surface portion of the n low-resistance layer 11a. The gate electrode 24d as the control electrode includes at least one first gate (second control electrode) 24A and at least one second gate (first control electrode) 24B arranged in a grid. The first gate electrode 24A has, for example, a first gate length (second electrode length) Lg2. The second gate 24B has, for example, a second gate length (first electrode length) Lgl which is longer than the first gate length Lg2 of the first gate 24A. In addition, the p-layers 1 4b, which are the multiple lower gates of the fifth semiconductor layer, are arranged in a line shape, respectively. 46- (42) (42) 200308096 is located between the adjacent P base layers 12a. The second gate electrode 24B has a corresponding position. The gate-drain capacitance when a low drain voltage is applied is determined based on the capacitance of the short gate length. In this case, the capacitance between the 閛 閛 and the drain becomes small, and the speed can be increased. Compared to this, the capacitance between the pole and the drain when a high drain voltage is applied increases significantly. This is because the p-layer 14b under the gate is depleted in a portion where the gate length is long, thereby reducing noise. The power MOSFET having the structure shown in FIG. 36 can be formed by changing the area of the P layer under the gate. As shown in FIG. 37, for example, a plurality of lower gate p-layers 14b-1 are selectively formed at positions corresponding to the above-mentioned second gate 24B between adjacent p-base layers 12a. In this way, it is easy to adjust the change in the capacitance between the gate and the drain by changing the area of the P layer 14b-1 under the gate. At this time, the interval Ljp between adjacent P layers 14b-1 under the gate is set to the same level as the interval Lj of the p base layer 12a corresponding to the first gate 24A. Thereby, by increasing the interval Ljx of the P base layer 12a corresponding to the second gate electrode 24B, it is possible to suppress a decrease in withstand voltage. FIG. 38 shows an example when a part of the gate electrode 24d has a split structure in the power MOSFET having the structure shown in FIG. 36. That is, in the gate 24d as the control electrode, the first gate 24A having a short gate length can be achieved by using the split structure shown in FIG. 38 or the terrace structure shown in FIG. 14. Speed up. • 47- (43) (43) 200308096 (12th embodiment)

FIG. 40 shows a configuration example of a power MOSFET according to a twelfth embodiment of the present invention. The same figure (a) is a plan view, and the same figure (b) is a sectional view. The same reference numerals are given to the same parts as those of the MOSFET shown in Fig. 28, and detailed descriptions thereof are omitted. In addition, only the different parts will be described here. Fig. 40 shows an example in which the p-layer 14d below the gate having the gate length Lg2 below the first gate 24A is formed in a self-integrated state in the power MOSFET having the configuration shown in Fig. 28. Here, an example is shown when the first and second gates 24A and 24B are formed in a line shape. That is, the MOS unit 52a as the first unit is provided with a second gate (first control electrode) 24B having a gate length Lgl. The MOS cell 52a1 is formed with a Π + source layer 13 as a third semiconductor layer on a surface portion of a p-base layer 12 as a second semiconductor layer. Further, a low-concentration η layer 1 1 b as a seventh semiconductor layer is provided between the P base layers 12. The low temperature n layer 1 1 b has a lower impurity concentration than the η low resistance layer 1 1 a. On the other hand, the MOS cell 51b as the second cell is provided with a first gate (second control electrode) 24A having a gate length Lg2 which is shorter than that of the second gate 24B. The MOS cell 51 b has an n + source layer 13 formed on a surface portion of the P base layer 12. In addition, a p-layer 14d below the gate, which is a fifth semiconductor layer, is provided between the p-base layer 12. In this case, there are different gate lengths Lg2 for the mixed existence of the p-layer 14d ° -48- (44) (44) 200308096 For the two types of MOS cells 51b and 52a / of the gates 24A and 24B of Lgl, the MOSFETs under the gate can be formed by self-integration (self-algin). FIG. 41 shows a manufacturing process of the MOSFET having the structure shown in FIG. 40. First, ion implantation and diffusion are performed on a substrate having a drift layer 11 and an n + drain layer 15 (see the same figure (a)). In addition, an η low-resistance layer 11a is formed on the surface portion of the drift layer 11 (see the same figure (b)). Next, ions of P-type impurities such as boron are implanted on the surface of the η low-resistance layer 11a and annealed. Thereby, a low-concentration η layer lib is formed on the surface portion of the η low-resistance layer 11a (see the same figure (c)). Then, the first and second gate electrodes 24A and 24B are patterned on the surface of the low-concentration η layer 1 lb through the gate insulating film 23 (see the same figure (d)). Thereafter, the p-base layer 12 is formed by ion implantation and diffusion (see the same figure (e)). At this time, a low-concentration n-layer lib exists immediately below the first and second gates 24A and 24B. Therefore, the same effect as that obtained when the lateral diffusion of the impurities in the p base layer 12 is increased can be obtained. That is, the impurities in the p base layer 12 only extend in the lateral direction near the surface of the n low-resistance layer 11a. The impurities in the P base layer 12 extend approximately evenly from both sides of each of the gates 24A and 24B. Therefore, when the gate length is short, the P base layer 12 is completely p-layered by the impurities of the p base layer 12. Thereby, it is possible to selectively form only the p-layer 14d below the first gate 24A with a short gate length of -49 · (45) (45) 200308096. When the gate length is long, the P base layers 12 are not completely P-layered. That is, the p-layer 14d below the gate is not completely formed under the second gate 24B having a long gate length. In this way, the p-layer 14d under the gate is formed only under the first gate 24A by self-integration. When the p-layer 14d under the gate is formed by lateral diffusion from the P-base layer 12, in order to completely p-layer between the p-base layers 12, the p-base layer of the MOS cell 51b The interval of 12 is preferably narrow. On the other hand, the MOS cell 52a &gt;, the interval between the p base layers 12 is preferably wide. In order to surely form two MOS cells 51b and 52a with different patterns, it is desirable to change the interval between the p-base layers 12 more than twice. In the case of a MOSFET formed by this process, the gate-drain capacitance when a low drain voltage is applied can be determined based on the capacitance of the MOS cell 52a &lt; having a low concentration n-layer lib. In addition, the capacitance between the gate and the drain when a high drain voltage is applied increases the capacitance of the MOS cell 52a / by adding the capacitance of the MOS cell 51b having the P layer 14d under the gate. This can reduce noise. In addition, for the MOSFET structured in this way, the overall ratio of the MOS cell 51b to the entire cell of the element, or the area of the p-layer 14d under the gate relative to the area under the gate of the entire element ( For example, the ratio of the surface area of the low-concentration η layer 1 1 b) is increased. This makes it possible to increase the gate-drain capacitance when a high drain voltage is applied. As a result, the effect of noise reduction can be improved. Therefore, the proportion of the above-mentioned MOS unit 51b is -50- (46) 200308096 or the proportion of the area of the P layer 14d below the gate. In addition, the gate provided under the gate of the MOS unit 51b should be completely covered with the gate 24A. Below. Only the P-layer 1 has a gate-drain capacitance due to the drain. Therefore, about the same effect as that between the p base layer 12 can be obtained. That is, it is possible to obtain low noise, and a plutonium with a clear net doping amount of the p-layer 14d under the gate. Furthermore, it is possible to selectively form the n + source layer 13 for the power having the structure shown in FIG. 40. That is, as shown in FIGS. 42 (a) and (b), the n + source layer 1 3 as the third semiconductor layer, for example, the second gate 24B having a long gate length is a P group of a corresponding layer. The surface portion of the electrode layer 12. That is, the old electrode layer 13 is formed on the surface of the p base layer 12 corresponding to the first electrode 24A. In addition, the same figure (a) is a plan view and [1 figure. The MOS cell 51b is covered with the p-layer Md below the second pole of the first gate 24A. Therefore, the m0S flow flows through. Therefore, in the surface portion facing I with the first gate electrode 24A, even if there is no N + source layer 1 3, the resistance is not affected. Furthermore, it is possible to suppress the movement of the through-throw dual-port transistor. For example, when the P layer 14d is more than 30%, the effect of complete P-layer aging is not required to increase the formation of a depletion voltage. It is better that the power MOSFET that has been said to be g is only formed on the P-th part which is shorter than the length of the second semiconductor gate. The N + source is not formed. Figure (b) is completely below the cross-section. The unit 51b does not have the P base layer 12 of the electrical I for turning on the element, and can increase the area of -51-(47) 200308096 safe operation of the element. Fig. 43 is a diagram showing another configuration example of the power of the twelfth embodiment of the present invention. Here, for a power MOSFET capable of self-integrating the p-layer under the gate, the first and second gates 24A and 24B are formed in a grid-like shape, that is, the second semiconductor layer is mostly Each p base is arranged in a lattice (or zigzag) manner at the η low-resistance layer portion. An n + source layer 13a is formed on the surface of the P base layer 12a. The gate electrode 24d serving as the control electrode has at least one first gate electrode (at least one second gate electrode (first control electrode) 24B of the second control circuit). 24A has, for example, a first gate length (second (Electrode length) The gate 24B has, for example, a second gate length (first electrode length) Lgl which is longer than the first Lg2 of the first gate 24A. In addition, a plurality of gates as the fifth semiconductor layer are self-integrated (Selfalgin) are formed only between the P base layers 12a and are opposite to the first gate 24A, respectively, and are located between adjacent P base layers 12 and corresponding to the upper 24B. 1 lb ° of the seventh semiconductor layer can be formed with the same gate length by self-rate MOSFET even if it has such a structure. For example, the layer 12a has a surface of 1 1 a. 3 The semiconductor layer has a configured electrode.) 24A and the first gate Lg2. The 21st gate length ρ layer 14d is located at the adjacent corresponding part. tSecond gate Low-concentration η layer Integratedly formed • 52- (48) (48) 200308096 The p-layer under the gate 14d, which can reduce cost. Fig. 44 shows an example when the n + source layer 13 is selectively formed in the power MOSFET having the structure shown in Fig. 43. That is, the η + source layer 13a as the third semiconductor layer is formed only on the surface portion of the P base layer 12a as the second semiconductor layer corresponding to the second gate 24B having a long gate length. That is, in the control electrode 24d, the n + source layer 13a is not formed on the surface portion of the p base layer 12a corresponding to the first gate electrode 24A having a short gate length. The portion of the first gate 24A is completely covered by the p-layer 14d under the gate between the p-base layers 12a. Therefore, no current will flow in this part. Therefore, the surface portion of the p base layer 12a corresponding to the first gate electrode 24A does not affect the ON resistance of the device even if the n + source layer 13a is absent. Furthermore, it is possible to suppress the operation of the dual-port transistor, and to increase the field of safe operation of the device. Fig. 45 shows another example when the gate is arranged in a line shape in the power MOSFET of the twelfth embodiment. In addition, the same figure (a) is a plan view illustrating a gate pattern, the same figure (b) is a cross-sectional view taken along line 45B-45B of the same figure (a), and the same figure (c) is along the same Figure (a) is a sectional view taken along line 45C-45C. In this example, a plurality of gate electrodes 24e as control electrodes are provided in a line shape. In addition, each of the plurality of gates 24e includes a gate portion (second control electrode portion) 24A having at least one of the first gate length (second electrode length) Lg2, and a gate portion 24A having more than the first gate length (second control electrode portion). Pole length -53- (49) 200308096

Lg2 is the second gate portion (first control electrode portion) 24B of the long second gate length (first electrode length) Lgl. Fig. 46 shows another example when the gates of the power MOSFETs of the twelfth embodiment are arranged in a grid pattern. In addition, the same figure (plan pattern illustrating the gate pattern), the same figure (b) is a cross-sectional view of line 46B-46B in figure (a), and the same figure (c) is line 46C-46C along a) Section view. In this example, the plurality of gate electrodes 24f serving as the control electrodes include a gate portion (second control electrode portion) 24A / having a gate length (second electrode length) Lg2 of up to, and The gate length Lg2 is a long second gate length (the second gate portion (the first control electrode portion) of at least one of the first electrodes Lg 1). In addition, a plurality of gates 24f respectively separate the first gates. The poles are assembled here in a grid pattern. Fig. 47 shows another example when the gates of the power MOSFETs of the twelfth embodiment are arranged in a grid pattern. In addition, the same figure (a plan view of a gate pattern) and the same figure ( b) is a sectional view taken along line 47B-47B in Fig. (a), and (c) is a sectional view taken along line 47C-47C in a). 〇 In this example, a plurality of The gate 24 g includes a gate portion (second control electrode portion) 24A # having a length of the first gate length (second electrode length) Lg2, and a second gate having a length longer than 1 gate length Lg2. Length (at least one of the first electrode: a) is along the same figure (including one less than the above first length) 24B / 24 Along the same figure (respectively include one less than the above-mentioned length) -54- (50) 200308096

The second gate portion (first control electrode portion) of at least one of the Lgls is 24B /. In addition, the plurality of gate electrodes 24g are each assembled with the first gate portions 24A in a grid pattern. As shown in FIGS. 45 to 47, the gate lengths of the gates 24e, 24f, and 24g are locally changed. At this time, by changing the ratio of the width of the first gate portion 24A with a short gate length, the area of the P layer 14d under the gate can be freely changed in either case. In addition, each of the power MOSFETs shown in FIGS. 45 to 47 is the same as the power MOSFETs shown in FIGS. 42 and 44, and can be omitted from the first gate portion 24A # corresponding to the short gate length. An n + source layer 13 is formed on a surface portion of the p base layer 12. (Thirteenth Embodiment) Fig. 48 shows a configuration example of a power MOSFET according to a thirteenth embodiment of the present invention. In addition, the same reference numerals are assigned to the same parts as those of the MOSFET shown in FIG. 40, and detailed descriptions thereof are omitted. Here, only the different parts will be explained. Fig. 48 is a case in which a p-layer under the gate can be self-integrated to form a p-layer under the gate. A case in which the p-layer under the gate 14 d can be formed under the second gate 24B having a certain gate length is taken as an example . That is, a plurality of p base layers 12 as the second semiconductor layer are selectively arranged on the surface portion of the n low-resistance layer 11a. In addition, an n + source layer 13 as a third semiconductor layer is formed on the surface of the p base layer 12, and the η low-resistance layer -55- (51) located between adjacent P base layers 12 is formed. 200308096 The surface portion of 11a is provided with a low-temperature 11 layer 11b as a seventh semiconductor layer. In the control electrode, for example, the gate electrode 24B has a certain long gate electrode (for example, Lgl). In this example, p 1 4d, which is a plurality of gates of the fifth semiconductor layer, is formed between adjacent p base layers 12 by self-integration (lateral type diffusion of p-type impurities). The p-layer 14d below the gate is connected to each of the P-base layers 12 separately. In addition, the p-layers 14d under the gates do not completely cover the adjacent P base layers 12 respectively. As described above, for forming a p-layer MOSFET under the gate by self-integration, for example, as shown in FIG. 48, forming the p-base layer 12 under the gate 24B having a gate length of a certain range does not increase the p-base layer 12 The P layer 14d is completely covered therebetween. As a result of the p-layer 14d under the gate, the gate-drain capacitance will increase due to the rise in the drain voltage. Therefore, approximately the same effect as when the p-layer is completely p-layered between the p-base layers 12 can be obtained, that is, the effect of reducing noise. When the doping amount of the P-type impurity increases, p 1 4d under the gate is easily formed. However, at this time, the resistance constant of the low-concentration η layer 1 1 b is increased and the ON resistance is increased. Here, the doping amount of impurities used to form the under-gate P layer 14d and the low-concentration η layer 1 and the gate length of the gate 24B (the interval between the p base layers 12 must be appropriately designed. In order to suppress the increase in the ON electricity, the interval between the P base layers 12 is set to a width approximately equal to the depth of the ρ base 12. It is also preferable to set the interval between the P layers 14d under the gate to about half. The layered and grounded poles will also have a resistance layer of lb. -56- (52) (52) 200308096 In addition, as in this embodiment, it can be formed under the gate 24B, which has a certain gate length. The MOSFET of the P layer 14d that does not completely cover the p-base layers 12 may be a MOSFET other than the MOSFET shown in FIG. 40. For example, the MOSFET can be similarly applied to a case where the gate and the gate can be omitted. The first gate electrode 24A having a short length is a MOSFET in which the n + source layer 13 is formed on the surface portion of the corresponding p base layer 12. As shown in FIG. 43 or FIG. 44, the p base layer 12a is arranged in a grid. For a MOSFET with a similar structure, for example, the p-layer 14d can be formed so that it can be positioned below the gate 24A with a short gate length. The p-base layers 12 and 2 are completely covered, but the p-base layers 12a located below the gate 24B with a long gate length are not completely covered. Furthermore, in the twelfth embodiment, The MOSFET is not limited to a MOSFET in which two types of MOSFETs having different gate lengths are mixed, and may be a MOSFET including only one type of MOSFET having a certain gate length. (Fourteenth Embodiment) FIG. 49 shows the present invention. A configuration example of a power MOSFET according to a fourteenth embodiment of the present invention. In addition, the same reference numerals are assigned to the same parts of the MOSFET shown in FIG. 1, and detailed descriptions thereof are omitted. In addition, only different parts will be described here. In FIG. 49, a plurality of p base layers 12a as the second semiconductor layer are arranged in a lattice (or zigzag) manner on the surface portion of the n low-resistance layer 11a. In addition, a plurality of fifth base layers The p-layer 14a under the gate is disposed between four adjacent p-base layers 12a. • 57 · (53) 200308096 In addition, a plurality of n + source layers 13a as the third semiconductor layer are It is formed in a ring shape on the surface portion of each of the p base layers 12a. A rectangular source electrode 22a as a first main electrode is provided at a position corresponding to each of the P base layer 12a and the n + source layer 13a. The gate electrode 24h as a control electrode is provided in a grid pattern. The portions other than the above-mentioned respective source electrodes 22a. The gate electrode 24h has a portion which does not correspond to the p-layer 14a below the gate, that is, corresponds to an η low-resistance layer 11a located between the p-layer 14a below the gate There is a split structure with an opening of 24ha in the part. The MOSFET according to this embodiment can reduce the gate-drain capacitance when a low drain voltage is applied. This can increase speed. In addition, the MOSFET of this structure is not limited to the split structure, and the same effect can be expected even if the gate adopts a terrace structure as shown in FIG. 14. (Fifteenth Embodiment) Fig. 50 shows a configuration example of a power MOSFET according to a fifteenth embodiment of the present invention. In addition, the same reference numerals are assigned to the same parts of the MOSFET shown in FIG. 1, and detailed descriptions thereof are omitted. In addition, only the different parts will be described here. In FIG. 50, a plurality of p base layers 1 2a as the second semiconductor layer are arranged in a lattice (or zigzag) manner on the surface portion of the n low-resistance layer 1 1 a. In addition, a plurality of lower gate P layers 14a, which are the fifth semiconductor layers, are respectively disposed between four adjacent p base layers 12a. -58- (54) (54) 200308096 Furthermore, a plurality of n + source layers 13a as the third semiconductor layer are selectively formed on the surface portion of each of the p base layers 12a. The n + source layer 1 3 a is provided only on the surface portion of the p base layer 12 a except for a portion corresponding to the p layer 1 4 a under the gate. That is, the n + source layer 1 3 a is not formed on the surface of the p base layer i2a corresponding to the p layer 14a under the gate. In addition, the p base layer 12a and the n + source are respectively formed. A rectangular source electrode 22a is provided as a first main electrode at a portion corresponding to the electrode layer 1a. The gate electrodes 24i serving as control electrodes are provided in a grid pattern at locations other than the respective source electrodes 22a. The MOSFET constructed according to this embodiment can suppress the operation of the parasitic dual-port transistor without changing the ON resistance. This makes it possible to increase the safe operation area of components. In addition, in the MOSFET of this structure, the gate electrode 24i may adopt a split gate structure shown in FIG. 49 (or a trorrance gate structure shown in FIG. 14). In this case, it is possible to realize a high-speed MOSFET with a large field of component safety operation. (16th embodiment) Fig. 51 shows a configuration example of a power MOSFET according to a 16th embodiment of the present invention. The same reference numerals are assigned to the same parts as those of the MOSFET shown in FIG. 49, and detailed descriptions thereof are omitted. In addition, only the different parts will be described here. FIG. 51 shows an example in which the gate layers of the gate -59- (55) 200308096 are connected to each other in the MOSFET having the structure shown in FIG. 49. That is, a plurality of p base layers 12a, which are semiconductor layers of the table 2, are arranged in a lattice (or zigzag) manner on the surface portion of the n low-resistance layer 11a. In addition, a plurality of p-layers under the gate 1 4 a / which are the fifth semiconductor layer are arranged between the four adjacent p-base layers 1 2 a. Further, a plurality of lower gate P layers 14a &lt; respectively arranged between two adjacent p base layers 12a are locally connected to each other. Further, a plurality of n + source layers 13a as the third semiconductor layer are formed in a ring shape on the surface portion of each of the p base layers 12a. A rectangular source electrode 22a is provided as a first main electrode at portions corresponding to the p base layer 12a and the n + source layer 1 3a. The gate electrodes 24i serving as control electrodes are provided in a grid pattern at locations other than the above-mentioned respective source electrodes 22a. With such a structure, the MOSFET structured in this embodiment can form a p-layer 14 a / under the gate without breaking the MOS channel. As a result, an increase in the ON resistance can be suppressed. In addition, as shown in FIG. 52, the MOSFET having this structure is also applicable to a MOSFET having a structure in which gates are arranged in a line shape. That is, a plurality of p base layers 12 as the second semiconductor layer are arranged in a line shape on the surface portion of the η low-resistance layer 1 1a. In addition, p-layers under the gate serving as the fifth semiconductor layer are respectively disposed between two adjacent p-base layers 12. Further, the p-layers under the gate 14 / which are respectively disposed between the two adjacent p-base layers 12 are partially connected to the two adjacent p-base layers 12 respectively. Further, at least -60- (56) (56) 200308096 one n + source layer 13 as a third semiconductor layer is formed in a line shape on the surface portion of each of the p base layers 12 described above. In addition, linear source electrodes 22 as first to electrodes are provided at positions corresponding to the P base layer 12 and the n + source layer 13 respectively. In addition, the gate electrode 24 serving as a control electrode is provided in a line shape via the insulating film 23 at positions other than the respective source electrodes 22 described above. This structure of the MOSFET can reduce the area of the p-layer 14 / under the gate connected to the MOS channel, and can suppress the reduction of the effective width of the MOS channel. As a result, the increase of the ON resistance can be suppressed. In addition, the MOSFET having the structure of the present embodiment described above can be similarly applied to MOSFETs having structures having gates having different gate lengths, as shown in each of the eleventh and twelfth embodiments. In addition, in each of the above embodiments, the case where the first conductivity type is set to the η type and the second conductivity type is set to the p type is described, but it is not limited to this, and any of the embodiments may also be the first type The conductivity type is a ρ-type, and the second conductivity type is a η-type. In each of the embodiments, the case of using Si is described, but it is not limited to this. For example, it can be applied to a carbon silicon compound (SiC), gallium nitride (GaN), or aluminum nitride (A1N). Of compound semiconductor or diamond components. Furthermore, the embodiments are not limited to MOSFETs having a super junction structure and vertical switching elements. For example, as long as it is a MOS or MIS device such as a lateral MOSFET or IGBT, the same can be achieved -61 · (57) (57) 200308096 In addition, the present invention is not limited to the above (each) embodiment, as long as it does not depart from it Various modifications can be made within the scope of the subject. Furthermore, the embodiments described above also include inventions in various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed components. For example, even if several elements of all the constituent elements shown in the (each) embodiment are deleted, the problem (at least one) described in the second paragraph of the problem to be solved by the invention can be solved. When the effect (at least one) described in the second paragraph of the effect of the invention is removed, the structure that deletes the constituent elements can be extracted as the invention. [Brief Description of the Drawings] FIG. 1 is a perspective view showing a part of a configuration example of a vertical power MOSFET according to a first embodiment of the present invention. FIG. 2 is a characteristic diagram comparing the gate-drain voltage dependency of the gate-drain capacitance in the MOSFET shown in FIG. 1 with a conventional structure of MOSFET S E T. FIG. 3 is a characteristic diagram in which the drain voltage waveform and the drain current waveform of the MOSFET shown in FIG. 1 when the TURN is OFF are compared with a conventionally constructed MOSFET S E T. FIG. 4 is a perspective view showing a part of another configuration example of the vertical power MOSFET according to the first embodiment of the present invention. FIG. 5 is a perspective view cut away and showing a part of still another configuration example of the vertical power MOSFET according to the first embodiment of the present invention.

FIG. 6 is a characteristic diagram showing a waveform of TURN OFF -62- (58) (58) 200308096 of the MOSFET of the first embodiment of the present invention in comparison with a conventionally constructed MO SFET. Fig. 7 is a characteristic diagram showing the change in TURN OFF loss when the area of the P layer under the gate is changed in the MOSFET according to the first embodiment of the present invention. Fig. 8 is a characteristic diagram showing the change in TURN OFF loss when the net doping amount of the P layer under the gate is changed in the MOSFET according to the first embodiment of the present invention. FIG. 9 is a characteristic diagram showing the relationship between the p-base interval and the maximum net impurity amount of the P layer under the gate in the MOSFET according to the first embodiment of the present invention. Fig. 10 is a sectional view of a main part showing a configuration example of a power MOSFET according to a second embodiment of the present invention. Fig. 11 is a sectional view of a main part showing a configuration example of a power MOSFET according to a third embodiment of the present invention. Fig. 12 is a sectional view of a main part showing another configuration example of the power MOSFET according to the third embodiment of the present invention. Fig. 13 is a sectional view of a main part showing a structural example of a power MOSFET according to a fourth embodiment of the present invention. Fig. 14 is a sectional view of a main part showing another configuration example of a power MOSFET according to the fourth embodiment of the present invention. Fig. 15 is a perspective view showing a part of a configuration example of a power MOSFET according to a fifth embodiment of the present invention. Fig. 16 is a perspective view showing a part of a configuration example of a power MOSFET according to a sixth embodiment of the present invention. Fig. 17 is a perspective view of a power MOSFET according to a sixth embodiment of the present invention, which is partially cut away and showing another configuration example of -63- (59) (59) 200308096. Fig. 18 is a perspective view showing a part of still another configuration example of the power MOSFET according to the sixth embodiment of the present invention. Fig. 19 is a plan view showing an example of the arrangement pattern of the P layer under the gate in the power MOSFET according to the sixth embodiment of the present invention. Fig. 20 is a plan view showing another example of the arrangement pattern of the P layer under the gate in the power MOSFET according to the sixth embodiment of the present invention. 21 is a plan view showing still another example of a layout pattern of the P layer under the gate in the power MOSFET according to the sixth embodiment of the present invention. Fig. 22 is a sectional view of a main part of an example when applied to an IGBT in the seventh embodiment of the invention. Fig. 23 is a sectional view of a main part of another example of the configuration of an IGBT according to the seventh embodiment of the invention. Fig. 24 is a cross-sectional view of a main part of still another configuration example of the IGBT according to the seventh embodiment of the present invention. Fig. 25 is a sectional view of a main part showing a configuration example of a power MOSFET according to an eighth embodiment of the present invention. Fig. 26 is a sectional view of a main part of an example when applied to an IGBT in the eighth embodiment of the present invention. Fig. 27 is a sectional view of a main part showing a configuration example of a power MOSFET according to a ninth embodiment of the present invention. Fig. 28 is a sectional view of a main part showing another configuration example of the power MOSFET according to the ninth embodiment of the present invention. FIG. 29 shows the tenth embodiment of the present invention, which is based on the structure shown in FIG. 1 -64- (60) 200308096 MOSFET, showing the area ratio of the p-layer under the gate and the gate? Persistence diagram of the relationship between the maximum net doping amount of the layers. Fig. 30 is a characteristic diagram showing the relationship between the depth of the p base layer and the maximum net doping amount of the p layer under the gate in the MOSFET configured as shown in Fig. 1. Fig. 31 is a characteristic diagram showing the relationship between the impurity amount of the η low resistance layer and the maximum net impurity amount of the p-layer under the gate in the MOSFET configured as shown in Fig. 1. Fig. 32 is a characteristic diagram showing the relationship between the area ratio of the P layer under the gate and the minimum net impurity amount of the p layer under the gate in the MOSFET configured as shown in Fig. 1. Fig. 33 is a characteristic diagram showing the relationship between the interval between the p-base layer and the minimum net impurity amount of the p-layer under the gate in the MOSFET configured as shown in Fig. 1. Fig. 34 is a characteristic diagram showing the relationship between the depth of the p base layer and the minimum net impurity amount of the P layer under the gate in the MOSFET not constituted in Fig. 1. Fig. 35 is a characteristic diagram showing the relationship between the amount of impurity of the η low resistance layer and the minimum net amount of impurity of the P layer under the gate in the MOSFET having the structure shown in Fig. 1. Fig. 36 is a plan view showing a configuration example of a power MOSFET according to the eleventh embodiment of the present invention with a part of the gate electrode cut away. Fig. 37 is a plan view showing another example of the configuration of the power MOSFET according to the eleventh embodiment of the present invention, with a part of the gate electrode cut away. Fig. 38 is a plan view showing another example of the configuration of the power MOSFET according to the eleventh embodiment of the present invention with a part of the gate electrode cut away. Fig. 39 is a plan view showing another example of the power MOSFET according to the eleventh embodiment of the present invention, with a part of the gate electrode cut away. Fig. 40 is a configuration diagram of an example of a power MOSFET according to a twelfth embodiment of the present invention. FIG. 41 is a process cross-sectional view for explaining a process of manufacturing the power MOSFET shown in FIG. 40. FIG. Fig. 42 is a configuration diagram of another example of a power MOSFET according to the twelfth embodiment of the present invention. Fig. 43 is a plan view showing another example of the configuration of the power MOSFET according to the twelfth embodiment of the present invention with a part of the gate electrode cut away. Fig. 44 is a plan view showing another example of the configuration of the power MOSFET according to the twelfth embodiment of the present invention with a part of the gate electrode cut away. Fig. 45 is a configuration diagram of another example when the gate is arranged in a line shape in the power MOSFET having the configuration shown in Fig. 12. Fig. 46 is a configuration diagram of another example when the gates are arranged in a grid shape in the power MOSFET having the configuration shown in Fig. 12. Fig. 47 is a configuration diagram of still another example when the gates are arranged in a grid shape in the power MOSFET having the configuration shown in Fig. 12. Fig. 48 is a sectional view of a configuration example of a power MOSFET according to a thirteenth embodiment of the present invention. Fig. 49 is a plan view showing a configuration example of a power MOSFET according to a fourteenth embodiment of the present invention with a part of the gate electrode cut away. Fig. 50 is a plan view showing a configuration example of a power MOSFET according to a fifteenth embodiment of the present invention with a part of the gate electrode cut away. Fig. 51 is a plan view showing a structure of a power MOSFET according to a sixteenth embodiment of the present invention, with a part of the gate electrode cut away as an example. Fig. 52 is a plan view showing another example of the configuration of the power MOSFET according to the sixteenth embodiment of the present invention with a part of the gate electrode cut away. [Comparison table of main components] 1 1 η-drift layer 11a η low resistance layer 11b low concentration η layer 12, 12a p base layer 1 3, 1 3 a η + source layer 14, 14 ', 14a, 14a', 14b, 14b-1, 14c, 14d p-layer (p-layer under gate) 15 n + drain layer 21 drain 22, 22a, 22A source 2 3, 2 3 a, 2 3 d gate insulation film

24 、 24d 、 24e 、 24f 、 24g 、 24h 、 24i 、 24A 、 24A-1 、 24B Gate (planar gate structure) 24ha opening 24A / 1st gate part 24B / 2nd gate part 24a gate (deep groove analysis Structure) 24b gate (split structure) 24c gate (platform structure) • 67- (63) (63) 200308096 3 1 p + drain layer 32 η + buffer layer 4 1 dummy cell 42 normal cell 51, 51a , 51b MOS unit (with p-layer) 52, 52a, 52a ^ MOS unit (without p-layer)

Id Drain current V d s Drain voltage

Eoff turn off Loss Lgl 2nd gate length

Lg2 1st gate length -68-

Claims (1)

(1) 200308096 Patent application scope 1. An insulated gate semiconductor device, comprising: a first semiconductor layer of a first conductivity type; and a first semiconductor layer selectively formed on the first conductivity type. A plurality of second semiconductor layers of the second conductivity type on the surface portion; a third semiconductor layer of the first conductivity type that is formed on at least one of the surface portions of the plurality of second semiconductor layers of the second conductivity type; A plurality of first main electrodes connected to the plurality of second conductive layers of the second conductivity type and the plurality of first conductive electrodes of the third semiconductor layer of the first conductivity type; The fourth semiconductor layer on the back side of the 1 semiconductor layer; the second main electrode connected to the fourth semiconductor layer; the second semiconductor layer of the plurality of second conductivity types formed through the gate insulating film, at least one of the second semiconductor layer The third semiconductor layer of the first conductivity type, and the control electrode on each surface of the first semiconductor layer of the first conductivity type, and the first semiconductor layer of the first conductivity type is provided and is connected to the plurality of First At least one of the second-conductivity-type second semiconductor layers has a second-conductivity-type fifth semiconductor layer having a lower impurity concentration than the plurality of second-conductivity-type second semiconductor layers. 2. For example, the insulated gate semiconductor device of the scope of application for the patent, wherein the fifth semiconductor layer of the second conductivity type of at least one of the above is provided in position -69- (2) (2) 200308096 The surface portion of the first semiconductor layer of the first conductivity type between the second semiconductor layers of the two conductivity type. 3. The insulated gate type semiconductor device according to item 2 of the scope of patent application, wherein the plurality of second semiconductor layers of the second conductivity type are arranged in a line shape. The at least one second semiconductor layer of the second conductivity type is It is provided along the first direction of the second semiconductor layer of the second conductivity type. 4. If the insulated gate type semiconductor device according to item 2 of the patent application scope, wherein the plurality of second semiconductor layers of the second conductivity type are arranged in a line shape, and the at least one second semiconductor layer of the second conductivity type is It is provided along a second direction orthogonal to the first direction along the second semiconductor layer of the second conductivity type. 5. The insulated gate type semiconductor device according to item 1 of the patent application scope, wherein the fifth semiconductor layer of the at least one second conductivity type is buried in the first semiconductor layer of the first conductivity type. 6. The insulated gate type semiconductor device according to item 1 of the patent application, wherein the control electrode has a planar structure. 7. The insulated gate semiconductor device according to item 6 of the patent application, wherein the control electrode has a split gate structure. 8. The insulated gate semiconductor device according to item 6 of the patent application, wherein the control electrode has a terrace gate structure. 9. The insulated gate type semiconductor device according to item 1 of the patent application scope, wherein the control electrode has a deep trench structure. -70- (3) 200308096 1 0. If the insulated gate semiconductor device according to item 9 of the patent application scope, wherein the control electrode has a deep trench structure, the fifth semiconductor layer of the at least one second conductivity type is along the The bottom surface of the control electrode and at least one of the side surfaces are provided. 1 1. The insulated gate semiconductor device according to item 1 of the scope of the patent application, wherein the plurality of second semiconductor layers of the second conductivity type are arranged in a grid, and the at least one second semiconductor layer of the second conductivity type is a semiconductor layer. A rectangle is formed between the second semiconductor layers of the second conductivity type. 1 2 · In the case of an insulated gate semiconductor device according to item 11 of the patent application, wherein the fifth semiconductor layer of the second conductivity type of the above-mentioned one is provided on the adjacent second semiconductor of the second conductivity type Between layers. 1 3. The insulated gate semiconductor device according to item 11 of the scope of the patent application, wherein at least one of the fifth semiconductor layers of the second conductivity type is provided on the adjacent second semiconductor of the second conductivity type. Between layers. 1 4 · If the insulated gate semiconductor device of item 13 of the patent application 'is adjacent to the second semiconductor layer of the second conductivity type, the interval between the second semiconductor layer of the above-mentioned second conductivity type is longer than the interval of the adjacent second semiconductor layer of the second conductivity type. For the narrow. 1 5 · In the case of an insulated gate semiconductor device according to the scope of the patent application, wherein the plurality of second semiconductor layers of the second conductivity type are arranged in a grid, and at least one of the second semiconductors of the second conductivity type are arranged in a grid. The layers are respectively provided in a line shape between the second semiconductor layers of the second conductivity type. 16. If the insulated gate semiconductor device of item i in the scope of the patent application, -71-(4) 200308096, the plurality of second semiconductor layers of the second conductivity type are arranged in a grid shape. The fifth semiconductor layer of the second conductivity type is provided so as to surround a plurality of second semiconductor layers of the second conductivity type. 1 7 · The insulated gate semiconductor device according to item 6 of the patent application, wherein the at least one fifth semiconductor layer of the second conductivity type is provided in a zigzag shape. 18. The insulated gate type semiconductor device according to item 16 of the scope of patent application, wherein the at least one fifth semiconductor layer of the second conductivity type is provided in a line shape. 19 · An insulated gate type semiconductor device according to item 18 of the scope of patent application ′, wherein the fifth semiconductor layer of the second conductivity type of one of the above is provided in one direction. 20. The insulated gate semiconductor device according to item 18 of the scope of patent application, wherein at least one of the second semiconductor type fifth semiconductor layers is provided in two directions. 2 1 · Insulation gate type semiconductor device according to item 1 of the scope of patent application, wherein the fourth semiconductor layer is composed of a semiconductor layer of first conductivity type. 22 · Insulation gate type semiconductor device according to item 1 of the scope of patent application Wherein, the above-mentioned fourth semiconductor layer is composed of a semiconductor layer of the second conductivity type, such as an insulated gate semiconductor device of the 22nd scope of the application for a patent. The semiconductor layer -72- (5) (5) 200308096 is further provided with a sixth semiconductor layer of the first conductivity type. 24. The insulated gate type semiconductor device according to item 1 of the scope of patent application, wherein the surface area of the fifth semiconductor layer of the at least one second conductivity type is the second conductivity type adjacent to the second conductivity type. The surface area of the first semiconductor layer of the first conductivity type between the two semiconductor layers is 30% or more. 25. The insulated gate semiconductor device according to item 1 of the patent application range, wherein the effective impurity amount of the at least one second conductive type fifth semiconductor layer is from lxlO12 to 3.2xl012cm · 2. 26. The insulated gate type semiconductor device according to item 1 of the patent application scope, wherein the effective impurity amount (Np) of the at least one second conductive type fifth semiconductor layer and the adjacent second conductive type second semiconductor are The interval (Lj) ratio of the layers is Np / Lj &lt; 2xl015cm · 3. 27. The insulated gate semiconductor device according to item 1 of the scope of the patent application, wherein the effective impurity amount (Np) of the fifth semiconductor layer of at least one of the second conductivity type and the adjacent second semiconductor of the second conductivity type The ratio of the product of the layer spacing (Lj) and its joint depth (Xj) is Np / (Lj · Xj) &lt; 5xl018cm-4. 2 8 · An insulated gate semiconductor device, comprising: a first semiconductor layer of a first conductivity type; and a plurality of selectively formed on a surface portion of the first semiconductor layer of the first conductivity type. A second semiconductor layer of the second conductivity type; -73- (6) 200308096 a third semiconductor layer of the first conductivity type formed on at least one of the surface portions of the plurality of second semiconductor layers of the second conductivity type; A plurality of first main electrodes connected to the plurality of second conductive layers of the second conductivity type and the plurality of first conductive electrodes of the third semiconductor layer of the first conductivity type; The fourth semiconductor layer on the back side of the 1 semiconductor layer; the second main electrode connected to the fourth semiconductor layer; the second semiconductor layer of the plurality of second conductivity types formed through the gate insulating film, at least one of the second semiconductor layer The third semiconductor layer of the first conductivity type, and the control electrode on each surface of the first semiconductor layer of the first conductivity type, and the first semiconductor layer of the first conductivity type is provided and is connected to the plurality of 2nd conductive type At least one of the two semiconductor layers, and the fifth semiconductor layer of the second conductivity type having one of the lower impurity concentrations than the second semiconductor layer of the plurality of second conductivity types, a voltage is applied to the second semiconductor layer. The capacitance between the control electrode and the second main electrode at the time of the main electrode is configured to be reduced at a low voltage and constant or increased at a high voltage. 29. An insulated gate-type semiconductor device, comprising: a first semiconductor layer of a first conductivity type; a plurality of first semiconductor layers selectively formed on a surface portion of the first semiconductor layer of the first conductivity type; Second semiconductor layer of two conductivity type; -74- (7) (7) 200308096 A third semiconductor of first conductivity type formed on at least one of the surface portions of the second semiconductor layer of the plurality of second conductivity types, respectively. Layers; a plurality of first main electrodes respectively connected to the plurality of second conductive layers of the second conductivity type and the at least one third conductive layer of the first conductivity type; formed on the first conductivity type A fourth semiconductor layer on the back side of the first semiconductor layer; a second main electrode connected to the fourth semiconductor layer; and formed on the plurality of second semiconductor layers of the second conductivity type via a gate insulating film. At least one third semiconductor layer of the first conductivity type, and a control electrode on each surface of the first semiconductor layer of the first conductivity type, and a first semiconductor layer provided on the first conductivity type and connected to the first semiconductor layer of the first conductivity type The plurality of second conductive types When the second semiconductor layer has at least one of the two semiconductor layers, and the second semiconductor layer has a lower impurity concentration than the second semiconductor layer of the plurality of second conductivity types, the fifth semiconductor layer of the second conductivity type is applied to the second main electrode. When the voltage is 1/3 to 2/3 of the rated voltage, the capacitance between the control electrode and the second main electrode will start to increase. 30 · An insulated gate semiconductor device, comprising: a first semiconductor layer of a first conductivity type; a plurality of first semiconductor layers selectively formed on a surface portion of the first semiconductor layer of the first conductivity type; Second semiconductor layer of two conductivity type; -75- (8) 200308096 A third semiconductor layer of first conductivity type formed on at least one of the surface portions of the second semiconductor layer of the plurality of second conductivity types, respectively; A plurality of first main electrodes connected to the plurality of second conductive layers of the second conductivity type and a plurality of first conductive electrodes of the third semiconductor layer of the first conductivity type; A fourth semiconductor layer on the back side of the semiconductor layer; a second main electrode connected to the fourth semiconductor layer; and a second semiconductor layer of the plurality of second conductivity types formed through the gate insulating film, the at least one of The third semiconductor layer of the first conductivity type, and the control electrode on each surface of the first semiconductor layer of the first conductivity type; and the first semiconductor layer of the first conductivity type, which is provided to the plurality of first semiconductor layers; Second conductivity type A fifth semiconductor layer of the second conductivity type having at least one of the conductive layers and a second conductivity type having a lower impurity concentration than the second semiconductor layer of the plurality of second conductivity types is applied to the second main electrode. When the voltage is 1/3 to 2/3 of the rated voltage, the at least one fifth semiconductor layer of the second conductivity type is completely empty. 3 1. An insulated gate type semiconductor device, comprising: a first unit including at least: a plurality of second units selectively formed on a surface portion of a first semiconductor layer of a first conductivity type; The second semiconductor layer of the conductive type is a first semiconductor layer of the first conductive type formed on at least one of the surface portions of the plurality of second semiconductors of the second conductive type • 76- (9) 200308096 layer, and A plurality of main electrodes connected to the second semiconductor layer of the second conductivity type and the third semiconductor layer of the at least one first conductivity type; and the second unit: at least including: selectively The second semiconductor layer of the second conductivity type formed on the surface portion of the first semiconductor layer of the first conductivity type is provided between the second semiconductor layer of the second conductivity type and adjacent to the second semiconductor layer of the second conductivity type. The fifth semiconductor layer of the second conductivity type has a lower impurity concentration than the second semiconductor layer of the plurality of second conductivity types. 3 2 · The insulated gate semiconductor device according to item 31 of the scope of patent application, wherein the second unit is provided with the fifth semiconductor layer of the second conductivity type, which can completely cover the second conductive layer adjacent to the second conductive type. The surface portion of the first semiconductor layer of the first conductivity type between the second semiconductor layers of the metal type. 3 3. The insulated gate type semiconductor device according to item 31 of the scope of patent application, wherein the second unit further includes: a first main electrode connected to the plurality of second semiconductor layers of the second conductivity type, or separately A third semiconductor layer of the i-th conductivity type formed on at least one of the surface portions of the second semiconductor layer of the plurality of second conductivity types, and a second semiconductor layer connected to the plurality of second conductivity types and the at least one The first main electrode of the first semiconductor layer of the first conductivity type and the third semiconductor layer. 3 4 · If the insulated gate type semiconductor device according to item 31 of the scope of patent application, the length of the control electrode of the second unit or the interval between adjacent second semiconductor layers of the second conductivity type is longer than that of the first unit. The length of the control electrode or the distance between the adjacent second semiconductor layers of the second conductivity type is large. -77- (10) 200308096 3 5 · If the insulation gate type d of the first item of the patent application scope is adjacent to the second The p of the second semiconductor layer of the conductivity type is higher than that of the first semiconductor layer of the first conductivity type, and the low-resistance layer of the first conductivity type, and the fifth semiconducting quality of the at least one second conductivity type (Np ), And the sum of the surface area (Apl) of the at least one second conductivity type body layer and the {area (Ap2) of the first conductivity type and the fifth half product (Apl) of the at least one second conductivity type ( Apl + Ap2) ratio (Ap = Apl / has a relationship of 0 &lt; Np &lt; 9xl01 VAp + l .2xl012cm'2 〇3 6. If the insulated gate type of the patent application scope No. 35 is half of the above at least one of the second conductive type fifth semiconductive bone mass (Np), and at least one of the above The ratio of the surface area (Apl) of the second conductive type body layer to the area (Ap2) of the first conductive type and the sum of the fifth half H product (Apl) of the at least one second conductive type (Apl + Ap2) ( The relationship Ap = Apl / is a conductor device, and it is further provided with the surface of the surface layer of the 5th semiconducting resistive layer with an impurity concentration layer Ap1 + Ap2) the conductor device, and the 5th semiconducting layer of the effective impurity: The surface of the resistance layer: the surface of the bulk layer: Ap1 + Ap2) -78- (11) (11) 200308096 Np> 2.5xl0n / Ap + 5.3xl011cm'2. 37. In the case of the insulated gate semiconductor device according to item 1 of the scope of patent application, a second semiconductor layer having a higher conductivity than the first semiconductor layer of the first conductivity type is provided between adjacent second semiconductor layers of the second conductivity type. The low-resistance layer of the first conductivity type of the impurity concentration, the effective impurity amount (Np) of the fifth semiconductor layer of the at least one second conductivity type, and the surface area of the fifth semiconductor layer of the at least one second conductivity type ( Apl) to the ratio (Apl + Ap2) of the surface area (AP2) of the low-resistance layer of the first conductivity type and the surface area (Apl) of the fifth semiconductor layer of the at least one second conductivity type (Apl / (Apl) + Ap2) and the distance (Lj) between the adjacent second semiconductor layer of the second conductivity type is 0 &lt; Np &lt; Np / Nj &lt; l .7xl015 / Ap + 2xl015cnT3 3 8. If the insulated gate semiconductor device of the 37th scope of the patent application, the effective impurity amount (Np) of the at least one second conductive type fifth semiconductor layer, and at least the above The surface area (Apl) of the fifth semiconductor layer of one second conductivity type and the surface area (Ap2) of the low-resistance layer of the first conductivity type and the surface area (Apl) of the fifth semiconductor layer of the at least one second conductivity type The ratio of the sum of (Apl + Ap2) (Ap = Apl / (Apl + Ap2) • 79- (12) 200308096 and the relationship between the interval (Lj) of the adjacent second semiconductor layer of the second conductivity type is Np /Lj&gt;4.29xl014/Ap + 8.8x10Mcm · 3. 3 9 · If the insulated gate semiconductor device of the first patent application scope is provided, it is further provided between adjacent second semiconductor layers of the second conductivity type. A low-resistance layer of the first conductivity type having a higher impurity concentration than the first semiconductor layer of the first conductivity type, an effective impurity amount (Np) of the fifth semiconductor layer of the at least one second conductivity type, and The surface area (Apl) of the fifth semiconductor layer of the at least one of the second conductivity type and the above The ratio of the surface area (Ap2) of the low-resistance layer of the first conductivity type and the sum of the surface area (Apl) of the fifth semiconductor layer of the at least one second conductivity type (Apl + Ap2) (Apl / (Apl + Ap2), The relationship with the junction depth (Xj) of the adjacent second semiconductor layer of the second conductivity type is 0. &lt; Νρ &lt; Νρ · Xj &lt; 3.6 x 1 0 8 / Ap + 4.8 X 1 0 8 cm'1. 40. If the insulated gate semiconductor device according to item 39 of the patent application 'the effective impurity amount (Np) of the at least one second conductive type fifth semiconductor layer and the at least one second conductive type fifth semiconductor The surface area (Apl) of the layer and the surface of the low-resistance layer of the first conductivity type -80- (13) (13) 200308096 product (Ap2) and the surface area of the fifth semiconductor layer of the second conductivity type (Apl) ) And (Apl + Ap2) ratio (Apl / (Apl + Ap2)) and the junction depth (Xj) of the adjacent second semiconductor layer of the second conductivity type is Np · Xj &gt; lxl08 / Ap -f2.1xl08cm'1. 4 1 · If the insulated gate semiconductor device according to item 1 of the scope of patent application, a second semiconductor layer having a higher conductivity than the first semiconductor layer of the first conductivity type is provided between adjacent second semiconductor layers of the second conductivity type. The low-resistance layer of the first conductivity type with a low impurity concentration, the effective impurity amount (Np) of the fifth semiconductor layer of the at least one second conductivity type, and the surface area of the fifth semiconductor layer of the at least one second conductivity type The ratio (Apl) to the sum of the surface area (Ap2) of the low-resistance layer of the first conductivity type and the surface area (Apl) of the fifth semiconductor layer of the at least one second conductivity type (Apl + Ap2) (Ap = Apl) The relationship between / (Apl + Ap2) and the interval (Lj) between the adjacent second semiconductor layer of the second conductivity type and the junction depth (Xj) of the adjacent second semiconductor layer of the second conductivity type is 0 &lt; Np &lt; Np · Xj / Lj &lt; 6 X 1 0 11 / Ap + 8 X 1 0 1 1 c m'2. (14) (14) 200308096 42. If the insulated gate semiconductor device of item 41 in the scope of patent application, the ratio of (Apl) to (Apl + Ap2) (Ap = Ap 1 / (Ap 1 + Ap2), and phase The relationship between the distance (Lj) between adjacent second semiconductor layers of the second conductivity type and the junction depth (Xj) between adjacent second semiconductor layers of the second conductivity type is: at least one of the second conductivity types The effective impurity amount (Np) of the fifth semiconductor layer, the surface area (Apl) of the fifth semiconductor layer of the at least one second conductivity type, the surface area (Ap2) of the low-resistance layer of the first conductivity type, and the at least one The ratio of the surface area (Apl) and (Apl + Ap2) of the fifth semiconductor layer of one second conductivity type (Ap = Apl / (Apl + Ap2)) to the adjacent second semiconductor layer of the second conductivity type The relationship between the interval (Lj) and the junction depth (Xj) of the adjacent second semiconductor layer of the second conductivity type is: Np · Xj / Lj &gt; 1 · 7x 1 0 1 1 / Ap + 3. 5 X 1 0 1 1 cm · 2. 4 3. If the insulated gate semiconductor device of the first patent application scope is between the adjacent second semiconductor layers of the second conductivity type A low-resistance layer of the first conductivity type having a higher impurity concentration than the first semiconductor layer of the first conductivity type, and an effective impurity amount (Np) of the fifth semiconductor layer of the at least one second conductivity type is further provided. , The effective impurity amount (Nn) of the low-resistance layer of the first conductivity type, and the fifth semiconductor-82 · (15) 200308096 of the at least one second conductivity type of the above-mentioned layer and the first conductivity of the first conductivity type The low-resistance f-product (Ap 2) of the type and the ratio (Ap Apl + Ap2) of the sum of the surface area (Apl) of the second conductive type of at least one of the above (Apl + Ap2) are 0. &lt; Np &lt; Np &lt; 8.4 X 10M / Ap + 0.34Nn + 0.015Nn / Ap-1.2 x 44 · If the insulated gate type semiconductor of the 43rd scope of the application for patent, at least one of the above-mentioned fifth conductive layer of the second conductivity type &amp; quality (Nρ ), The narrow amount (Nη) of the low-resistance layer of the first conductivity type, the surface area (Apl) of the fifth layer of the at least one second conductivity type, and the low-resistance product (Ap2) of the first conductivity type. And the relationship between the surface area (Apl) and the (Apl + Ap2) ratio (Ap: Apl + Ap2) of at least one of the second conductivity type and the fifth is Np &gt; -4xl01 ° / Ap + 0.0375Nn + 0.075Nn / Ap + 4xl011cm · 2 45. If the insulated gate type semiconducting bone in item 1 of the scope of patent application is more adjacent to the second semiconductor layer of the second conductive type than the first conductive type 1 The semiconductor layer is a high-impurity, low-resistance layer of the conductivity type, and the at least one of the above-mentioned fifth conductivity layer of the second conductivity type is a white surface conductor layer Apl / (0 1 1 c m'2 device, I effective miscellaneous Surface of impurity semiconductor: conductor layer = Αρ1 / (device, there is a degree of effective impurity -83- (16) (16) 200308096 mass (Np), and The effective impurity amount (Nn) of the low-resistance layer of the first conductivity type and the surface area (Apl) of the fifth semiconductor layer of the at least one second conductivity type and the surface area (Ap) of the low-resistance layer of the first conductivity type are described. 2) and the ratio of the surface area (Apl) of the fifth semiconductor layer of the second conductivity type and at least one of the above (Apl + Ap2) (Ap = Apl / (Apl + Ap2)) and the adjacent second conductivity type The relationship of the interval (Lj) of the second semiconductor layer is 0 &lt; Np &lt; Np / Lj &lt; 1.4xl015 / Ap + 570Nn + 25Nn / Ap-2xl014cm ° 46. For an insulated gate semiconductor device having a patent application scope of item 45, the effective impurity amount of the at least one second conductive type fifth semiconductor layer (Np ), The effective impurity amount (Nil) of the low-resistance layer of the first conductivity type, and the surface area (Apl) of the fifth semiconductor layer of the at least one second conductivity type, and the The ratio of the surface area (AP2) and the sum (Apl + Ap2) of the surface area (Apl) of the fifth semiconductor layer of at least one of the second conductivity types (Ap = Apl / (Apl + Ap2)) and the adjacent second The relationship between the distance (Lj) of the conductive second semiconductor layer is Np / Lj> -6.7 X 1 0 13 / Ap + 62.5Nn + 1 2 5Nn / Ap + 6.7 x 1014cm ': -84- (17) 200308096 4 7 · If the insulated gate semiconductor device according to item 1 of the scope of patent application, a second semiconductor layer having a higher conductivity than the first semiconductor layer of the first conductivity type is provided between adjacent second semiconductor layers of the second conductivity type. The low-resistance layer of the first conductivity type with an impurity concentration is effective for the fifth semiconductor layer of the at least one second conductivity type. The mass (Np), the effective impurity mass (Nn) of the low-resistance layer of the first conductivity type, and the surface area (Apl) of the fifth semiconductor layer of the at least one second conductivity type are lower than those of the first conductivity type. The ratio of the surface area (Ap 2) of the resistance layer and the sum (Apl + Ap2) of the surface area (Apl) of the at least one second conductivity type fifth semiconductor layer (Ap = Apl / (Apl + Ap2)) The relationship between the interval (Lj) of the second semiconductor layer of the second conductivity type and the junction depth (Xj) of the adjacent second semiconductor layers of the second conductivity type is 0. &lt; Νρ &lt; Νρ · Xj / Lj &lt; 5.6xl011 / Ap + 0.22 8Nn + 0.01Nn / Ap-8x 1010 cm'2. 48. In the case of an insulated gate type semiconductor device according to item 47 of the scope of patent application, the effective impurity amount (Np) of the at least one second conductivity type fifth semiconductor layer and the above-mentioned first conductivity type low resistance layer Mass (Nn), and the surface area (Apl) of the fifth semiconductor layer of the second conductivity type and the surface area (Ap2) of the low-resistance layer of the first conductivity type and the second conductivity type of the at least one 5 The ratio of the surface area (Apl) and (Apl + Ap2) of the semiconductor layer (Ap = Apl / (-85- (18) (18) 200308096 Apl + Ap2)) and the adjacent second conductive type second The relationship between the interval (Lj) of the semiconductor layers and the junction depth (Xj) of the adjacent second semiconductor layer of the second conductivity type is Np · Xj / Lj &gt; -2.7xl010 / Ap + 0.025Nn + 0.05Nn / Ap + 2.7xl0n 4 9 · If the insulated gate semiconductor device of the first scope of the patent application, wherein the second semiconductor layers of the plurality of second conductive types are arranged in a grid, and correspond to the plurality of second semiconductor layers The aforementioned control electrodes are disposed between the second semiconductor layers of the conductive type. 5 〇 · If the scope of patent application is 49. The insulated gate semiconductor device according to item 9, wherein the control electrode includes a first control electrode having at least one of the first electrode lengths and a second control electrode having at least one of the second electrode lengths. The insulated gate-type semiconductor device according to item 1, wherein the control electrode includes a first control electrode having at least one electrode length and a second control electrode having at least one second electrode length. The at least one second control layer of the second conductivity type corresponding to the first control electrode of at least one electrode length is provided with the at least one second conductivity type fifth semiconductor layer between the two. The insulated gate semiconductor device -86- (19) 200308096 of the scope of application for patent No. 51, wherein the first electrode length of the first control electrode is longer than the second electrode length of the second control electrode. 5 3 · For example, the insulated gate semiconductor device of the 51st scope of the patent application, in which at least one of the fifth semiconductor layer of the second conductivity type is selectively provided on the corresponding The second semiconductor layers of the plurality of second conductivity types described above are between each other. 5 4 · As the insulated gate type semiconductor device of the scope of application for patent No. 50, the control electrode has a length of the second electrode. At least one of the second control electrodes has a split gate structure or a table gate structure. 5 5. The insulated gate type semiconductor device according to item 1 of the patent application scope, wherein the control electrode includes a first control having at least one of the first electrode lengths. And at least one second control electrode having a second electrode length, and only the second semiconductor layer of the second conductivity type corresponding to the plurality of second conductive layers corresponding to the i-th control electrode having at least one of the first electrode lengths. A fifth semiconductor layer of at least one of the second conductivity type is provided therebetween, and only the second of the plurality of second conductivity types corresponding to the second control electrode having at least one of the second electrode lengths is provided. The surface layer of the semiconductor layer is provided with a third semiconductor layer of at least one of the first conductivity type. 56. The insulated gate semiconductor device according to item 1 of the scope of patent application, wherein the control electrode includes a first control electrode having at least one length of the first electrode and a second control electrode having at least one length of the second electrode, In addition, only at least one of the plurality of second conductive type second semiconductor layers corresponding to the second -87- (20) 200308096 control electrode having at least one of the second electrode lengths is provided with each other. 5th semiconductor layer of the second conductivity type 〇 5 7 · If the insulated gate semiconductor device of the scope of application for the patent No. 55, there is more between the adjacent second semiconductor layer of the second conductivity type has a The first semiconductor layer of the first conductivity type is a low-resistance layer of the first conductivity type provided with a high impurity concentration. The control electrode includes a first control electrode having at least one of the first electrode lengths and a second electrode length. At least one of the second control electrodes has only the second semiconductor layer of the second conductivity type corresponding to the plurality of second control electrodes having at least one of the second electrode lengths. The fifth semiconductor layer of the second conductivity type having at least one of the above is provided between each other, and only in the second of the plurality of second conductivity types corresponding to the first control electrode having at least one of the first electrode lengths. The seventh semiconductor layer of the first conductivity type having a lower impurity concentration than the low-resistance layer of the first conductivity type is provided between the semiconductor layers. 5 8 · If the insulated gate semiconductor device according to item 5 of the scope of patent application, the control electrode includes a first control electrode having at least one first electrode length and a second control electrode having at least one second electrode length , Only the second semiconductor layer of the second conductivity type of the plurality of second conductivity types corresponding to the second control electrode having at least one of the second electrode lengths is provided with the at least one second conductivity type of the fifth semiconductor layer. (88) (21) 200308096 The semiconductor layer is provided only on the surface portion of the plurality of second conductive type second semiconductor layers corresponding to the plurality of first control electrodes having at least one of the first electrode lengths. The third semiconductor layer of the first conductivity type. 5 9 · The insulated gate type semiconductor device according to claim 50 of the patent application scope, wherein the control electrode, the first control electrode having at least one of the first electrode lengths, and the second control electrode having at least one of the second electrode lengths The control electrode system is provided in a line shape. 60. The insulated gate semiconductor device according to claim 50, wherein the control electrode, the first control electrode having at least one of the first electrode lengths, and the second control having at least one of the second electrode lengths The electrode system is provided in a grid shape. 61. The insulated gate type semiconductor device according to item 49 of the scope of patent application, wherein the control electrode is provided with a plurality of control electrodes, the first control electrode portion having at least one of the first electrode lengths, and the second control electrode portion having a second electrode length. A second control electrode portion of at least one of the electrode lengths. 6 2 · The insulated gate semiconductor device according to item 61 of the patent application scope, wherein the plurality of control electrodes are arranged in a line shape. 63. The insulated gate semiconductor device according to item 61 of the patent application range, wherein the plurality of control electrodes are arranged in a grid shape. 64. The insulated gate type semiconductor device according to item 63 of the application, wherein the plurality of control electrodes include a first control electrode portion having at least one of the first electrode lengths and a first control electrode portion having at least one of the second electrode lengths. The second control electrode section. 6 5. An insulated gate semiconductor device, characterized in that: -89- (22) (22) 200308096 is provided with: a first unit: at least including: a first semiconductor selectively formed in a first conductivity type The second semiconductor layer of the second conductivity type on the surface portion of the layer is a third semiconductor layer of the first conductivity type formed on at least one of the surface portions of the plurality of second semiconductor layers of the second conductivity type. And a plurality of main electrodes connected to the second semiconductor layer of the plurality of second conductivity types and the third semiconductor layer of the at least one first conductivity type; and the second unit: at least includes: a selection Sexually formed in the above! The second semiconductor layer of the second conductivity type on the surface portion of the first semiconductor layer of the conductivity type is provided between the second semiconductor layer of the second conductivity type adjacent to the second semiconductor layer of the second conductivity type and has a plurality of The second semiconductor layer of the second conductivity type is a fifth semiconductor layer of the second conductivity type having a low impurity concentration, and the first semiconductor layer of the first conductivity type is provided with a first semiconductor layer having a higher conductivity than the first conductivity type. The low-resistance layer of the first conductivity type having a high impurity concentration is provided between the second semiconductor layer of the second conductivity type adjacent to the first cell and has a low-resistance layer having a higher conductivity than the first conductivity type. The seventh semiconductor layer of the first conductivity type having a low impurity concentration. 6 6 · If the insulated gate semiconductor device according to item 65 of the scope of patent application, wherein the control electrode length of the above two units or the interval between adjacent second semiconductor layers of the second conductivity type is more controlled than that of the first unit The electrode length or the distance between adjacent second semiconductor layers of the second conductivity type is small. 67. For example, the insulated gate semiconductor device -90- (23) (23) 200308096 'where the aforementioned first unit is further provided between adjacent second semiconductor layers of the second conductivity type There is a fifth semiconductor layer of the second conductivity type having a lower impurity concentration than the second semiconductor layer of the second conductivity type. 6 8 · In the case of the insulated gate semiconductor device according to item 65 of the patent application, wherein the second unit further includes: a main electrode connected to the second semiconductor layer of the plurality of second conductive types, or The third semiconductor layer of the first conductivity type is formed on at least one of the surface portions of the second semiconductor layer portion of the plurality of second conductivity types, and the second semiconductor layer of the second conductivity type is connected to the plurality of second conductivity types. The first to third electrodes of the semiconductor layer and the at least one first conductivity type third semiconductor layer. 69 · An insulated gate type semiconductor device, comprising: a first semiconductor layer of a first conductivity type; a first semiconductor layer provided on the first conductivity type; The first semiconductor layer is a low-resistance layer of the first conductivity type having a high impurity concentration; a plurality of second semiconductor layers of the second conductivity type are selectively formed on a surface portion of the low-resistance layer of the first conductivity type; A third semiconductor layer of the first conductivity type formed on at least one of the face portions of the second semiconductor layer of the plurality of second conductivity types; a second semiconductor layer of the second conductivity type and a second semiconductor layer connected to the plurality of second conductivity types; and A plurality of first main electrodes of the at least one first conductivity type third semiconductor layer; -91-(24) (24) 200308096 formed on the back side of the first conductivity type third semiconductor layer A fourth semiconductor layer; a second main electrode connected to the fourth semiconductor layer; a second semiconductor layer of the plurality of second conductivity types formed through a gate insulating film; 3 semiconductor layer, and the first The control electrode on each surface of the conductive low-resistance layer and the low-resistance layer provided on the first conductive type are connected to adjacent second semiconductor layers of the second conductive type, respectively, and have more than the above. The second semiconductor layers of the second conductivity type are a plurality of fifth semiconductor layers of the second conductivity type having a low impurity concentration. The low-resistance layer of the first conductivity type is a seventh semiconductor layer of the first conductivity type having a low impurity concentration. 7 〇 · An insulated gate-type semiconductor device, comprising: a first semiconductor layer of a first conductivity type; and a first semiconductor layer provided on the first conductivity type and having a higher conductivity than the first conductivity type. The first semiconductor layer is a low-resistance layer of the first conductivity type having a high impurity concentration; a plurality of second semiconductor layers of the second conductivity type are selectively formed on a surface portion of the low-resistance layer of the first conductivity type. A third semiconductor layer of the first conductivity type formed on at least one of the surface portions of the second semiconductor layer of the plurality of second conductivity types; a second semiconductor layer of each of the plurality of second conductivity types connected to the second semiconductor layer; A plurality of first main electrodes of -92- (25) (25) 200308096 and at least one of the first conductivity type third semiconductor layer; formed on the back surface of the first conductivity type first semiconductor layer A fourth semiconductor layer on the side; a second main electrode connected to the fourth semiconductor layer; a second semiconductor layer formed on the plurality of second conductivity types via a gate insulating film, and at least one of the first conductivity types The third semiconductor layer, and the above The control electrode on each surface of the low-resistance layer of the one-conductivity type and the first semiconductor layer provided on the first-conductivity type are connected to the second semiconductor layers of the plurality of second-conductivity types, respectively, and have a higher value than the above. The plurality of second semiconductor layers of the second conductivity type are a plurality of second semiconductor layers of the second conductivity type having a low impurity concentration. 7 1 · The insulated gate semiconductor device according to item 70 of the scope of patent application, wherein the plurality of second semiconductor layers of the second conductivity type are arranged in a grid shape, and the plurality of second semiconductor layers of the second conductivity type are arranged in a grid shape. The semiconductor layer is provided between four adjacent second semiconductor layers of the second conductivity type. 7 2 · The insulated gate semiconductor device according to item 71 of the scope of patent application, wherein the plurality of fifth semiconductor layers of the second conductivity type are locally connected, respectively. 73. If the insulated gate semiconductor device according to item 70 of the patent application scope, wherein the third semiconductor layer of the first conductivity type of the above-mentioned one is provided only in addition to the fifth semiconductor of the second conductivity type connected to the plurality of above-mentioned ones, respectively Location of layer -93-(26) 200308096 The surface portion of the second semiconductor layer of the plurality of second conductivity types described above. 74. The insulated gate semiconductor device according to item 70 of the patent application, wherein the control electrode is arranged in a grid shape, and a portion corresponding to the first conductive type low-resistance layer has a split gate structure or a platform structure. 75. The insulated gate semiconductor device according to item 70 of the application, wherein the second semiconductor layers of the plurality of second conductivity types are arranged in a line shape * The fifth semiconductor layers of the plurality of second conductivity types are It is locally connected to the plurality of second semiconductor layers of the second conductivity type. -94-