SU999039A1 - Reflected binary to positional binary code converter - Google Patents

Description

(54) TRANSFORMER OF REFLECTED BINARY CODE TO POSITIVE BINARY CODE N BACK

one

The invention relates to automation and digital computing and can be used in the construction of measurement systems and control systems.

A device is known for converting a reflected binary code into a positional binary code containing delay elements, AND, OR, AND IS-NOT triggers and shapers in bit 1.

A disadvantage of the known device is the low speed and the impossibility of the inverse transformation.

The closest solution to this problem by technical essence and circuit construction is a binary code converter into the Gre code and vice versa, comparing the register of triggers with counting inputs of the group, formers, And elements and delay elements 2,

. A disadvantage of the known device is the low speed, since the conversion to the (p-1) stage, each of which includes the sum of the trigger times, the driver, the AND element and the delay time and the signal by the delay element.

The aim of the invention is to increase the speed of the video.

The goal is achieved by the fact that in a converter of a reflected binary code into a positional binary code and back containing a register and the first group of elements AND whose first inputs are connected to the control input of the converter whose outputs are register outputs, the unit input of the n-th bit and which is connected to the input of the higher bit of the converter, where n is the number of bits of the code being converted, the second and

15 is a third of a group of n-1) -th element AND a group of (n-2) half-adders, with the i-th half-adder (i l-r n-1) having (i + 1) inputs and the element NOT, whose input is a gate input

20 of the converter and connected to the first inputs of elements AND of the second group, the second inputs of which are connected to the inputs of the corresponding bits of the converter, and the outputs of the i-element of AND

25 of the second and third groups, respectively, with the unit and counting inputs of the corresponding register bits, the first inputs of the AND elements of the third group are connected to the output of the element NOT,

30, the second input of the j-th (j 1 p-2J of the threw And of the third group is connected to the output of the j -th half-adder of the group, the first input of which is connected to the input of the (j +1) -th bit of the converter, the second input of the j -th element And the first the group is connected to the input of the (j +2) -th 5th digit of the converter, the second input of the (nl) -ro element AND of the third group is connected to the input of the n-th bit of the converter and the second input of the (n-2) -th element of the first group , output - j 10 of the element And the first group is connected by the +1) -th inputs from the first to the) -th half-adders of the group.

Pa drawing shows a block diagram of the proposed reflected binary 15 code in the positional binary code and vice versa.

The converter contains a register 1, which includes triggers 2, special 3, second 4 and third 5 groups of элементов elements I, group b of half-summers, inverter 7, gating inputs, control input 9 and inputs Nf.

The Converter of the reflected binary code in the positional binary code 25 and back works as follows.

In the initial state, all the triggers 2) of Register 1 are in the zero state, at the information inputs N (N (low potentials, at the gate, 8) high potential, at the outputs of the And 4, And 5 and semi-sum / low potential b. The code to be converted is written into triggers 2 of register 1, into the most significant bit directly, and into the remaining 35 bits through AND 4 elements opened on the first inputs by a single potential from the gate input 8. The state of the triggers 2 changes to bit in which the code is equal to one. Inputs of half-summers of an odd number of units, unit potentials appear on their voltages. To convert the reflected binary code into a positional binary code 45, a single potential must be applied to the control input 9 for the entire time of the conversion. Register 1 is reversed in those bits eaten with respect to which in the higher bits there is an odd number of units in the source code. In order to convert the positional binary code into the reflected binary code, it is necessary to apply a zero potential to the control input 9 for the entire conversion time. As a result, zero potentials are set at the outputs of the And 3 elements. In this case, the state of the flip-flops 2 in the register 1 is changed to be opposite to 60 in those bits with respect to which: in the neighboring most significant bit there is a unit in the source code. In order to obtain the maximum speed of an e-bess in the service

In addition, if the response time t of the half-adder B of the lower-order bit is longer than the time t-j of the trigger 2, the time t from the moment the source code is supplied until the gate of the potential of the potential is determined by the expression t + t ,, where tya is the time of the element I 3.

The conversion burden Tpr for this case is defined by

Tpr t + tng + tv, s + t, where the response time of the inverter 7; tyc - element response time

And 5.

In order to obtain the maximum speed of the converter in case time t t. ,, time t is determined

- It is supposed that it is necessary to convert the four-digit reflected-binary code 1010 (which corresponds to the number of twelve in the decimal system) to a positional binary code. Upon receipt of the source code 1010 in the high and in the second bits of the register 1. Triggers 2 are set to one, and the original shaft will be written in the register. A single potential input to the higher-order input will cause the appearance at the output of an I 3 element of a single potential, which, having entered the other input of the half-adder b of the second discharge, will trigger it since there is zero potential at the first input of it N. Semi-Aced / Piator 6 of the first digit does not work, since there are an even number of units in its inputs. After time t, after supplying the source code to the gating input 8, a zero voltage is applied, closing .1И 4 at the first input. The unit potential from the output of the inverter 7, entering the first inputs of the And 5 elements, will trigger those of them, at the second inputs which there is a single potential. In this case, the unit potential from the output of the And 5 elements in the second and third bits will set the triggers 2 to the opposite state, as a result of which the position code 1100 appears in the register (in the Electrical system T-12).

Consequently, when converting a reflected binary code to a positional binary code, the state of the flip-flops in the register changes to the opposite in those bits in which the half-adder is triggered when there is an odd number of units in all the senior ones in relation to this bit of the source code;

Claims (2)

Thus, if there is a single potential at the control input in the converter, the mode of converting the reflected binary code to the positional binary code is set up, which provides for one conversion step, including the state of triggers of those bits in relation to which in the higher bits of the original The code has an odd number of units. The speed of the converter is limited only by the time of propagation of the signal on the two elements AND, the semi-adder, the inverter and the switching time of the trigger. Suppose you need to convert a four-bit position code 1101 (thirteen) into a reflected binary code. Since a single signal of the information input Nj is supplied to the first input of the half adder 6 of the second discharge, and there is zero potential on the other part of it, the output of the half summat b appears to be a single potential. At the output of the half adder 6 of the first discharge, the zero potential continues to remain, due to the presence of zero potentials at its input. dah. Time t after the source code has been applied to the gate input 8, a zero potential is applied, covering the elements AND 4 at the first input. A single potential from the output of the inverter 7 will lead to the operation of those elements And 5, on the second inputs of which there is a single potential. In this case, the unit potential from the output of the elements And 5 in. the second and third bits will set triggers in the opposite state, as a result of which the reflected binary code 1011 {in the decimal system -13) appears in the register. Consequently, when converting a positional binary code in a reflected binary code, the state of the flip-flops in the register changes in those bits in which the half-adder is triggered when there is a unit in the next bits of the source code. . Thus, if there is a zero potential at the control input in the converter, the mode of converting the positional binary code into the reflected binary code is set, which provides one conversion step. The design features of the proposed technical solution allow to increase the speed of the converter, as the conversion of the reflected binary code the positional BINARY code occurs in one step, which includes writing to the source code register and changing to the opposite state triggers of those bits, with respect to which in the higher bits of the source code has an odd number of ones. The conversion time, in general, is defined as the sum of the two response times of the elements And, the response time of the semi-augers (at the younger, the response time of the inverter and the switching time of the trigger. The proposed converter can be built as a purely combinational device, for which converter inputs must be connected to additional inputs of half-summers. In this case, the need for triggers and elements of AND 5 is no longer necessary, and the speed of the converter is increased. Neither a reflected binary code converter into a position binary code and vice versa containing a register and a first group of elements AND whose first inputs are connected to a control input of a converter whose outputs are register outputs whose unit input of the nth digit is connected to the higher-order input Yes, the converter, where p is the number of bits of the code being converted, characterized in that, in order to increase speed, the second and third groups of the (n-1) -th element AND, the group of- (p-2) half adders, are entered into it, with the i-th the accumulator (1 1 t n-1) has (i + 1) inputs. And the element, whose input is the gate input of the converter, is connected to the first inputs of elements AND of the second group, the second inputs {which are connected to the inputs of the corresponding bits of the converter, and the outputs of the i-ro element of the second and third groups, respectively, with the single and counting inputs of the corresponding register bits; the first inputs of the AND elements of the third group are connected to the output of the CB element, the second input of the (j 1 -g n -2) element And the third group is connected to the output of the j -th half-sum Group RA. the first input of which is connected to the input of the (i-I) -th bit of the converter, the second input of the j-th element of the first group is connected to the input of the (+2) -th bit of the converter, the second input of the (n-1) -th element of I the third group is connected to the input of the n-th bit of the maker, and the second input of the (n-2) -th element of the first group, the output of the jth element of the first group of the first group is connected to the (j -I) -th inputs from the first by j th semi-adders group. Sources of information taken into account in the examination 1. The author's certificate of the USSR. No. 369706, cl. H 03; K 13/24, 08.11.73. 2. USSR author's certificate number 560222, cl. G 06 F 5/02, 30.05.77, (prototype).