SU970474A1 - Analog memory device - Google Patents

Description

(54} ANALOG STORAGE DEVICE

one

The invention relates to automation and computing and can be used to store and process analog signals.

An analog storage device (AMS) is known, which contains an operational amplifier, to the output of which a storage capacitor and a voltage follower Cll are connected via two series-connected switches.

The closest to the technical essence of the invention is the ABC, containing two storage elements connected through the first and second keys to the input of the device and through the first and third repeaters, and the subtracting unit to the drying unit, the output of which is connected to the second repeaters) voltage 2.

The disadvantage of the known devices. is the distortion of the amplitude of the memory signal by the key control signal that creeps into the memory capacitor through the capacitance between the control input and the key output.

The purpose of the invention is to increase the memory accuracy of the input / O signal.

The goal is achieved by the fact that in an analog storage device containing the first and second accumulative elements, for example, capacitors, the first plates of which are connected to the zero potential bus, the second plates are connected to the outputs of the first and second Q keys, the inputs of which are combined and are the input of the device, the second plate of the second capacitor is connected to the input of the voltage follower, the output of which is connected to the first input of the adder, the second plate of the first capacitor is connected to the second input an adder whose output is an output device.

The adder contains an operational amplifier whose output is

20 output of the adder, the first passive element, for example, the first resistor connected between the output and the inverting input of the amplifier, the second and third passive elements, for example

Claims (2)

25, the second and third resistors, one terminals of which are connected to the inverting and non-inverting inputs of the amplifier, respectively, the other terminals of which are respectively the first and second inputs of the adder. The drawing shows a functional diagram of the proposed CAM. The device contains the first and second switches 1 and 2, the first and second storage capacitors 3 and 4, the voltage follower 5, the adder b containing the operational amplifier 7 | and the first, second, third resistor. ry 8 - 10. The device operates as follows. In the zadi mode, the keys 1 and 2 are open and the input signal is fed to capacitors 3 and 4, which are charged to the amplitude of the input signal. From capacitor 4 through the voltage follower and resistor 9, the signal is fed to the inverter input of the operational amplifier, from capacitor 3 through a resistor 10 - to a non-inverted input, the voltage of the rta output of the amplifiers will be equal to U bix Ufex-1 and U (K ,, R8 where the gain of the amplifier in inverse R8 + k9 K is the gain of the amplifier in the non-inverted input ,, From formulas can be seen that with equal resistors 8 and 9 The gain t in the inverse ode is -1, and in the non-inverse input 2, the voltage at the output of the device will be U4x (-l) -t-Uex (2) Uj. In storage mode, keys 1 and 2 are closed and at the inputs of the amplifier Signals stored by capacitors 3 and 4 come in. When the device switches from recording mode to storage mode, storage capacitors 3 and 4 appear on the signal, whose value V is determined by the ratio of the internal capacitance values of the keys and storage capacitors. With equal capacities of switches 1 and 2, which is quite acceptable when the keys are identical, and the choice of the capacitance of the storage capacitor 4 is less than the capacitor 3, the propellant signal on the capacitor (2i4U) is twice as large as on the condenser 3 ( uU) "At the output of the amplifier in storage mode, in this case, the voltage will be equal to () 2) () - i.e. the propeller error will be fully compensated. l is provided by the choice of capacitance values of capacitors 3 and 4. In addition, the proposed device has a large storage time-information. It is achieved due to the fact that the signal arriving at. the non-inverter input of the amplifier decreases in time two times slower than at the inverse input, since the capacitance of the capacitor 3 is twice the capacity of the patea. The proposed device has a greater accuracy in memorizing the input signal while simultaneously preserving a large memorization time, which distinguishes it from known devices. 1. Analog storage device containing first and second storage elements — for example, capacitors, the first plates of which are connected i with a zero potential bus, the second plates with the outputs of the first and second keys, respectively, whose inputs are combined and are the input of the device, The second capacitor plate is connected to the input of the voltage follower, the output of which is connected to the first input of the adder, characterized in that, in order to increase the accuracy of the device, the second plate is not Vågå capacitor connected -c second input of the adder whose output is VYHODOMustroystva, 2. The device according to claim 1, wherein the adder contains an amplifier whose output is the output of cyivtMdTOpa, the first passive element, for example, the first resistor connected between the output and the inverting input of the amplifier, the second and the third passive elements, for example, the second and third resistors, some of which are connected to the inverting and non-inverting inputs of the amplifier, respectively, the other outputs of which are the first and second inputs of the adder, the sources of information taken into account during the examinations e 1. Author's certificate of the USSR 756484, class C. 11 C 27/00, 1978. 2, USSR Copyright Certificate No. 803013 class C. 11 C 27/00, 1979. (prototype).