SU964615A1 - Walsh function generator - Google Patents

Description

one

The invention relates to automation, and computing, in particular to discrete function generators, and can be used in information transmission and processing systems, in constructing spectrum anapizators, digital filters, synthesizers of complex signals.

A known Wopsch function generator, comprising a clock pulse generator, a counter, And elements, a modulo-two adder, and blocks for converting the code of Walsh functions into Gre 1 code.

The disadvantages of this generator in-. There are limited functionality, since it is not possible to implement the phase shift of the Walsh functions.

The closest technical solution to the invention is the Walsh function generator, which contains a clock pulse generator, two counters, elements AND | modulo two 2 J.

The disadvantage of the known Walsh function generator is that it generates a symmetric matrix of Walsh functions only if all control inputs have a logical, i.e. when ... Wed-1. For Other control sets, an asymmetric matrix is generated. However, when solving problems of information processing and spectral analysis of signals, it is desirable to have symmetric matrices (Walsh functions. So, the direct and inverse discrete 10 ftoe Fourier – Fourier transform of an arbitrary discrete function (i) is described in matrix form

V p wf,,

where f and F are the column vectors of the original

15 (function and its spectrum, respectively

  | tf (0), f (l), ..., f (H-1) | T

F} | F (C7), F (1), ...-, F (N-1) ir,.

VV is orthogonal function matrix

20 Wopsha size N N.

When W W i.e. when the matrix W is symmetric, the transition from the decomposition of the original function in the Walsh base to its reconstruction is much simpler, since the same matrix of Walsh functions is used. From the point of view of the hardware implementation, the use of a simcritical matrix W permits one to use the same Walsh function generator in the decomposition of the original signal and in its recovery. The invention is an extension of the functionality of the Walsh function generator, which is capable of generating symmetric matrices of Walsh functions. The delivered circuit is achieved by the fact that the Walsh generator functions, which contain a clock impulse generator, two n -digit counters (n is an order of the Wopsch function system), n And elements, a modulo two, and the output of the clock generator is connected to the count input the first counter, (21-1) th and 2i-th, where i l- (nl), the control inputs of the generator of the WOGa function are connected respectively to the first and second control inputs of the i-ro bit of the first counter (2n-1) control signal input terminal of the function of the device is connected to the control input -g The first counter, the outputs of the same bits of the first second counter are connected to the inputs of the corresponding element AND, the outputs of the elements AND are connected to the inputs of the adder modulo two, the output of which is the output of the WalsH function generator, contains n -1 elements OR, and the first input of the first element OR is connected to the inverse output of the first bit of the first scracchik, the first input of the i-ro element OR, except the first element OR, is connected to the output (il) -ro of the element OR, the second input of the 1st element OR is connected to the additional you during the (1 + 1) -th bit of the first counter, the output (n-l) -ro of the element OR is connected to the counting input of the second counter, the control inputs of the bits of the second counter are connected to the control inputs of the same bits of the first counter. In addition, the first bit of the first and second counters consists of a trigger and two modulo adders, the inverse output of the trigger is connected to its information input and to the first inputs of the first and second modulators two, the second inputs of which are the first and second the control input of the first bit, the bit of the first and second counters, where 54 j-2-f (nl), consists of a trigger, three modulo two modulators and an AND element, with the inverse trigger output of the jth bit connected to the first inputs of the first and second amounts modulators are two 3rd bits, the second inputs of the first and second adders modulo two j-th bits are respectively the first and second control inputs of the j-th digit of the counter, the outputs of the first and second modulators are two j -th bit is connected to the first inputs of the third modulo-two adder and the element AND the j-th bit, the output of the third adder is two j-th bits and is an additional output of the j-th bit and is connected to the information input of the trigger j- ro bit, n th bit of the first and second counters consists of three of a two-modulator and two adders modulo two, the inverse of the output of the n-th trigger flush to the first input of the first modulo-two adder, the second input of the modulator of the two n-th digit is the control input of the n-th digit the corresponding counter, the output of the first modulo two nth digit is connected to the first input of the second modulo modulator of the two nth digit, the output of which is an additional output of the nth digit of the corresponding counter and connected to the information input flip-flop trigger a, you-s moves of the first and second adders modulo two of the first bit in each of the counters are connected to the second inputs of the third adder respectively, modulo two and the second bit element, the output of the element AND the R -th bit, where R is 24 (p-2), is connected to the second inputs of the third adder modulo two and epementa And (R + l) -ro bit, the output of the element And (nl) -ro bit is connected to the second input of the second adder modulo two n- bits, the trigger outputs of all bits are the bits of the corresponding counters, the clock inputs of all m The riggers contained in the meter are combined and connected to the counting input of the corresponding meter. The drawing shows a functional diagram of the Walsh function generator, the Device contains 1 clock pulse generator, n-bit counters 2 and 3, adders 4 modulo two, elements AND 5, elements OR 6, elements And 7, adder 8 modulo two, trig - heres 9. The corresponding control inputs of counters 2 and 3 are interconnected and are the control inputs of the generator .... The device operates as follows. Before operation, counters 2 and I are reset. The binary code received from counter 3 controls the transmission of the binary code, r. irrated by counter 2, to the input of the adder 8 modulo two through the elements of AND 7. At the output of cyMiviaTopa 8 modulo two, Walsh functions with shifted phases are formed, forming a symmetric matrix. The phase shift of the functions of the GPS and the order of their following can be controlled by changing the state of the control inputs of the generator. Thus, for three-bit counters 2 and 3, when the counters generate a code where a v | - junior, and 1 - most significant bits of counters 2 and 3. At the output of the adder 8 modulo two, at the same time, a code is received, which is after transcoding. pr Leads to the next symmetric matrix of Walsh functions

W, In the case of .j, 2 and 3 generate the code

F

the invention

o p m u l a In this case, the matrix of the Wapp functions has the form It is easy to notice that the matrices (1) and (2) are not equivalent, i.e. no permutation of the rows of one of the matrices can be obtained from the other; moreover, they are symmetric, i.e. NV-W. The advantage of the generator provided is that due to the possibility of symmetrically controlling the phase of the generated functions and the order of them. Composition A better matching of the Walsh basis functions system with specific requirements of the problem to be solved is achieved, and, therefore, the accuracy of the solution is improved. In addition, it becomes possible to ensure the repeatability of the Walsh basic function generation blocks in the information transmission and processing equipment, which helps reduce the costs of its development, manufacture and operation. At the same time, hardware costs increase insignificantly. Disconnecting the respective control inputs of the counters allows the SOY phase of the generated Walsh functions and the order in which they are to be controlled independently, thereby achieving enhanced functionality as compared to the well-known Walsh function generator. 1. A Walsh function generator containing reHepaiop clock pulses, two n -dbit counters (n is the order of the Walsh function system), And elements, an adder for modup two, the output of the clock generator connected to the counting input of the first counter, (2j -; 1) -th and 21st, where i 1-g (n-1), control inputs of the Walsh function generator are connected respectively to the first and second control inputs of the i-th digit of the first counter, (2n-1) control input of the Walsh function generator is connected to the control input of the nth digit of the first counter, the outputs of the same The first and second counters are connected to the inputs of the corresponding element AND, the outputs of the elements AND are connected to the inputs of the modulo two adder, the output of which is the output of the Walsh function generator, which is connected with the extension circuit of the functionality of the generator, and It is the ability to generate symmetric matrices of Walsh functions, it contains ti-l elements OR, the first input of the first element OR is connected to the inverse output of the first bit of the first counter, the first input of the I-th elec ENT, except the first element OR, is connected to the output (il) -ro of the element OR, the second input ir of the element OR is connected to the auxiliary output (-i + l) -ro of the first counter, the output (nl) -ro of the element OR connected to the counting input of the second counter, the control inputs of the bits of the second counter are connected to the control inputs of the same bits of the first counter. 2. The device in accordance with claim 1, wherein the first discharge of the first and second counters consists of a trigger and two adders, two of them, and the inverse output of the trigger is connected to its information input and to the first inputs of the first and second modulators two, the second inputs of which are respectively the first and second control inputs of the first bit, j and the bits of the first and second counters, where jft2f (nl), consists of a trigger, three modulators two and the element And , moreover, the inverted output of the trigger of the jth digit is connected to the first inputs of the first and second adders modulo two j-th bit, the second inputs of the first and second adders; The two j-th bits of the module are correspondingly the first and second control inputs of the j-th digit of the counter, output | Dy of the first and second modulo two J-ro bits are connected to the first inputs of the third modulo two and element And the j-th bit of the third adder modulo two j-th bit is an additional output of the Y-th bit and is connected to the information input of the trigger of the j-th bit, the n-th bit of the first and second counters consists of the trigger and two modulo-two adders, with the inverse trigger output of the n-th bit connected to the first input of the first modulo two n-th digit, the second input of the modulo two n-th digit is the control input of the n-th digit of the corresponding counter, the output of the first modulo two of the n-th digit Yes, it is connected to the first input of the second adder modulo two nth bits, the KOTOpctro output is an additional output of the nth digit of the corresponding counter and connected to the information input of the n-th trigger, outputs of the first and second modulators two the first bit in each of the account Pd connects to the second inputs of the third modulo two and the second AND-second element, respectively, the output of the element And the ft -th bit, where (n-2), is connected to the second inputs of the third modulo-two and the element And {R +1) -th bit, output of the AND (nl) -ro bit switch is connected to the second input of the second adder modulo two n-th bits, the outputs of the flip-flops of all bits are the outputs of the bits of the corresponding counters, the sync inputs of all the triggers contained in the meter are combined and connected to the counting input corresponding to counter. Sources of information taken into account in the examination 1, USSR Copyright Certificate No. 456268, cl. G 06 F 1 / O2, 1973., 2. USSR author's certificate in application M 2906756 / 18-24, cl. G 06 F 15/332, 1980.

Claims (2)

Claim 1. A Walsh function generator containing a clock generator, two η-digit counters (and is the order of the system of Walsh functions), η elements are two modulo adders, and the output of the clock generator is connected to the counting input of the first counter, (2j: 1) - th and 2 th, where i = lr (nl), the control inputs of the Walsh function generator are connected respectively to the first and second control inputs of the jth category of the first counter, (2n-1) th control input of the Walsh function generator is connected to the control input η-th discharge of the first counter, outputs of the same name 7 discharges of the first and second counters are connected to the inputs of the corresponding element AND, the outputs of the elements AND are connected to the inputs of the adder modulo two, the output of which is the output of the Walsh function generator, which corresponds to the fact that, with the extension circuit of the generator’s functionality, . namely, the possibility of generating symmetric matrices of Walsh functions 10, it contains ti-1 OR elements, ^ the first input of the first OR element being connected to the inverse output of the first digit of the first counter, the first input of the -th OR element, except for the first 15th OR element connected to the output of (ϊ-Ι) -γο of the OR element, the second input of the i-ro of the OR element is connected to the additional output (ΐ + 1) of the first discharge of the first counter, the output (nl) -ro of the OR element 20 is connected to the counting input of the second counter, control inputs of the discharges of the second counter is connected s with control inputs of the same category bits of the first counter. 25 2. The device according to π. 1, characterized in that the first bit of the first and second counters consists of a trigger and two adders modulo two, and the inverse output of the trigger is sub-connected to its information input and to the first inputs of the first and second adders modulo two, the second inputs are koto-. ryh are respectively the first and ¹ second control input of the first category, the Jth category of the first and second counters, where 3 & 2γ- (η-1), consists of a trigger, three adders modulo two and the element And, and the inverse output of the trigger J -th discharge is connected to the first ₀ input of the first and second adders modulo two j-th category, the second inputs of the first and second adders modulo two j-th category are respectively the first and second control input _{45 of the} j-ro category counter, exhausts of the first and second adders modulo two J-ro categories Keys to the first inputs of the third adder modulo two and the AND J -th bit, the output of the third adder modulo two J -th bit output is further j-ro discharge and connected to the data input of flip-flop j-th bit, η th. the discharge of the first and second counters' consists of a trigger and two adders modulo two, and the inverse output of the trigger of the ηth discharge is connected to the first input of the first adder modulo two pth digits, the second input of the adder modulo two ηth digits is the control the input of the ηth row of the corresponding counter, the output of the first adder modulo Two ηth discharges is connected to the first input of the second adder modulo two ηth discharges, the output of which is an additional output of the ηth discharge of the corresponding counter and under is connected to the information input of the η-th trigger, the outputs of the first and second adders modulo two of the first digit in each of the counters are connected to the second inputs of the third adder modulo two, and the element And of the second category, the output of the element And Q-th category, where R = 2i- (n-2), connected to the second inputs of the third adder modulo two and the element And (R +1) -th category, the output of the element And (nl) -ro discharge is subpuffed to the second input of the second adder modulo two η -th discharge, the outputs of the triggers of all bits are. the outputs of the bits respectively of the corresponding counters, the synchronization inputs of all the triggers contained in the counter are combined and connected to the counting input of the corresponding counter.