SU963086A1 - Rectangular igfet-based decoder - Google Patents

Description

(FOR) RECTANGULAR DEFINER ON TIR TRANSISTORS

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The invention relates to a computing technique and can be used when creating storage memories on MIS transistors (MIS-ZU). ..

Linear decoders are known, consisting of a single decoding stage, built on NDP transistors, the gates of which are connected to the input address buses, and the combined drains are output decoder buses f 13.

The lack of such decoders is limited functionality.

Closest to the proposed by the technical nature of the rectangular daiifrator containing two steps: decoding 2,

However, the known decoder has limited capabilities in terms of the amount of information to be converted.

(can not contain more than 2-3 decryption steps).

The purpose of the invention is to expand the amount of information to be converted.

The goal is achieved by the fact that a rectangular decoder on MOS transistors containing the first decryption stage ... consisting of eight transistors, and the second stage of the decoding stump, and the origins of four transistors of the first decryption stage are connected to the gates of the second decoding transistors, and the sources the other four transistors of the first deciphering stage — with the drains of the second-stage transistors of the decoding, sources, the second-stage transistors of the decoding are output buses, a block of time distributions is introduced dividing the address, the gates of the transistor which are connected to the input bus of the decoder, drains to the corresponding clock tires

Claims (2)

; and the sources - to the corresponding valves and drains of the first stage of decoding. FIG. 1 shows the scheme of the proposed decoder; in fig. 2 provides a temporary diagram of his work. The decoder consists of transistors 1-8 of the first decryption stage, let us take the sources of the transistors 1-4 connected to the corresponding drains, and the sources of the transistors - with the corresponding gates of the transistors of the second decryption stage, the sources of which are the output buses of the decoder, and the transistors of the time distribution address the drains of which are connected to the corresponding clock buses 9-51 sources - to the corresponding gates and drains of transistors 1-8 of the first decryption stage, and the gates are the input buses of the decoder 50-59. The proposed decoder works as follows. Suppose that the code A 0 is supplied to the input buses of the decoder 52-59; Ai 0; A 3 0; In this case, the transistors h2, i, 6, and 8 of the temporary address allocation unit are opened. Then, the transistors 7 and 8 of the first stage of the decoder are opened by a pulse on the first clock bus 49 through the open transistor. The impulse on the second clock bus 50 through the open transistor k2 of the time distribution unit opens the transistors 3 and 4 of the first decryption stage, and through the open transistors Ts8 and B the transistors of the second decryption stage 12, 16C open. The pulse of the third clock bus 51 through open transistors k 4 and 12 passes to the output bus of the decoder 28. The decoder is designed so that the signals on the clock buses 9-51 through the block of the time distribution of the address provide a consistent pre-charge of the decoder gates and their transition to floating mode, and then the signal to the current electrodes. It is known that the operation of a MOS transistor in the floating potential mode at the gate provides a high signal transmission rate from the drain to the source and eliminates voltage losses associated with the cut-off of the channel of the MOS transistor. Thus, the use of a temporary address allocation unit in the proposed decoder allows to expand the amount of information to be converted and to increase the speed by providing a floating potential mode for all the decoder transistors. Claims. Rectangular decoder on MIS transistors, containing the first step of decoding, consisting of. eight transistors and a second decryption stage, with the origins of four transistors of the first deciphering stage being connected to the gates of transistors of the second deciphering stage, and the origins of the other four transistors of the first decryption stage with drains of the second-stage decoding transistors, the origins of the second decoding transistors are output buses of the decoding stage, This also includes the fact that, in order to expand the amount of information to be converted, a block is inserted in it for temporary address allocation, the gates of the transistors of which are connected a decoder input bars, flows - to the respective clock buses, and sources - the respective gate and drain of the transistors of the first decoding stage. Sources of information taken into account in the examination 1.US Patent ff 07 “237, cl. 3 0-173. 2.Bukreev I.N. and others Microelectronic circuits of digital devices. I., Soviet Radio, 1975, p. 31 (prototype). sh dn v L7. 5g, aif yfj "7lr jn 7 j S7 SB . 50 51 figg