SU936371A1 - Multiplier of frequency of fundamental harmonic of periodic signal - Google Patents

Description

I

The invention relates to computing and measuring technology.

The digital tracking frequency multiplier is known, which contains a pulse shaper, the input is connected to the information input of the device, and the output is connected to the control inputs of the frequency divider, counter and register, the generation of clock pulses, the output of which is connected to the information input of the frequency divider. The output of the frequency divider is connected to the information input of the counter, the bit outputs of which are connected to the information inputs of the register. The register outputs are connected to the control inputs of the digital-controlled frequency divider, whose information input is connected to the output of the clock pulse generator tl.

A disadvantage of the known device is the necessity of using as input an oscillation close in shape to a sine wave. Meanwhile, in most practical cases, this signal has a significant non-sinusoidality and, therefore, the need for pre-filtering arises, which limits the frequency range of input signals and, moreover, is associated with additional hardware costs.

Also known is the frequency multiplier of the fundamental signal of a periodic signal, which contains a series-connected input source and an analog-to-digital converter (ADC), serially connected clock pulses (GTI) and the first frequency divider, as well as a control unit, the first input of which is connected to the input GTI, the first and second counters, register, trigger 20, the first and second elements AND, the first inputs of which are combined and connected to the output of the first counter 2. However, the known device does not provide Exposure to extreme accuracy in expanding the range of input frequencies. The purpose of the invention is to improve the accuracy when expanding the range of input frequencies. The goal is achieved by the fact that the frequency multiplier of the main harmonic of a periodic signal containing serially connected input source and analog-to-digital converter ADC, serially connected GTI clock pulse generator and the first frequency divider, as well as the control unit, the second input of which is connected to the output GTI, first and second counters, register, trigger, first and second elements And, the first inputs of which are combined and connected to the output of the first counter, between the output of the GTI and the outputs of the register vv den the second frequency divider, between the output of the ADC and the first trigger input, serially connected memory unit and comparator are entered, the second input of which is connected to the ADC output, the second trigger input is connected to the output of the first counter, the trigger outputs are connected to the second inputs of the first and second elements, respectively And, the output of the first frequency divider is connected to the first input of the first counter and to the second input of the control unit, the output of which is connected to the combined control inputs of the memory unit and the comparator controlling the moves of the first frequency divider are connected to the control inputs of the register and connected to the output of the second sweeper, whose inputs are connected respectively to the outputs of the first and second elements I, the second output of the first counter connected to the second input of the memory unit, and the input of the register is connected to the output the second element I. The drawing shows the structural scheme of the proposed multiplier often the main harmonic of the periodic signal. The frequency multiplier of the fundamental signal of a periodic signal contains a clock pulse generator (GTI) 1, the first frequency divider 2, register 3, the first counter, the analog digital converter (ADC) 5, the memory block 6, the comparator 7, the second counter 8, trigger 9, the first and the second elements are And 10 and 11, the second frequency divider 12, the control unit 13, the input source. The multiplier frequency of the main harmonic of the periodic signal works as follows. The input periodic non-sinusoidal signal, converted by ADC 5, is recorded in block 6, and is also fed to one of the inputs of comparator 7. At the comparator, the output signals of ADC 5 and block 6 are compared. The write or read information of block 6 is set by control unit 13 The write or read address codes of block 6 are generated by a counter k, to the input of which clock pulses of varying frequency are received. The output signal of block 6 coincides in form with the output signal of ADC 5 and differs from it only in a time scale, which is determined by the rate of change of the counter code. If the periods of the comparator input signals are different, the output signal of the comparator trigger 9 is set to state 1, element 10 opens and the output pulses of counter k change the state of counter 8. This changes the division factor of divider 2, the frequency of the pulse of counter and, consequently, the period of the output signal 6. At the moment of equality of the periods of the output signals of the ADC 5 and block 6, the trigger 9 is set to the state O, Element And 10 is closed, And 11 is opened and the next output pulse with 4 etchika code counter 8 is rewritten into register 3, after which the counter 8 is reset to zero. In case of equal periods of the input signals of the comparator 7, the period of the output signal of the counter, which reflects the changes in the states of the most significant bit over time, is equal to the period of the indicated signals and, therefore, to the period of the main harmonic of the input signal. From the algorithm of the device follows f. frjr is the frequency of the main harmonic of the input signal; fyy is the pulse frequency of the generator 1;

K is the division factor of the digitally controlled frequency divider 2 (counter code 8); N - recalculation factor

counter t.

Then the frequency of the output pulses of the frequency divider 12 is equal to

V

TP

- og-ftbHl - K

The proposed device multiplies the frequency of the main harmonic of a non-sinusoidal periodic signal whose frequency does not necessarily coincide with the frequency of the main harmonic, moreover, the frequency multiplication is performed without prior filtering the signal, which will ensure high accuracy when expanding the input frequency range. In addition, the possibility of multiplying the frequency of the fundamental harmonic of a non-sinusoidal signal eliminates the need to form an additional clock signal of a sinusoidal form on the measurement object.

Claims (2)

1. USSR author's certificate №, cl. G 06 F 7/52, 1978. 2. Author's certificate of SSSG No. i 35582, cl. H 03 B 19/00, 1970 , (prototype). 3k  g R t j b w f oo rJ "-S