SU930387A1 - Analogue storage - Google Patents

Description

(S) ANALOGIC SAFETY DEVICE

The invention relates to computing, in particular to analog storage devices, and can be used to store continuous analog signals. An analog storage device is known for storing disk values of analog continuous signals, characterized in that capacitors are used as analog storage elements, which in recording mode are alternately connected via keys to an input source for the time corresponding to the quantization step. In storage information, all capacitors are disconnected. In the playback mode, the capacitors are connected in turn to the output repeater on the same time scale. And in the erase mode, all capacitors are shorted tl3. The drawback of the device is the low reproduction accuracy of the recorded information. In a known device, in order to reduce errors that occur during playback during switching of memory elements into a circuit. feedback of the replay enhancers are corrective. In spite of these measures to improve the reproduction accuracy of the recorded information, the disadvantages of the known devices are not completely eliminated. These devices reproduce the recorded continuous signal in the form of a stepwise approximation, for further use of which it is necessary to bring it to its original form. smooth vat (, integrate). Integrating the step function throughout the entire period of playback:

nor contributes to the accumulation of npi-h solutions.

The closest in technical essence is a device that contains a group of storage capacitors, an output DC amplifier and a correction circuit including resistors, capacitors, a switch, an additional amplifier. The input source through the switch is connected to the input of the output amplifier, the feedback circuit of which is connected via the keys to a group of storage capacitors, as well as a correction circuit. The output of the output amplifier is connected to the input of the additional amplifier through a communication element, for example, a resistor, and the input of the output amplifier is connected to the output of an additional amplifier through a communication element, for example, a capacitor, in the feedback circuit of an additional amplifier are connected in parallel a connected capacitor, a resistor key west

Information is recorded in the device by alternately connecting the storage capacitors to an input source. Parasitic capacitances are also charged. During the period of information storage, the key in the feedback circuit of the additional amplifier closes, which ensures the discharge of stray capacitances and the restoration of the machine zeros of the amplifiers. In playback mode, this switch is again opened and a correction circuit is connected to the feedback circuit of the output amplifier, which prevents the storage capacitors, which are alternately connected to the output amplifier. This leads to a decrease in instrumental error arising in the process of reproducing the recorded information.

A disadvantage of the known device, despite the fact that the reproduction accuracy of the recorded information slightly increases, is the preservation of significant errors in the form of the output signal, i.e. the accuracy is still low, since the input signal itself is not reproduced, but only its step approximation.

Another disadvantage of the device is its application area. When performing various calculations, for example when calculating recurrent

functions, it becomes necessary to simultaneously record new information and play back the previously recorded in one memory block, which

simplifies the organization of the computational process, contributes to the accuracy of analog computing.

This device does not allow simultaneous recording, playback and erasing of information, i.e. possesses low efficiency. The purpose of the invention is to improve the accuracy of the device and expand the area of its application by simultaneously recording, reproducing and erasing information.

The goal is achieved by the fact that in an analog storage device containing the first block

the memory, the first input of which is connected to the input of the device, the second, third and fourth inputs of the first memory block are connected in accordance with the first, second and third outputs of the control unit, the recording bus and the quantization step selection bus connected to the inputs of the control unit are entered the second memory block, the differential amplifier, the first and second keys, the first and second integrators, the repeater and the adder, the output of which is connected to the output of the device, the inputs of the adder are connected. respectively, with the outputs of the integrators and the output of the voltage follower, whose input is connected to one of the inputs of the differential amplifier, the inputs of the integrators are connected to the outputs of the keys, the first inputs of which are connected to the output of the differential amplifier, the inputs of which are connected to the outputs of the memory blocks, the second inputs of the keys are connected to the fourth output of the control unit; the first input of the second memory unit is connected to the input of the device; the fifth, sixth and seventh outputs of the control unit are connected to the second, third and the fourth inputs of the second memory block.

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The control unit contains the counter, the distributor, the first, second and third groups of triggers, the inverter, the first, second, third, even. true and fifth triggers and generator

Claims (3)

5 clock signals, one input of which is connected to the inputs of the control unit, the output of the clock signal generator is connected to the first input of the counter, to the first input of the distributor and to the inputs of the first and second triggers, the second input of the distributor is connected to one of the inputs of the control unit and to the input of the third trigger whose output is connected to the input of the fourth trigger, to the input of the inverter and to the first inputs of the first group triggers, the output of the inverter is connected to the input of the fifth trigger and to the first inputs of the second group triggers, second to the meter stroke is connected to the second input of the distributor, the meter output is connected to another input of the clock signal generator and to the first inputs of the third group triggers, the second and third inputs of each 1st trigger of the first second and third groups are connected respectively to the 1st and (+1 the) outputs of the distributor, the outputs of the second, fourth and fifth triggers are connected respectively to the first, second and third outputs of the control unit, the output of the first trigger is connected to the fourth output of the control unit, the outputs of the triggers of the first, second and third The network of groups is connected to the fifth, sixth and seventh outputs of the control unit. FIG. 1 is a functional diagram of the proposed device; in fig. 2 is a functional block diagram of the control unit; FIG. 3 is one of the variants of the circuit execution of the memory block. The device contains a control unit 1, memory blocks 2 and 3, keys j and 5, integrators 6 and 7. Adder 8, voltage follower E, differential amplifier 10, start bus 11, and quantization step bus 12. The control unit (Fig. 2) contains a clock signal generator 13, a circuit H, triggers 15-19, an inverter 25, a distributor 21, triggers 22-24 of the first, second and third groups. The memory block (FIG. 3) contains keys 25-32, operational amplifiers 33 and 3, resistors 35 and 3B, memory cells 37, each of which consists of a capacitor 38 and keys. In the playback mode in the memory block, the keys are closed. 27-30. Reproduction of the recorded information is performed in the same way as the recording process, only at each playback step to the differential amplifier 10 is fed through the voltage amplifiers 33 and 3 from the 1st and (1 + 1) -th memory cells 37. The voltage of the memory cells is fed to the input of the input differential amplifier 10, the output of which is formed of a | - signal equal to their difference. This signal alternately through the clock of the generator 13 through the keys and 5 is fed to the first and second integrators 6 "fi 7- Each integrator measures the signal during only one quantization step, and if the first integrator 6 integrates the signal, then the second integrator 7 during this step restores its machine zero, and vice versa. This allows K to reduce the time of accumulation of errors. From integrators 6 and 7, the difference signal is fed to the adder 8, where it is summed with a fixed voltage value on the memory connected during the i-ro pitch of the 1st memory cell 37. At the output of this adder 8, which is the output of the entire device, a continuous analog signal is generated, which is an exact copy of the recorded one. The erase information cycle is combined with the recording and playback cycles, namely, with the beginning of the 1st step, the capacitor 38 is played back by the erase key 39, which opens only at the beginning (1-1) of the first step of the write cycle. Thus, the time to erase information from each capacitor of 38 memory cells 37 is n times longer than the recording time. This is the asymmetry of recording times and. erasing information contributes to improving the accuracy of the device, since for many types of capacitors the process of depolarization of the dielectric is more inertial, which can contribute to the accumulation of errors due to frequent information rewriting. The control unit operates as follows. With the arrival of the trigger pulse, the generator 13 and the counter k are started. The distributor 21 also changes the output logic potential of the trigger 17, which causes a change in the state of Schmidt triggers 18 and 19, which are intended to switch recording and playback modes in the first and second memory blocks, respectively. ti 2 and 3, i.e. control keys 25-30. At any time in the arena triggers 18 and 19 are in pro. opposite conditions, since the input of the trigger 18 is connected to the output of the trigger 17 directly, and the input of the trigger 19 through the inverter 20. From the generator output 13, the clock pulses go to the input of the counter k, which allocates the {k + 1) -th clock the pulse that serves as the signal for the end of the next record-play cycle. This impulse arrives at the input of the generator 13 and stops the latter (with full use of the memory volume msk). The clock pulses arrive at the input of the trigger 1, which controls the keys k and S of the integrators 6 and 7, and those at the input of the trigger 16. to zero the operational amplifiers 33 and 3 in the information storage mode (in the absence of clock pulses). I Clock pulses arrive at the input of the distributor 21, in which each i-th input pulse is allocated to the 1st output of the distributor, then the i-th pulse opens the 1st trigger and closes the (| -1) -st switching capacitor 24 both of the memory blocks 2 and 3, and also opens (1-1) -th and closes (1 + 1) -th triggers 22 and 23 erase, the first triggers 22 and 23 are closed by a start pulse. The inputs of the flip-flops 22 erase the first ruler, the control signal comes from the output of flip-flop 17 directly, and to the inputs of the flip-flops 23 erase the second ruler through the inverter 20. Triggers 2 are controlled by keys 40 and 41 of both memory blocks 2 and 3, triggers 22 and 23 control the erase keys 39 of the first and second memory blocks 2 and 3, respectively. When working with the recorded signals of a certain duration into the memory block, the quantization step length is determined by their duration and the number of capacitors Z3. In this case, the potential corresponding to a certain quantization step length is fed to the bus 1.1, i.e. set the frequency of impulses of the generator 13. The minimum duration of the quantization step is defined. In this case, when recording rapidly changing processes, it may be necessary to use only a part of storage capacitors 38. At the same time, counter 14 is tuned to the (t + 1) -th clock pulse, where m - the number of the last step of the record-play cycle, in addition, this (t + 1) -th clock pulse goes to the closing inputs of all the flip-flops 24 (these inputs are equipped with cross-section diodes), which leads to the standard end of the record-play cycle. The proposed device will allow. record and play back processed signals as a continuous signal. The reproduction accuracy of the recorded information will satisfy more stringent requirements, since in the course of reproduction during integration, the accumulation time of no resolutions is significantly reduced. The proposed device significantly expands its field of application, namely: it simultaneously records, reproduces and erases information, and the time to erase information from each capacitor is much longer than the recording time, which also contributes to an increase in accuracy. Claim 1. Analog memory device containing a first memory block, the first input of which is connected to the device input, the second, third and fourth inputs of the first memory block are connected to the first, second and third outputs of the control unit, the recording bus and the step bus quantization, connected to the inputs of the control unit, characterized in that, in order to increase the accuracy of the device and expand its area of application by simultaneously recording, reproducing and erasing information and, a second memory block, a differential amplifier, first and second keys, first and second integrators, a voltage follower and an adder, the output of which is connected to the output of the device, are entered, the inputs of the adder are connected respectively to the outputs of the integrators and to the output of the voltage follower, whose input is connected to one of the inputs of the differential amplifier, the integrator inputs are connected to the outputs of the keys, the first inputs of which are connected to the output of the differential amplifier, the inputs of which are connected to the outputs of memory blocks, the second inputs of the keys are connected to the fourth output of the control unit, the first input of the second memory block is connected with the input of the device, the fifth, sixth, and seventh outputs of the control unit, respectively, with the second, third, and fourth inputs of the second memory unit. 2. The device according to claim 1, wherein the control unit comprises a counter, a distributor, a first, second and third group of triggers, an inverter, a first trigger, a third, a fourth and fifth triggers, and a clock signal generator, one inputs of which are connected to the inputs of the control unit, the output of the clock signal generator is connected to the first input of the counter, to the first input of the distributor and to the inputs of the first and second triggers the second input of the distributor is connected to one of the inputs of the control unit and to the input of the third trigger, output cat cerned connected to the input of the fourth flip-flop to the input of the inverter. 3038710 and to the first inputs of triggers of the first group, the output of the inverter is connected to the input of the fifth trigger and to the first inputs of triggers of the second group, the second input of the counter is connected to the second dispenser input, output score. with another input of the clock signal generator and with the first inputs of the third group triggers, the second to and the third inputs of each J-ro trigger of the first, second and third groups are connected respectively to the 1st and (1- | -1) -th outputs of the distributor, the outputs of the second,: fourth and fifth J5 flip-flops, connected respectively to the first, second and third outputs of the control unit, the output of the first flip-flop is connected to the fourth output of the control unit, the outputs of the flip-flops 2p of the first, second and third groups are connected to the fifth, sixth and seventh outputs of the control unit. Sources of information taken into account in the examination 1. USSR author's certificate “32563Y, cl. G 11 C 27/00, 1972. 2. USSR author's certificate №, cl. G 11 C 27/00, 197. 3. USSR author's certificate number 362352, cl. G 11 C 27/00, 1973 (prototype). 3foff