SU905998A1 - Analogue-digital converter - Google Patents

Description

(54) ANALOG-DIGITAL CONVERTER

one

The invention relates to computing and can be used in automated information processing systems.

A known analog-to-digital converter contains a voltage divider, the outputs of which are connected to the first inputs of null organs, the second inputs of which are connected to the input source bus, and the outputs are connected to the inputs of the information processing unit l.

The disadvantage of the device is low conversion accuracy.

A analog-to-digital converter is known, containing an input signal differentiation unit, the output of which is connected to the input of a parallel analog-to-digital converter, and the input is connected to the input of a series-parallel parallel analog-to-digital converter 2.

The disadvantage of the device is low speed.

The purpose of the invention is to increase speed.

This goal is achieved by the fact that the analog-to-digital converter contains an adder, the output of which through a parallel analog-digital converter is connected to the first input of the output driver

10 codes, the second and third inputs of which are connected respectively to the VBBJM and the second inputs of the digital-to-analog converter, the output of which is connected to the input to the matrix,

15 a digital filter is inserted, the first input of the digital filter is connected to the output of the output codes generator, the second input is connected to the second input of the output codes generator,

20 and the output is connected to the first input 1C of the fro-analogue transform-n.

FIG. 1 shows a structural electrical arrangement, on

ig. 2 - digital filter, structural electrical circuit.

The device contains an adder 1, a digital-to-analog converter 2, a parallel analog-digital converter 3, a form of 4 output codes, a digital filter 5. The latter contains digital registers 6, 7 and 8, a weighted-sum block 9.

The device works as follows.

Before operation, the digital-to-analog converter 2, driver 4, digital filter 5 are set to zero. At the beginning of the j-ro clock, the unitary code from the output of the parallel analog-digital converter 3 enters driver A, where it is converted into a binary code and added to code coming from digital filter 5. After that, a new code is input to the digital filter 5, which generates a digital code that is the (j + 1) -ro prediction code of the clock. This code at the output of the digital-to-analog converter 2 to the beginning of the CJ + 1) clock generates an analog signal that compensates for the input analog signal. The remainder of the compensation at the output of the adder 1 is the prediction error g. This remainder is converted by a parallel analog-to-digital converter 3 at the beginning of (j + 1) -ro clock into a unitary code, according to which shaper 4 generates a true digital code by summing the predicted code at the output of digital filter 5 with the residue code At the output of parallel analog-digital converter 3 and outputs it to the output of the device and to the input of the digital filter 5 to effect the conversion in the next cycle. Thus, a parallel analog-to-digital converter is intended only to convert a small part of the signal - the remainder of the compensation. Introduction of digital. filter allows you to increase speed.

Claims (2)

1. Gitis E.I. Information converters for electronic digital computing devices. M., Energie, p. 314. 2. Authors certificate of the USSR for application no. 2565154, 1978 (prototype). FIG.