SU903981A1 - Storage device - Google Patents

Description

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The invention relates to computer technology and is intended for the creation of permanent memory semiconductor devices with electrical reprogramming of information based on MNDS (metal silicon nitride - silicon oxide - semiconductor) memory structures.

A permanent memorizing device with an electrical change of information is known, which contains an INEC matrix. memory cells, each of which consists of a memory and separation transistors, allow you to use one column bar common to two neighboring cells, connecting each pair of cells to a read amplifier in such a way that one cell is memory, and the other one is reference 1.

However, this storage device, due to the asymmetry of the circuit, has reduced noise immunity and insufficient information storage time.

The closest in technical essence to the present invention is a permanent memory device, in which each columnar function, which is common to each two neighboring cells containing a junction and memory transistors, connects C2 to the cells through corresponding deciphering key transistors of the shift register C 2 .

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The disadvantage of such a device is the need to switch when recording and erasing the voltage of the outgoing wave signals by transmitting key transistors, which requires

IS venno-high voltage circuits of address amplifiers, register, which reduces the reliability of the circuit. In addition, the disadvantage of such a memory device is that the flow direction

Claims (2)

20 current in two adjacent cells opposite. This requires the inclusion of a separator1 of the cell transistor either in the drain circuit or in the source circuit of the memory transistor, changing the cell slope and, therefore, the speed of the circuit. The purpose of the invention is to increase the reliability of the device and the speed of reading. This goal is achieved by the fact that in a memory device containing the first group of key elements made on transistors whose drains are connected to the information inputs of the matrix drive, and the sources go to the inputs of the read-write block, one address input of the matrix drive is connected to the outputs of the address decoder , address amplifiers, the outputs of the first of which are connected to other address inputs of the matrix accumulator, were additionally introduced a voltage source, load elements, each of which performed on a transistor, the source of which is connected to the corresponding information input of the matrix accumulator, the gate and drains of the transistors of the load elements are connected to the outputs of the corresponding power sources, and the second group of key elements, each of which is made on the transistor, the source of which is connected to the corresponding information input of the matrix accumulator and to the drain of the transistor of the corresponding key element of the first group, the drains of the transistors of one of the key elements of the second group are connected to the sources of the corresponding transistors of the key elements of the first group and to the corresponding inputs of the read-write block, the drains of the transistors of other key elements of the second group are connected to the drains of the transistors of the corresponding key elements of the first group and to the corresponding outputs of the source of the reference voltage, gates of the transistors of the first and second key elements and the second groups, respectively, are combined and connected to the outputs of the second adhesive amplifier. In addition, the matrix accumulator contains memory and separation transistors, the gates of the corresponding storage transistors are combined and are the same address inputs of the matrix accumulator, the gates of the corresponding separation transistors are combined and are the address inputs of the matrix accumulator, the drains of the corresponding storage transistors are combined, and the corresponding inputs of the matrix accumulator the inputs of the matrix accumulator, the sources of the corresponding junction transistors are combined and are sootvetstvuyui1imi matrix data inputs of the accumulator, the source of each of the memory transistors connected to the drain of the corresponding transistor of the separation. The drawing shows a diagram of a storage device. The storage device contains the first group of key transistors 1 whose drains are connected to the information inputs 2 of the matrix accumulator 3, the inputs 4 of the read-write unit 5, the outputs 6 of the source 7 of the reference voltage, the second group of key elements, each of which is made on the transistor 8, the address amplifier 9, transistors 1O, which are load elements, power supply 11, one address inputs 12 of matrix storage 3, address cipher 13, other address inputs 14 of matrix storage 3, address amplifier 15. Matrices 3 comprises a storage drive transistors 16 and 17. Transistors separating apparatus operates as follows. in the read mode, the load elements yu are closed and are in a non-conducting state. In order to interrogate the cell of the storage device, junction transistors 17 are opened, connected to one of the terminals of the address amplifier 15. The junction transistors 17 of each neighboring cells are connected to another of the terminals of the address amplifier 15 and closed, excluding the flow of current through these cells. At the same time, transistors 1 of the first group of key elements are turned on from a different address amplifier 9. From the source 7 of the reference voltage from the output 6, a voltage is applied to the source of the transistor 1 of the first group of key elements. If the storage transistor 16 is in the conducting state, a current flow circuit is created: the voltage source, output 6, transistor 1 of the first group of key elements, information. output 2, separation transistor 17, memory transistor 16, information output 2, transistor 1 of the first group of key elements, input 4, block 5 read-write. The neighbor cell is polled when the potentials at one of the terminals of the address amplifiers 9 and 15 are reversed. In this case, the separation transistors are opened. 17 and the transistors 8 of the second group of key elements. The cell is polled as in the first case, only in the current flow circuit, instead of transistors 1 of the first group of key elements, transistors 8 of the second group of key elements participate, in the recording mode all dividing transistors 17 of the storage device are closed. Through the load elements 10, the gates and drains of which are connected to the high voltage power supply 11 (on the order of 30-35 V), the write-lock voltage is applied to the information buses 2 of the matrix 3. The information buses 2 and, accordingly, the drains of the storage transistors 16 are connected through transistors of the first or second group of key elements to the corresponding input 4 of the read-write unit 5. If at the input 4 of the read-write scheme has a low potential, the information is recorded in the cell of the matrix drive. If the input 4 of the write reading circuit is floating, then the information bus 2 has the potential to lock the write and no information will be written to the cell. In the proposed device, the high voltage circuits of the address amplifier and the read / write unit are eliminated, which increases the reliability and speed of the device. In addition, the device has a unidirectional flow of read current through the memory cell from the odd-numbered NOY bus to even-numbered, which also increases the reliability of its operation. The invention contains a storage device containing the first group of key elements made on transistors, the drains of which are connected to the information inputs of the matrix accumulator, and the sources - to the inputs of the read-write block, one address inputs of the matrix accumulator connected to the outputs of the address decoder, address amplifiers, outputs of the first accumulator of which are connected to other address inputs of the matrix storage device, characterized in that, in order to improve the reliability and speed of the device, it contains the source of voltage, load elements, each of which is made on a transistor, the source of which is connected to the corresponding information input of the matrix drive, the gates and drains of the load element transistors are connected to the outputs of the power sources, and the second group of key elements, each the transistor, the source of which is connected to the corresponding information input of the matrix drive and to the drain of the transistor of the corresponding key element of the first group, is the drain of the transistor in some key elements of the second group are connected to the sources of transistors of the corresponding key elements of the first group and to the corresponding inputs of the read-write unit, the drains of transistors of other key elements of the second group are connected to the drains of transistors of the corresponding key elements of the first group and to the corresponding outputs of the voltage source, gates transistors of the first and second key elements of the first and second groups, respectively, are combined and connected to the corresponding outputs of the second ad esnogo amplifier., 2. A storage device according to claim 1, similarly to the fact that the atric drive contains memory and separator transistors, the attributes of the respective storage rasistors are combined and are the same address inputs of the matrix accumulator, the gates of the respective separation transistors are combined, "are sent with the address inputs of the matrix accumulator, the slots of the corresponding separation transistors are combined" are sent with the address inputs of the matrix accumulator, the slots of the corresponding separation transistors are combined, "are sent with the address inputs of the matrix accumulator, and the associated memory transistors are combined to be the corresponding information inputs of the matrix drive, the drains of the corresponding dividing ranzist The oors are combined and are the corresponding information passes of the matrix drive, the source of each of the storage transistors 79039818 connected to the drain of the corresponding1. US Patent No. 4090257, separation transistor, CP. G 11 C 11/40, 1978. Sources of information, 2. U.S. Patent No. 4,103344, taken into account during examination. G 11 C 11/40, 1978 (prototype), F AND one f6f7r Ш1Ъ eleven i wnj 1bPg 1617g 13 No. t7i rm