SU903851A1 - Interfacing device - Google Patents

Description

(54) DEVICE FOR PAIRING

one

The invention relates to computing and can be used, for example, to organize highly reliable homogeneous computing systems for processing data in real time.

Computer interfacing devices are known in computing systems containing a group of computers (VM), a group of switches, and a shift register 1.

The disadvantages of such a computing system are the impossibility of simultaneously accessing several VMs at once and reducing the speed or reducing the number of functions performed in case of failures of individual VMs.

Closest to the invention is a device for interfacing computers in a computer system containing M switches, M shift registers, with the information output of the j-th computer (j 1, M) connected to the first information input of the j-ro switch, input j -ro shift register is connected to the j-ro output of the switch, and the output is connected to the second information input of the (j + 1) -th switch and information input (+1) of the VM, the output of the M-th shift register

connected to the second information input of the first switch; the controlling output of the jth VM is connected to the control input of the j-ro switch; the synchronization output of one of the M VMs is connected to the synchronization inputs of the remaining VM 2.

The disadvantage of this device is limited functionality, since the device does not allow assigning addresses of failed VMs to backup ones.

As a result, the speed and reliability of the computing system is reduced. Thus, in the case of system redundancy, the hardware connection of the backup VMs to the place of the failed VMs requires additional switching costs, and another way of switching the VMs — assigning the standby VMs to the identifier of the failed VMs (if the backup VMs are connected to the same line as the main VMs) changes the specified processing sequence information, which leads to an increase in the time of transmission of information from one VM to another.

The purpose of the invention is to expand the functionality of the device by providing automatic reassignment of the addresses of the device inputs.

The goal is achieved by the fact that the device containing M shift registers, M switching units, M address registers and M control triggers, with the outputs of the j-th (J 1, M) shift register and address register, the input of the j-ro control trigger and The first information input of the j-ro switching unit are respectively the jth information and address outputs of the device, the readiness input and information input of the device, and the second information input and output of the j-ro switching unit are connected respectively to the output j-ro and (J + 1) th shift registers introduced M elements And and a reconfiguration unit comprising M switches, two counters, a pulse generator, a state register and a group of elements AND, the first input and output of the j-ro element AND are connected respectively to the JM control input of the device and the control input j-ro switching unit, and the second input - with the j-ro output of the control trigger and the first input of the j-ro element AND group, the second input of which is connected to the M-th output of the decoder and the reset inputs of the first and second counters, and the output - to the information input j- ro bit yes status register, clock the input of which is connected to the clock inputs of the first and second counters and the output of the pulse generator, and the output to the information input of the first counter, the output connected to the information inputs of the switches, the address inputs of which are connected to the corresponding outputs of the decoder, the input of which is connected to the output of the second counter, output j The -ro switch is connected to the input of the j-ro address register, the output of the M-th switching unit is connected to the input of the first shift register.

The drawing shows a block diagram of a device for interfacing computers in a single computing system and a diagram of a reconfiguration unit.

The device contains shift registers 1, address registers 2, connected by outputs to the inputs of VM 3, whose outputs are connected to the inputs of switching blocks 4, AND 5 elements and triggers 6, and reconfiguration block 7, including AND group 8 elements, state register 9, first counter 10, switches 11, decoder 12, second counter 13 and pulse generator 14.

The device works as follows.

Let M of computers M be working, and the rest be backup.

In the initial state, all (main and standby) VM 3 are operational, and registers 2 record the sequence numbers of the corresponding VM.

The logical units "1 at the outputs of the triggers 6 controls, corresponding to the correct VM, are connected to the control inputs of blocks 4 through the elements AND 5 and the control outputs of VM 3. If VM 3 set a single signal at the control output, then the corresponding block four

connects the information output of this VM to its output, giving it the opportunity to display information. With a zero signal at the control input, unit 4 switches the input and output of two registers 1. Thus, the information entered from VM 3 and blocks 4 is circulated to the corresponding shift registers 1 around the shift register 1. Each VM 3 is assigned an address that it identifies in informational message in the register 1. When

5 identifying your address VM 3 reads and processes the message from the register 1 corresponding to it but given to the program.

Standby VM 3 in the specified process do not participate until their addresses recorded in registers 2 do not correspond to the addresses

 working VM 3. As soon as the address of any failed VM 3 is recorded in register 2 of any backup VM 3, the backup VM 3 includes the processing program and participates further in the operation of the system

5 as did the worker VM. During the operation of the generator system 14, it generates clock pulses, which is counted by counter 13. Under the action of these pulses, register 9 shifts its contents to the left, and counter 10 adds one to the content, if the bit that is expelled in a given clock cycle is one or contents, if the displaced bit is zero. Each cycle opens one of the switches 11, and in

the corresponding register 2 confirms the old one or introduces a new address determined by the contents of the counter 10. Each M-th also resets the counters 10 and 13 and records the states of the working and

jj of the reserve VM 3, fixed on the triggers 6, through the elements AND 8 into the register 9. Thus, in the state when all the VM 3 are in good condition, at the outputs of the triggers 6 single signals are fixed, which prepared the elements And 5 and bits

s register 9. In this case, registers 2 contain addresses that increase in the order of connecting VM 3 to the chain of registers 1.

Suppose the second VM failed.

0 Then, at the output of the second trigger 6, a zero signal is generated (at the command of the control system of the second VM 3), which blocks the second element And 5 and, accordingly, the possibility of issuing data from the second VM 3. At the next cycle, the second bit of the registry 9 is not recorded single signal. As a result, the address of the second VM is recorded in the third register 2, the address of the third VM is in the fourth register 2, and so on, with the address

Claims (1)

Claim A device for interfacing containing M shift registers, M switching blocks, ² M address registers and M control triggers, with the outputs of the jth (j = 1, M) shift register and address register, the j-ro control trigger input and the first information the input of the j-ro of the switching unit is respectively the j-th information and address outputs, the readiness input and the information input of the device, the second information input and the output of the j-ro switching unit are connected respectively to the output of the j-ro and j + 1st shift registers , distinctive; the fact that, in order to expand the functionality of the device by providing automatic reassignment of the addresses of the inputs of the device, M elements And and a reconfiguration block are included in it, including M switches, two counters, a pulse generator, a state register and a group of And elements, and the first input and the output of the j-ro element And are connected respectively to the j-th control, the input of the device and the control input j-ro of the switching unit, and the second input is the output of the j-ro trigger of the control and the first input of the j-ro element of the And group, the second input which is connected to the Mth output of the decoder and the reset inputs of the first and second counters, and the output to the information input j-ro of the discharge of the state register, the clock input of which is connected to the clock inputs of the first and second counters and the output of the pulse generator, and the output from the information input of the first counter, the output connected to the information inputs of the switches, the address inputs of which are connected to the corresponding outputs of the decoder, the input of which is connected to the output of the second counter, the j-ro output of the switch is connected to j-ro move the address register, the output M-th switching block is connected to an input of the first shift register.