SU900282A1 - Device for adding n-bit decimal numbers - Google Patents

Description

(5A) DEVICE FOR THE ADJUSTMENT OF A D-DISTRIBUTED DECIMAL

NUMBERS

t

The invention relates to automation and computing and can be used in specialized computing machines.

A device for adding decimal numbers is known, which allows for the correction of the result of the sum per CO time.

The disadvantages of this device are the need to correct the result and use the code in decades without erroneous detection ability.

The closest to the technical essence of the present invention is a device for adding spurious decimal numbers in which the Fibonacci numbering system is used to represent each decimal digit and excludes correction of the result of the addition. Each bit of the device includes four adders of the addition of two numbers and the element OR 21.

A disadvantage of the known device is that in the case of a transfer hyphen in the i-th decimal bit, an additional step of addition is needed for summing the transfer unit and the sum of the digits in this bit. This leads to a decrease in the performance of the adder of decimal numbers.

The purpose of the invention is to increase

10 device speed summation decimal numbers.

The goal is achieved by the fact that in the device for adding n-bit decimal numbers, the i-th bit of which (, 2,.,. N) contains four binary adders and the first element OR, the outputs of the sum of the first, second, third and fourth binary adders given

The 20 bits of the device are connected to the outputs of the sum of a given bit of the device, respectively, the first and second inputs of the second, third and fourth binary adders of a given bit of the device are connected to the inputs of the first and second operands of this bit of the device, respectively, the output outputs of the second and third binary adders of a given The bit of the device is connected to the first and second inputs of the first element OR of the given bit of the device, respectively, the output transfer of the third binary adder of the given bit is The device is connected to the third input of the fourth binary summator of the given bit of the device, the transfer output of which is connected to the transfer output from the given f-ro device bit of the (| +1) device bit, to each i-th bit of the device entered the eeent And, the second element OR, and the block forming the operands of the first binary adder and carries into the first, second and third binary adders, the first, second, third and fourth binary inputs of which are connected to the carry input from (bit, device into this i- Device size, to per The first and second operands of the i-ro device bit and the carry output from the second and third binary adders of a given device bit, respectively, and the first, second, third, fourth and fifth outputs are connected to the first, second, third inputs of the first binary adder of this device bit, to the first input element AND of the given bit device and to the first input of the second element OR of the given bit device, respectively, the second input of the second element OR is connected to the transfer output of the second binary adder given Aage discharge device, the second input of AND gate connected to the output transfer of the first binary adder of the discharge device. In addition, the operand generation block of the first binary adder and transfers to the first, second and third binary adders contains three OR elements, six AND elements and four NOT elements, the first block input connected to the first inputs of the first and second AND elements, the second block input connected to the input of the first element NOT, to the first input of the first element OR, and to the second input of the first element AND, the output of the first element2.44 of the element is NOT connected to the second input of the second, element OR, the output of which is connected to the second input of the first element that OR, the output of which is connected to the first output of the block, the second and third outputs of which are connected to the outputs of the second and third elements OR, respectively, the output of the first element AND connected to the first inputs of the third and fourth elements AND, the third input of the block connected to the second input of the third element AND , to the first input of the second element OR, and to the input of the second element NOT, the output of which is connected to the second input of the fourth element AND, the output of which is connected to the second input of the second element OR, the output of the third element AND the connection en to the first inputs of the fifth and sixth elements And, the fourth input of the block is connected to the second input of the fifth element And, to the first input of the third element NOT, the output of which is connected to the second input of the sixth element And, the output of which is connected to the second input of the third element OR, the output of the fourth element is NOT connected to the fourth output of the block, the fifth output of which is connected to the output of the fifth AND element and to the input of the fourth element NOT. The drawing shows a functional diagram of one decade of the device. The circuit consists of four three-input single-charge binary adders, elements OR 5 and 6, element AND 7 and block 8 logical elements, which consists of four elements NOT, six elements AND, and three elements OR 19-21. 0 this device to the inputs of the block 8 logical elements of the i-ro bit receives signals from the first and second operands and transfer from the (i -1) -th bit, from the first and second operands and transfer from the second and third three-input single-bit binary adders this decimal place. If one of these four signals is zero, then the block of logic elements transmits single signals to the inputs of the first three-input single-bit binary adder of the given decimal place, and summation is performed without block 8, If all signals at the input of block 8 are single, then the addition in the lowest The 5th bit (with a weight of 1) is performed in accordance with the 1 + 1 + 1 + 1 1 rule and a transfer to the bit 3 is formed. This is achieved by the block 8 of logic elements delivering to the input of the first three-input one-bit binary adderec tich' Nogo discharge unit blocks carry output of the adder and generates the carry input to the input of the third trehvhodovogo odnorazr-stand binary adder of a de adic discharge. In accordance with this, block 8 of logic elements implements the following logical functions: 1 P 1 1 Va jftpg V Y, - Pa (Pj VP,) V (D V P,) P, rD tPjVP,), where P is the transfer from the previous dec good discharge; transfers from the second and third bits of this decade; 01, & - binary digits of the decade data of the components; PJ- is the transfer to the third order of the decade. Single-digit 1-C adders are common adders in classical binary arithmetic that correspond to bits with a weight of 1.2, 3.5 and are interconnected by chains based on the summation rules in the decade bits, i.e. the transfer P is fed through the element AND 7 to the input of the adder 2, the transfer of Bj through the element OR 6 to the input of the adder 3 and through the element OR 5 to the input of the block of logical elements, the transfer of the RE; - to the input of the adder “and through the element OR 5 - to the input of the block of logic elements, the transfer Rc - transfer to the next decade. The element OR 5 is introduced so that the block of logic elements has four inputs. It does not distort the result of the summation, since the carry and Pj cannot be computed at the same time because the input of the decade is given codes in normal form, i.e. the presence of units in the second and third decade levels is simultaneously impossible. The element OR 6 is introduced to implement the addition of four units at the youngest decade level. The 3toT element does not distort the result of the summation. 82 since the P and Pj (s) of the logical element block simultaneously cannot appear for the same reasons as in the previous case. Element And 7 is introduced to implement the addition of four units in the first decade decade. On the input it is connected to the output Py of the block of logic elements and in the case of four units at the inputs of the block of logic elements, this element blocks the propagation of transfer f; Block 8 of logic elements is introduced to realize the addition in the youngest bit of a decade. It consists of logical elements connected in accordance with the formulas for the logical functions V ;, 3 (j, -, FV. Implemented by the block. The block of logical elements of the connection based on the summation rules in decade digits with adders 1 and 3, as well as And 7, i.e., the outputs ,, i / j ,, j are connected to the first, second and third inputs of adder 1, the transfer P through the element OR 6 is fed to the input of the adder 3 and the output Pf is connected to the input of element And 7. Installation inputs the zero is not shown. The device operates as follows. At the same time, the inputs of the decade are You receive summable decimal digits A and 8 in the normal form of the Fibonacci system and transfer from the younger decade P, transfers and the first intermediate figure are formed, then the transfers are summed up and the transfer is blocked from the least significant decade in the case of four units at the input of a block of logic elements , the formation of a second intermediate digit and new carries, and so on, until the formation of transfers stops and a code is formed at the outputs of the adders 1-. Further, this code is rewritten to the normalizer where the result code is normalized using the convolution operation. a) A ", First Intermediate Amount Derived Carriers Blocked Carry On Amount Code 1011 Here, the Amount Code was in normalized form b) Without Blocked Carriage,,,, First First Intermediate Amount and Carry On 1111 Amount Code Amount Code after Normal 1 000 0003 nose nose Thus, unlike the previously known binary-decimal adders, the device speeds up, since if there is a transfer to this decade from a decade less, it is not necessary to add the sum code in this decade to this transfer unit. The device simplifies the summation scheme for decimal numbers and eliminates equipment for correcting and controlling it, respectively, increases the reliability of the node, moreover, simplifies its control over the Fibonacci numbering system and speeds up, so; 002828 as there is no need to perform an additional tick of addition if there is a transfer to this decade from the younger one. invention formula). A device for adding p-digit decimal numbers, each i-th bit of which (1.1,2 .., p) contains four binary adders and the first element OR, the outputs of the sum of the first, second, third and fourth binary adders of the given digit the devices are connected to the outputs of the sum of the given bit of the device, respectively, the first and second inputs of the second, third and fourth binary adders of this bit mouth. roystaa connected to the inputs of the first and second operands of this bit of the device, respectively, the transfer outputs of the second and third binary adders of this bit of the device are connected to the first and second inputs of the first element OR of this bit of the device, respectively, transfer output of the third binary adder of this bit of the device connected to the third input of the fourth binary adder of the given bit of the device, the transfer output of which is connected to the transfer output from this 5th bit of the device to (+1) - bit device, characterized in that, in order to improve speed, in each i-th bit of the device entered the element And the second element OR and the block forming the operands of the first binary adder and carries in the first, second and third binary adders, first, second the third and fourth inputs of which are connected to the transfer input from (tl) -ro device bit to this J-bit device, to the first and second operands of the i-bit device bit, and to the carry output from the second and third binary adders of this bit yes devices with accordingly, the first, second, third, fourth and fifth outputs are connected to the first, second, third inputs of the first binary adder of a given bit of the device, to the first input of the AND element of a given bit of the device and to the first input of the second element OR of a given bit Yes, the device, respectively, the second input of the second element OR is connected to the transfer output of the second binary adder of the given section of the device, the second input of the AND element is connected to the transfer output of the first binary adder of the given discharge of the device. 2. The device according to claim 1, of which there is a unit for forming operands of the first binary adder and transfers to the first, second and third binary adders contains three OR elements, six AND elements and four NOT elements , taking the first input of the block is connected to the first inputs of the first and second elements AND, the second input of the block is connected to the input of the first element NOT, to the first input of the first element OR, and to the second input of the first element AND, the output of the first element is NOT connected to the second input of the second element AND which output is connected to about the second input of the first element OR, the output of which is connected to the first output of the block, the second and third outputs of which are connected to the outputs of the second and third elements OR, respectively, the output of the first AND element connected to the first inputs of Tra9 2.0 dark and fourth And elements, the third in - block input is connected to the second input of the third element AND, to the first input of the second element OR and to the input of the second element NOT, the output of which is connected to the second input of the fourth element AND whose output is connected to the second input of the second element LI, the output of the third element AND is connected to the first inputs of the fifth and sixth elements AND, the fourth input of the block is connected to the second input of the fifth element AND, to the first input of the third element OR and to the input of the third element NOT, the output of which is connected to the second input of the sixth element And, the output of which is connected to the second input of the third element OR, the output of the fourth element is NOT connected to the fourth output of the block, the fifth output of which is connected to the output of the fifth AND element and to the input of the fourth element NOT. Sources of information taken into account in the examination 1. The author's certificate of the USSR N 488206, cl. G About F 7/385. 19752. USSR author's certificate in accordance with the application If 2807бЗЗ / 18-2, cl. G 06 F 7/385, 1979 (prototype).

Claims (2)

Claim 1. A device for adding p-bit decimal numbers, each i-th bit of which (1 = .1,2 .., p) contains four binary adders and the first OR element, the outputs of the sum of the first, second, third and fourth binary adders of this the discharge of the device is connected to the outputs of the sum of this discharge of the device, respectively, the first and second inputs of the second, third and fourth binary adders of this discharge of the device are connected to the inputs of the first and second operands of this discharge of the device, respectively, the outputs of transfers of the second and If the binary adders of this discharge of the device are connected to the first and second inputs of the first element OR of this discharge of the device, respectively, the transfer output of the third binary adder of this discharge of the device is connected to the third input of the fourth binary adder of this discharge of the device, the transfer output of which is connected to the transfer output from this 5- of the device’s discharge into the (| +1) th discharge of the device, characterized in that, in order to improve performance, the element And, the second e OR element and a unit for generating operands of the first binary adder and transfers to the first, second and third binary adders, the first, second, third and fourth inputs of which are connected to the transfer input from the ((-l) -th discharge of the device to this 5-bit device, to the first and second operands of the i-ro discharge of the device and to the output of transfers from the second and third binary adders of this discharge of the device, respectively, and the first, second, third, fourth and fifth outputs are connected to the first, second, third inputs of the first binary sum For this discharge of the device, to the first input of the AND element of this discharge of the device and to the first input of the second OR element of the given discharge of the device, respectively, the second input of the second OR element is connected to the transfer output of the second binary adder of this discharge of the device, the second input of the AND element is connected to the transfer output the first binary adder of this bit of the device. 2. The device according to claim 1, with the fact that the unit for generating operands of the first binary adder and transfers to the first, second and third binary adders contains three OR elements, six elements, and four elements NOT, and the first input of the block is connected to the first inputs of the first and second elements AND, the second input of the block is connected to the input of the first element NOT, to the first input of the first OR element and to the second input of the first AND element, the output of the first element is NOT connected to the second input of the second element And, the output of which is connected to volts rum input of the first OR gate whose output is connected to the first output unit, the second and third outputs of which are connected to the outputs of the second and third elements or, respectively, the output of the first AND element is connected to first inputs tre- 900282 _{) 0 of the} fourth and fourth elements AND, the third input of the block is connected to the second input of the third AND element, to the first input of the second OR element and to the input of the second NOT element, the output of which is connected to the second input of the fourth AND element, the output of which is connected to the second input of the second OR element, the output of the third AND element is connected to the first inputs of the fifth and sixth AND elements, the fourth input of the block is connected to the second input of the fifth AND element, to the first input of the third OR element and to the input of the third element NOT, the output of which is connected to the second input of the sixth AND element, the output of which is connected to the second input of the third OR element, the output of the fourth element is NOT connected to the fourth output of the unit, the fifth output of which is connected to the output of the fifth element of the element And to the entrance of the fourth NOT.