SU898429A1 - Pulse-frequency dividing device - Google Patents

Description

The invention relates to automation and computing and can be used to divide two pulse frequency signals. The following pulse-frequency divider is known, which contains a reversible counter, a group, the elements AND, a counter, a block of complexity 1. The disadvantage of the device is low speed. The closest in technical essence to the invention is a device containing a control unit, a controlled frequency divider, a reversible counter, two elements AND, a group of potential impulse elements AND, and the inputs of the control unit are connected respectively to the input bus signal-divider, device output and the output of the first controlled frequency divider, the control input of which is connected to the output of the first element And, the first input of which is connected to the first output of the control unit, the first input of the second element And Connected to the second output of the control unit, and the output to the first input of the reversible counter, the addition and subtraction tires of which are connected respectively to the third and fourth outputs of the control unit, and the outputs are connected respectively to the first inputs of the pulse-potential elements AND of the first group, the second inputs of which are combined and connected to n -. that output of the control unit, and the outputs are respectively connected to the set of new inputs of the controlled frequency divider P This device produces the time interval of the RT equal to the difference of the periods of the frequency divider f / and the frequency f equal to

where is fa

- the frequency of the dividend;

  previous result of dividing fj by fj,,

and correction in. the current ATj is the value of pulses with a following frequency equal to the frequency of the dividend until equality is established, i.e.

, ii

(2)

N,

O. A disadvantage of the known device is the low division accuracy.

The purpose of the invention is to improve the accuracy of the device

The goal is achieved by the fact that a pulse counter, a second and a third group of pulsed potential elements AND, an OR element, a register, a second controlled frequency divider and a delay element are entered into the device, the counting input of the pulse counter is connected to the input frequency reference bus, and the input reset the pulse meter - with the output of the delay element, the input of which is connected to the input bus of the signal-dividend and the input of the register record, the outputs and the lower bits of the pulse counter are connected respectively to the first inputs of the pulse of the potential elements of the second group, the second inputs of which are connected respectively to the input buses of a constant multiplier N, the outputs of the pulse potential elements of the second group are respectively connected to the inputs of the OR element, the output of which is connected to the control input of the second controlled frequency divider, the outputs n of the higher bits of the pulse counter are respectively connected to the information inputs of the register, the outputs of which are respectively connected to the first | inputs of the pulsed-potential elements I rd group, the second inputs of which are combined and connected to the output of the second controllable frequency divider and the second inputs of the first and second AND gates, and outputs respectively connected to the inputs of the second mounting controllable frequency divider.

The drawing shows a block diagram of a pulse frequency divider device.

The block diagram of the device contains controlled frequency dividers 1 and 2, reversible counter 3, elements I i and 5, groups of impulse-potential elements AND 6-8, control unit 9, count 984294

pulse pulses 10, the element OR 11, the register 12 delay element 13. The inputs of the control unit 9 are connected respectively to the input signal-signal bus of the tel, the device output and the output of the controlled frequency divider 1, the control input of which is connected to the output of the And element, the second input which is connected to the second input of the second Q TH element AND 5) the second inputs of the pulse-potential elements And 8 and the output of the controlled frequency divider 2, and the first input - with the first output of the control unit 9, the first input

JJ element 5 is connected to the second output of the control unit 9, and the output to the first input of the reversible counter 3, the addition and subtraction bus of which are connected respectively to the third and fourth outputs of the control unit

20

9, and the outputs of the reversible counter, respectively, are connected (with the first inputs of a group of pulse-potential elements I b, the second inputs of which

25 are combined and connected to the fifth output of the control unit 9, and the outputs are respectively connected to the installation inputs of the controlled frequency divider}, the counting input of the pulse counter to is connected to the input bus

30 of the reference frequency, and the reset input with the output of the delay element 13, the input of which is connected to the input bus of the signal-dividend and the input of the register entry 12. The outputs of the low-order bits of the pulse counter 10 are connected respectively to the first inputs of the group of pulse-potential elements And 7, the second inputs of which are connected to the input buses of a constant (knife

40 N, and the outputs with the corresponding inputs of the OR element, the output of which is connected to the control input of the controlled frequency divider 2, the outputs and the higher bits of the pulse counter

 10 are connected to the information inputs of the register 12, the outputs of which are respectively connected to the second inputs of the group of pulse-potential elements AND 8.

50 Register 12 consists of D-flip-flops, the 0-inputs of which are the inputs of the register, and the synchronization inputs of the flip-flops are connected and connected to the input of the register entry.

55 The delay element can be made in the form of RC-chains.

Claims (2)

The device works as follows. n to the best bits of the pulse counter 10, the group of pulse-potential elements AND 7 and the element OR 1T form an integrator with sequential transfer, the output of which forms a pulse-frequency sequence with the following frequency f: f, (3) where% is the reference frequency N -constant multiplier arriving at the input of a controlled frequency divider 2 o During each period of the frequency of the divisible fj and n higher bits of the counter of pulses 10, the number of pulses N is calculated by the frequency of the following,, m -, nr - r.fj the beginning of each next his period fj. transferred to register 12, and the n most significant bit of pulse counter 10 is reset to zero. The controlled frequency divider 2 determines the division of the frequency f by the numbers j, the reverse code of which is transferred to it from register 12 with appearance and pulses at the output, the frequency of which is equal to: f В JL, At the beginning of each period the frequency of the divider f, if time is not performed correction of the state of the reversible counter 3 in the control unit 9, a positive potential is formed, arriving at the input of the element And l and allowing the pulse-frequency sequence f to pass at the input of the controlled frequency divider 1, Last produced um frequency division code f on the previous result for dividing f f -N etw i.e. the pulse at its output is Vits through time T from the beginning of period f: A / you T –RG-If the equality is 1 7, i.e. taking into account expressions (5) () (Z TO at the first input of element 5, there is always a zero potential that prohibits the passage of pulses from 8 9 4 outputs of controlled frequency divider 2 to the input of the reversing counter 3i, the state of which remains unchanged. If equality (7) is not complied with, the control unit 9 allocates the time interval DT, equal to AT4 T - –g - –J, during which a positive potential is applied to the first input of the And 5 element, allowing the pulses to pass through the input frequency of the reversible counter, which produce co The conversion of the previous ref, to f,, N as a result of dividing the value of / NBW, (10) at the time of the end of the time interval ΔT |, negative potential is applied to the first inputs of the elements And t and 5, prohibiting further input of pulses to the inputs of the controlled divider 1 and the reversible counter 3 and the reverse code of the number N jy, which direct cdd forms with in the reversible counter 3, by this time point ... 1 ... fj Nf.dl) N ", off" -BHXi ti is transferred to the controlled frequency divider 1 . The fact that the correction Nj must be made exactly by the value of U, N ja I, determines yus from expression (10), can be seen from the following statements. (f - D) taking into account the difference Af Wfeb, 9s of ations (3) - {6) is in I,. || Mf .-) t. -VNeWKj, whence & N a, taking into account the fact that AMout, DT Thus, the proposed time of a totally pulsed dividing device differs favorably from the known one, since it has a much more high division accuracy. The error of the result of dividing 5 of the known device with regard to the expression (2) is the error of the result of dividing the proposed device with regard to the expression (tl). From the comparison of the observations, it is clear that the formula of the frequency-pulse dividing device containing a controlled frequency divider , reversible counter, two elements And, a group of pulse-potential elements And, a control unit, and the inputs of the control unit are connected respectively to the input bus of the signal-divider output of the device and the output of The controlled frequency divider, the control input of which is connected to the output of the first element I, the first input of which is connected to the first output of the control unit, the first second of the second element I is connected to the second output of the control unit, and the output to the first input of the reversible counter bus addition and subtraction of which are connected respectively to the third and fourth outputs of the control unit, and the outputs are connected respectively to the first inputs of the pulse-potential elements AND of the first group, the second inputs of which are combined and connected to the fifth output of the control unit, and the outputs are respectively connected to the installation of 9 new inputs of a controlled frequency divider, characterized in that, in order to improve the accuracy of the device, a pulse counter, a second and a third group of impulse-potential elements, are entered into it , the OR element, the register, the second controlled frequency divider and the delay element, the counting input of the pulse counter is connected to the input bus frequency reference frequency, and the reset input of the pulse counter is connected to the output of the delay element whose input is Yuchen to the input bus signal - dividend and the register entry input, the outputs n the lower bits of the pulse counter are connected respectively to the first inputs of pulsed potential elements AND the second group, the second inputs of which are connected respectively to the input buses of a constant multiplier N, the outputs of pulse potential elements And the second group is respectively connected to the inputs of the OR element, the output of which is connected to the control input of the second controlled frequency divider, the outputs of the senior bits of the pulse counter corresponding to connected to the information inputs of the register, the outputs of which are co-OptBTcBeHHo connected to the first inputs of the pulse-potential elements AND of the Third group, the second inputs of which are combined and connected to the output of the second controlled frequency divider and the second inputs of the first and second elements: And, and the outputs are respectively connected the installation inputs of the second controlled frequency divider. .. Sources of information taken into account in the examination 1. The author's certificate of the USSR № 62Ш8, cl. G On. F 7/52, 1978. 2.Karpov R.G. Frequency pulse simulation technique. M., Masha whine swarming, 19b9 (prototype).  t