SU894694A1 - Timing pulse shaper - Google Patents

Description

one

The invention relates to computing and can be used in discrete devices of computing and automation.

Known multichannel clock pulse distributor, containing the elements And the triggers 1.

The disadvantages of the known distributor are the impossibility of obtaining TC4. TKT pulses, the period of which is equal to the period of following the pulses at the input of the distributor, the dependence of the period of the following clock pulses on the number of outputs, the need for a mandatory initial installation and the complexity of the circuit.

Closest to the proposed is a multi-channel clock distributor, containing And elements and triggers 2.

The disadvantages of the known distributor are the impossibility of obtaining clock pulses, the period of which is equal to the period of pulse following at the driver input, the dependence of the period of the clock pulse following the number of driver outputs, the presence of two time-shifted sequences

pulses required for the shaper to work, significant hardware costs to increase the number of clock pulses.

The purpose of the invention is to expand the functionality by obtaining clock pulses, the period of which is equal to the period

10 following impulses at the driver input.

The goal is achieved by the fact that a clock driver containing two flip-flops

15 and four elements And, the outputs of the first trigger connected to the first inputs of the first and second elements And, respectively, the outputs of which are connected to zero and one

20 inputs of the second trigger, respectively, the outputs of which are connected to the first inputs of the third and fourth elements AND, respectively, whose outputs are connected to the unit and zero inputs of the first trigger, respectively, entered the elements NOT, the delay element and the decoder, and the input of the imager is connected to the input of the element NOT and to the second input of the third element And, the output of the element is NOT connected to the second input of the second element And, the single output of the first trigger is connected to the gate input of the decoder, the output is formed l and the input of the delay element, the first output of which is connected to the second input of the first element And, the 1st output of the delay element (, 2, ... n) is connected to the 1st input of the decoder, respectively, the nth input of which is connected to the second input of the fourth element And the outputs of the decoder are a group of outputs of the former.

FIG. 1 shows a clock pulse shaper, a functional diagram, FIG. 2 is a timing diagram explaining the operation of a clock shaper forming a clock grid of four pulses.

The functional diagram of the clock pulse generator contains the input 1 of the driver, the element HE 2, the elements OF and 4, trigger 5, the elements 6 and 7, the trigger 8, the delay element 9, the decoder 10, the output 11 of the driver.

Input 1 shaper. connected to the second input element And b and through the element NOT 2 connected to the second input element And 3, the output of which is connected to the single input of the trigger 5. The single output of the trigger 5 is connected to the first input of the element And 6, the output of which is connected to the single input of the trigger 8, the unit output of which is connected to the input of the delay element 9, strobe the input of the decoder 10 and the first, the input element And 4. The first output of the delay element 9 is connected to; the first input of the decoder 10 and the second input of the element and 4, the output of which is connected to the zero input of the trigger 5. The zero output of the trigger is connected to the first input of the element AND 7. The nth output of the control element 9 is connected to the nth input of the decoder 10 and p. the second input element And 7, the output of which is connected to the zero input of the trigger 8, the zero output of which is connected to the first input of the element And 3.

Shaper clock pulses works as follows.

If there is no pulse at input 1, trigger 8 is in the zero state, and trigger 5 is in the single state. The impulse, which appeared at the input 1 of the former, arrives at the second input of the element 6 and translates the trigger 8 into a single state. The delayed front FRONT generated at the output of the trigger 8, gates the pulses received at the input of the decoder 10, from the first output of the delay element 9 the pulse arrives at the second input of the element 4, and translates the trigger 5

to zero state. After a time equal to the last output of the delay element 9 of the delay, the pulse converts the trigger 8 to the zero state. The initial state of the trigger 5 is determined by the absence of a pulse at input 1 and the zero state of the trigger 8.

The pulse duration of the unit output of the trigger 8 and the generator output 11 is determined by the n-th output of the delay element 9 and does not depend on the duty ratio of the pulses input 1, and the delay time of the leading edge of the pulse from the first output of the delay element 9 should be less than tj nSo the use of the proposed shaper clock pulse provides clock pulses, the period of which is equal to the period of the pulse at the shaper input pulse formation, the duration of which is not sieve of duty cycle pulses arriving at the input shaper.

Formula (Inventions

The clock pulse shaper contains two triggers and four elements AND, the outputs of the first trigger connected to the first gatherings of the first and second elements And, respectively, the outputs of which are connected to the zero and single inputs of the second trigger, respectively, the outputs of which are connected to the first inputs of the third and fourth elements And, respectively , the outputs of which are connected to the single and zero inputs of the first trigger, respectively, characterized in that, in order to expand the field of application, by obtaining Cto pulses, the follow-up period of which is equal to the follow-up period of the pulses at the input of the imaging device, the elements NOT, the delay element and the decoder are entered into it, and the input of the imaging device is connected to the input of the NOT element and to the second input of the third element AND And, a single output of the first trigger is connected to the gate input of the decoder, the output, the driver and the input of the delay element, the first output of which is connected to the second input of the first element And, the 1st output of the element The supports (, 2, ..., p) are connected to the 1st input of the decoder, respectively, the nth input of which is connected to the second input of the fourth element, And, the outputs of the decoder

are a group of outlets formed. tel.

Sources of information / taken into account in the examination

USSR certificate 06 F 1/04, 1974.

USSR certificate About F 1/04, 1976

Claims (1)

Claim A clock generator containing two triggers and four AND elements, the outputs of the first trigger connected to the first junctions of the first and second elements AND, respectively, the outputs of which are connected to the zero and single inputs of the second trigger, respectively, the outputs of which are connected to the first inputs of the third and fourth elements AND, respectively the outputs of which are connected to the unit and zero inputs of the first trigger, respectively, characterized in that, in order to expand the scope, by obtaining new pulses, the repetition period of which is equal to the repetition period of the pulses at the input of the shaper, HE elements are introduced into it, a delay element and a decoder, and the input of the shaper is connected to the input of the element NOT and to the second input of the third element AND, the output of the element is NOT connected to the second input of the second element And, the single output of the first trigger is connected to the gate input of the decoder, the output, the driver and the input of the delay element, the first output of which is connected to the second input of the first element And, the i-th output of the delay element and (1 = 1,2, ..., n) connected k.i th entry decoder, respectively, n-th input is connected to the second input of the fourth AND gate, the outputs of decoder? are the group of outputs of the shaper.