SU862236A1 - Amplifier using cigfets - Google Patents

Description

I

A device for converting voltage levels 1 is known, in which g-type, p-type transistors and a second transistor type are connected to the input. The device serves to coordinate with TTL circuits, however, it does not function as a latch, i.e., store information.

The closest in technical essence to the invention is a high-speed amplifier on CMD transistors 2, which contains two p-type key transistors and two P-type load transistors, connected according to a trigger circuit, two P-type transistors, whose sources are connected to the zero potential bus, and the gates to the first control pitch, and two p-type reset transistors, whose drains are connected to the drains of the corresponding p-type key transistors and with the amplifier outputs, the sources with the sources of the key transistors p-type and power supply, and the gates are connected to the second control bus, the first and second bit buses (input data buses), two matching-type transistors, whose sources are connected to the drains of the corresponding key-type transistors,

the drains are from the sources of the corresponding load-type transistors, and the gates are correspondingly with the first and second bit buses.

The disadvantages of this amplifier are limited functionality;

5 the need for a differential input signal and the impossibility of using a circuit for direct connection with TTL circuits in latch mode.

The aim of the invention is to enhance the functionality of the amplifier by providing a memory function. The goal is achieved by the fact that in an amplifier on CMDF transistors containing two p-type QC transistors and two n-type load transistors, united in a trigger circuit, in which the drains of the first key and load transistors are connected to the direct output of the amplifier and to the gate of the second key and load transistors, the drains of which are connected to the inverse output of the amplifier

20 and to the gates of the first key and load transistors, the origins of the key transistors of the trigger are connected to the power bus, two matching transistors-type.

the drain of each of which is connected to the source of the corresponding load trigger, two key P-type transistors, the drain of each of which is connected to the source of the corresponding matching transistor, and the source of the first d-type key transistor is connected to the zero potential bus, and the gate to the input information bus, two p-type reset transistors, the drains of which are connected to the drains of the corresponding p-type key transistors, the sources with power supply, and the gates with the control bus, additional reset transistors are introduced L.-type, the sources of which are connected to the zero potential bus, and each drain - to the corresponding source of the load transistors of the L.-type trigger, gates - to the gates of matching fv-type transistors and to the gates of the p-type reset transistors The type is connected to the input data bus, and the shutter is connected to the power bus.

The scheme of the proposed speed. Amplifier on CMPE transistors is given in the drawing.

The amplifier contains two p-type key transistors 1, 2 and two P-type load transistors 3, 4 connected according to a trigger circuit, two p-type reset transistors 5, 6, two T1-type key transistors 7, 8, two matching transistors a type 9, 10, control bus 11, input information fuHHy 12, two reset transistors 13, 14 L-type, direct 15 and inverse 16 outputs, power supply bus 17 and zero potential bus 18.

The sources of the transistors 1, 2 are connected to the bus 17, the drains to the drains of the transistors 3, 4 and the outputs 15, 16. Moreover, the transistors 1, 3 are connected to the direct output 15, and the transistors 1 to the inverse 16. , 3 are connected to the output 16, and the gates of the transistors 2, 4 - to the output 15. The sources of the transistors 5, 6 are connected to the bus 17, the drains - to the outputs 15, 16, and the gates - to the bus 11. The drains of the transistors 9, 10 are connected to the sources of transistors 3, 4, respectively, and the sources of transistors 9, 10 - to the drains of transistors 7, 8, respectively. The source of the transistor 8 is connected to the bus 18, and the gate to the bus 12. The sources of the transistors 13, 14 are connected to the bus 18, the drains to the drains of the transistors 9, 10, the gates to the gates of the transistors 9, 10, 5, 6. The source of the transistor 7 connected to the bus 12, and the gate to the bus 17.

Depending on the ratio of the sizes of the transistors, the amplifier can operate in an amplifier or a key mode.

In the amplifier mode, which provides high speed, the transistors 13, 14 are selected several times more than the transistors 7 - 10. In this case, the amplifier

works as follows: in the initial state (storage mode in the memory) on the control bus 11, the potential corresponds to the logical "O. As a result, the transistors 6 5 are open and at both outputs of the circuit 15, 16 the logic levels are set to "1 (equivalent to the absence of information in the memory, the opening transistors 3, 4 and the closing transistors 1, 2. The parasitic capacitances at the nodal points of the circuit B and A are charged to potential Transistors 9, 10, 13, 14 are closed, so the circuit does not respond to the input information on the bus 12. In this mode, bus 12 must be installed, the input information.

In the input memory reception mode (memory access mode), the potential on bus 11 is changed to "1. Transistors 5, 6 are closed, and transistors 9, 10, 13, 14 are opened.

If the potential 12 is present at the input 12, then the transistor 8 is open and the transistor 7 is closed. The parasitic capacitances at the nodal points of the Li circuit begin to discharge, and the discharge rate of the capacitance at node B is higher, since the total resistance of the open transistors 8, 10, 14 is lower than the resistance of the open transistor 13 (it is assumed that to improve the sensitivity of the s. Circuit (: i.e., the sizes of the transistors 1, 7, 9, and 13 are respectively equal to the sizes of the transistors 2, 4, 6, 8, 10, and 14. When the potential in the node B decreases to the trigger threshold, the regeneration process leading to quick install full logic At the outputs 15, the level will be set to "1, and the output to 16 will be set to" O.

Similarly, the scheme works when applying to the input 12 "O. In this case, the transistor 7 is opened, and the transistor 8 is closed. At the same time, the capacity of the node L is discharged faster, and the level "O" is set at the output 15, and "1" at the output 16.

In the described reversal mode, after triggering and establishing logic levels at outputs 15, 16, information at input 12 of the circuit may change, since transistors 13, 14 are open, and redistributing the resistances at nodes A and B relative to bus 18 will not affect the initially set state trigger

. Thus, the scheme remembers the input information. To change the information on the outputs 15, 16 of the circuit, it is necessary to set the storage mode again, change the information on the input 12 and go to the addressing mode.

Claims (2)

When the amplifier operates in the key mode, the transistors 13, 14 are selected to be minimal in size and necessary to maintain the static state. The principle of operation of the amplifier in the key mode is similar to that described above. In this mode, the circuit noise immunity is high. The trade-off option of the circuit is the use of comparable sizes of transistors 13, 14 and 7-10. The proposed amplifier can be used in integrated memory as a register element installed on the memory address inputs, and (or) as a memory reception and storage scheme in the case of presenting requirements to the integral memory in accordance with the TTL schemes and storing the input information. In addition, the use of an amplifier in integrated memory will reduce the number of integrated circuits in memory by about 10%, since this eliminates the level matching chips and the address register (for memory blocks using TTL-type chips and address registers). Accordingly, the cost will be reduced and the reliability of the memory unit will increase. Claims of the Invention Amplifier on a KMDP transistor containing two p-type key transistors and two c-type load transistors connected in a trigger circuit, with the outlets of the first key and load transistors connected to the forward output of the amplifier and to the gates of the second key and load transistors, the drains of which are connected to the inverter output of the amplifier and to the gates of the first key and load transistors, the origins of the key transistors of the trigger are connected to the power bus, two are consistent, their C-type transistor, with the current of each of which is connected to the source of the corresponding, its load transistor trigger, two key transistors and-type, the drain of each of which is connected to the source of the corresponding match, its transistor, and the source of the first key transistor of the type connected to the bus of zero potential, the gate - with input bus, two p-type collector transistors, the drains of which are connected to the drains of the corresponding p-type key transistors, the sources with the power bus, and the gates with the bus control, characterized in that increase the functionality of the amplifier by providing the memory function, additional reset transistors of the type P type, whose sources are connected to the zero potential bus, and each drain to the corresponding source of the load transistors of the G-type trigger, gates to the gates of matching transistors of the type, and to the gates of the p-type reset transistors, the source of the second C-type key transistor is connected to the input data bus, and the gate to the power bus. . Sources of information taken into account in the examination 1. USSR author's certificate number 558400, cl. H 03 K 19/00, 02.27.76. 2. USSR author's certificate for application number 2668722 / 18-24, cl. G 11 C 7/00, 1978 (prototype).