SU860049A1 - Data ordering device - Google Patents

Description

one

The invention relates to computing and can be used for conducting public opinion polls and working with experts, in information services, and the like.

A data acquisition device is known comprising a dial pad and a solver fl.

The disadvantage of it is that it does not provide an effective ranking process.

A device for collecting information comprising a keyboard, a memory unit and a cathode ray tube 2 is known.

This device provides input values (characteristics or location numbers), but does not allow ranking of data.

The closest to the present invention is a data ordering device comprising an input unit and serially connected information storage unit, write-read unit, main memory and display unit, as well as a control unit connected to the input unit, visual display unit, storage unit and additional external devices (printing and others).

The disadvantage of the device is low speed.

The purpose of the invention is to increase speed.

The goal is achieved by the fact that the device for ordering data containing a data set block, the first information output of which is connected to the first information input of the buffer register, the auxiliary memory block, the input and output of which are connected respectively to the first information output and the second information output.

15 by the input of the buffer register, the information display unit, the first and second information inputs of which are connected respectively to the second information output of the buffer register and the first information output of the main memory, the second information output and the first information input of the main memory are connected to the third information respectively, the input and output of the buffer register, and the control input of the data set unit is connected to the output of the information display unit; a buffer memory block is entered and, a shift unit and a data ranking unit, wherein the second information output of the data set unit is connected to the first input of the data ranking unit, the second and third inputs of which are connected respectively to the third information output of the UN memory unit and the first output of the shift unit, the first output of the ranking unit data is connected to the first control input of the main memory unit, the second output of the ranking unit is connected to the first address input of the main memory unit and to the first input of the shift unit, the second and third outputs the ranging rank is connected respectively to the second and third inputs of the shift block, the first to fourth outputs of which are connected respectively to the second control and second address inputs of the main memory block, to the address and control inputs of the buffer memory block, the information inputs and outputs of which connected to the fourth information output and to the second information input of the main memory unit, the fifth output of the shift unit is connected to the third input of the ranking unit, the fifth output of which is connected to retim information input display unit information.

The ranking unit contains two registers, a comparison circuit, pulse distribution, an address counter, a trigger, and three AND elements, the first input of the block connected to the information input of the first register, the setup input of the trigger and the first trigger input of the pulse distributor, the second, block input connected with the first information input of the comparison circuit, the second and third information inputs of which are connected respectively with the first output of the first register and with the output of the second register, the first output of the pulse distributor with Connected to the first inputs of the first and second elements And, the second output of the pulse distributor is connected to the control input of the comparison circuit, the output of which is connected to the first blocking input of the pulse distributor, the direct output of the trigger And is connected to the second start of the pulse distributor , the inverse output of the trigger is connected to the second input of the first element I, the output of which is connected to the control inputs of the registers, the second output of the first register and the output of the second element I through the third element And connected to the information input of the second register, the third to the sixth outputs of the pulse distributor are respectively the first, third, fourth and fifth outputs of the block, the seventh output of the pulse distributor through the address counter is connected to the second output of the block, the third century; the second blocking input of the pulse distributor, the third triggering input of which and the extinguishing input of the trigger are connected to the fourth input of the block.

The shift block contains three address counters, an address register, two comparison circuits, two AND elements and an impu / dispenser, the first input of the block is connected to the information inputs of the first, BTopoiO address and address register counters, the first information outputs of the first address counter and address register are connected with the inputs of the first comparison circuit, the first, the second outputs of which are connected to the first inputs of the first and second elements AND, the second inputs of the elements AND, the second inputs AND are connected to the second input of the block a, the first and The form {1-action output of the second address counter and the second information output of the first address counter are connected to the second output of the block, the second information outputs of the address register and the second address counter are connected via a second comparison circuit with the first blocking input of the pulse distributor, the outputs of the first, second And elements and the third input the devices are connected respectively to the first, second, third trigger inputs of the pulse distributor, the indicative output of the third address counter is connected to the second blocking input the pulse distributor, the first to the seventh outputs of the pulse distributor are connected respectively to the first, fourth, PYATYA outputs of the block, with the counting input of the third address counter, with the control inputs of the first and second address counters and the address register, the third output address counter information is the third output block.

FIG. 1 shows a block diagram of the device; FIG. 2 - t, a ranking unit; in fig. 3 is the same shift block.

The device for ordering data contains (Fig. 1) auxiliary data block 1, buffer register 2, main memory block 3, information display block 4, data block 5, ranking block, shift block 7, buffer memory block 8 ti.

The ranking unit includes (FIG. 2, pulse distributor 9, address counter 10, comparison circuit 11, registers 12 and 13, trigger 14, elements 15-17, second input 18, first input 19, first output 20 of first register 12, output 21 the second register 13, the Vitoron output 22 of the pair register 12, the output 23 of the third element And 15, bus 24 and 25, the input 26 of the first register 12, the output 27 of the first element And 16, the inputs 28-30 distribute the bodies 9 pulses, the output 31 distributes pulses, input 32 of the second element And 17, fifth output 33 block first output 34 of the block, output 35 of the pulse distributor, third output 3 6 block, the third block input 37, the fourth block output 38, the second block output 39. The shift block contains (Fig. 3, a distributor 40 pulses, address counters 41-43, register 44 and the address of circuit 45 and 46, elements And 47 and 48 , first block input 49, output 50 of the second address counter, output 51 of the third address counter, output 52 and input 53 of the second address counter, output 54 and 55 of the third address counter, input 56 and output 57 of the second comparison circuit, fourth output 58 of the block, output 59 and input 60 of the address register, first output 61 of the block, third input 62 of the block, fifth output 63 of the block, inputs 64 and 65 Pulses, input 66 and outputs 67 and 68 of the first comparison circuit, the second block input 69, the input 70 of the first address counter, the second block output 71. The auxiliary memory unit 1 provides for storing questions with answers to them on any machine medium with the possibility of its subsequent entry into a computer for automatic processing. In such a unit, various types of storage media can be used, in particular magnetic tapes and magnetic disks. The main memory unit 3 is designed to store information (a question and a set of answers), which is displayed on the screen of unit 4. The latter can also have its own internal memory to provide an indication (for example, when using a CRT tube). Block 5 contains ten numeric keys and at least three control keys: a continue selection key (Then, a selection end key (Start) and a transition to a new frame (Forward) key consisting of a question and a set of answers. Rank block 6 provides general process control, the shift unit 7 controls the actual movement of information / and the buffer memory unit 8 stores one option of the answer — one line of the screen — during the shift process. The proposed device works as follows. The device presses the key to move to a new frame. As a result, block 5 iiariycbaor register 2 itself becomes locked (FIG. 1). The register controls block 1. and provides reading; next to the next frame of information and recording it (writing) into the main memory block 3. After the end of the readout, the register 2 starts the block 4. The latter carries out an indication of the information not coming from its screen from the block 3 of the main memory, and removes the lock in the block 5. Thus, it becomes possible to press further keys, as indicated by p Adding information on the screen. Let the screen have a capacity of ten lines, the first of which is a question, and the remaining nine answer choices that have If the pre-monomer says that there are no numbers in the answer text, the answer numbers can be identified by digit codes (otherwise a special character is required for the response number flag and a separator between the number and the response text). in the following, we assume that there are no numbers in the answer text, the answers themselves are arranged in order of increasing numbers, and the numbers are located at the beginning of the line. Since the operation of the device is somewhat different for cases of shifting the response up or down, we will consider them separately, although the way of working is the same. Let the subscriber want to place on the screen of block 4 after the answer number 2 the answer number 5. To do this, dial the number of the answer selected first, i.e. digit 2 In this case, the code of the last of block 5 at input 19 (FIG. 2) is entered into register 12. Then, press the continue selection key. At the same time, from impulse 5, impulse, KO1, enters the ranking. Running along the input 28, the front edge triggers the distributor 9 to the pulse, b, and sets the rear edge to trigger 14 (in the initial state, the trigger is in O). Since at the time of launch of the distributor 9. pulses through bus 30 to it comes O from trigger output 14, then sd. The SP does not start and upon termination of the start-up pulse at the input 28, the distributor 9 pulses generates a pulse to set the number. The last bus enters the elements 31 and It and 17. Since the trigger 14 in this modeHT is already 1, the element 16 triggers, the pulse from which the bus opens the element 1 at bus 27. As a result, the contents of register 12 through the circuit - bus 22-element AND 15-bus 23 is entered in register 13. As a result, there are 2 in both registers. Then the number of the answer selected second is dialed, i.e. number 5, while the code of the last of block 5 at input 19 is entered in register 12. The result in register 13 is provided with digit 2, and in register 12 digit 5. Then press the continue selection key again. In this case, from impulse 5 to impulse block 6, a pulse comes in again, which at input 28 starts distributor 9 of pulses and confirms rotation of trigger 14. Because at the moment of launching distributor of impulses 9, bus 1 receives 1 output of trigger 14, it starts shift. To do this, first of all, the distributor 9 pulses on output 33 stops the operation of block 4, which in turn blocks the operation of block 5. Then the distributor 9 of pulses on bus 35 starts the address counter 10, the output 39 of which is connected to the address input of block 3 of the main memory. According to the commands of the distributor 9 pulses at the output 34 of the block 3 of the main memory, the content of the content cells is sampled at the address from the 10 address counter. The selected code at input 18 is supplied to the comparison circuit 11. In accordance with the control signal received via the bus 25 of the pulse distributor 9, a second input of the comparison circuit 11 is opened, to which the contents of register 13 are fed to bus 21. Counter 10 of the address sequentially enumerates all the addresses of the main memory 3 until the register contents 13 does not match the contents of one of the cells of the main memory block 3. In this case, the comparison circuit 11 clears the signal that goes through the bus 24 to the distributor 9 pulses (in block 6 of the ranking). Under the influence of this signal, the latter generates an address-entry signal, which is outputted at output 38 to shift unit 7. In block 7 of the shift, the address is written to input 61 (FIG. 3 arrives at the pulse distributor 40, which, via bus 60, enables the address to be entered into address register 44 (the address is fed to input 49 from the ranking unit output 39). Next, in block 6, ranking ( Fig. 2) restarts the 10address counter and the pulse distributor 9 at the output 34 allows sampling in the main memory in block 3. However, in this case, the distribution bus circulates on the bus 25, and a third comparison opens in the second pulse so that it contains the memory cells This is compared with the contents of register 12, On the bus 20. In the case of comparison of the codes of the codes from the comparison circuit 11, the bus 24 goes to the pulse distributor 9, which again generates an address-entry signal. The latter from the output 38 goes to the input 62 (FIG. 3) and to the pulse distributor 40 (in block 7 shift), which busses 53 and 70 allows the address to be entered into the counters 42 and 41, respectively. The distributor 9 pulses (figure 2), in addition, generates a shift start signal, which from its output 36 enters the shift block 7. In the shift unit 7, the shift start signal at input 69 (FIG. 3) is fed to the inputs of the elements 47 and 48, the other inputs of which are connected to the comparison circuit 45 by buses 67 and 68. The latter monitors the contents of the counter 41 and the address register 44, which enters the buses 66 and 59. As in our case, the address counter 41 contains the starting address of the response number 5, and in the address register 44 the address of the response number 2, and they are arranged in ascending order, then the contents of the address counter 41 are larger than the contents of the address register 44, as a result of which the comparison circuit 45 generates a signal (potential) on the bus 67. As a result, the shift trigger signal goes to the pulse distributor 40 along the circuit - input 69-element And 47 - tire 64 and starts the shift up. Shift up consists of three stages. At the first stage, the answer option number (one line of the screen) is transferred from block 3 by the memory base to block 8 of the buffer memory. On. in the second stage, the contents of the rows in block 3 of the main memory are shifted so that the answer number 4 moves to the fifth line (the question line has a zero number), and the number 3 moves to the fourth line. In the third stage, the answer option number 5 from block 8 of the buffer memory is entered into block 3 of the main memory, and on the third line. Thus, if before pressing the keys, the information was located in this order (initial location): question, answer / 2 answer, 3 answer / 4 answer / 5 answer; 6 answer, then after pressing the keys, the order of the location of information in block 3 of the main memory and on the screen of block 4 will change: question; 1 answer, 2 answer / 5 answer, 3 answer; 4 reply; 6 reply. Consider the shift block 7 (Fig. 3) in more detail. For convenience, we denote the number of characters in the screen row as N + 1 (it is convenient to choose N-3), the address of the beginning of the line with the answer number 2 is A, and the answer number 5 is B, Then the contents of register 44 of the address are A, and counters 41. and 42 addresses - B. At the first stage, the address from the output 51 of the counter 43 is fed to the address input of the block 8 of the buffer memory, and from the output 71 of the counter 41 to the address input of the block 3 of the main memory. By the command of the distributor 40 pulses, output 61 starts reading in block 3 of the main memory, and output 58 starts writing to block 8 of the buffer memory. At the same time, the contents of counter 43 via bus 55 vary from 6 (in the initial state, this counter is reset) to N, and counter 41 via bus 70 from B to B + N. This process ends when, after adding the next 1 bus 55, the address counter 43 generates a census termination signal which, via bus 54, goes to the pulse distributor 40, after which the counter 43 is quenched. At this point, the first stage is terminated. In the second stage, first, the signal from the pulse distributor 40 over bus 5 subtracts 1 from the contents of the address counter 42. Then, at the address from the output 50 of this counter in the main memory block is read. The selected code is recorded at the new address, which goes to the block 3 of the main memory from the output 71 of the counter 41. At the same time, the read-write control in the block 3 of the bases. The memory is carried out by signals from the output 61 of the distributor 40 and pulses. After each such census cycle, the contents of the address counters 41 and 42 are reduced by 1 on buses 70 and 53j. This continues as long as the comparison circuit 46 to which information is received on buses 52 and 56 does not generate a match signal from the contents of counter 42 and register 44 address, which is not 57 enters the distributor 40 pulses. As a result, the contents of the address counter 42 changes from B-3 to A, and the address counter 41 varies from B + N to A + N + 1. At this point, the second stage is terminated. At the third stage, the address from the output 51 of the counter 43 arrives at the address input of the block 8 of the buffer memory, and from the output 71 of the counter 41 to the address input of the block 3 of the main memory. Pulse distributor 40 at output 58 starts reading in block 8 of the buffer memory and at output 61 writes in block 3 of the main memory. The contents of the address counters 41 and 43 are incrementally after each cycle in the census by signals of the distributor 40 pulses, over the buses 70 and 55. This continues until, after adding the next 1 address counter 43, the census end signal is generated. Last bus 54 enters the dispenser 40 of them pulses, after which the counter 43 extinguishes. with . As a result, the contents of the address counter 41 change from A + N + i UOA + 2N. + 1, and the contents of counter 43 change from O to N. At this, the shift stops and the pulse distributor 40 generates a shift end signal, which from output 63 goes to the input 37 of the distributor 9 pulses in the ranking block 6 (Fig. 2). The latter primarily forms the impulse to set the number. Since the trigger 14 is in 1, then, as described previously, the contents of register 12 are transferred to register 13. As a result, both registers will be 5. After that, the distributor 9 output on output 33 starts block 4, which in turn unlocks block 5 Thus, the subscriber sees on the screen after the answer with no1er2 the answer with the number 5 and gets the possibility of further permutation of the answers (ranking). Next, dial the number of the answer selected by the third one, and press the continue selection key again, after which the answer selected by the third one is placed on the screen, and accordingly, in block 3 of the main memory after the second one. So, if you dial 4 and press the continue selection key, the following order of answers is formed: a question; 1 answer; 2 answer / 5 answer; 4 answer / 3 answer; 6 reply. This is accomplished similarly to that described earlier. Thus, we looked at shifting the response upwards. It has been noted earlier that the operation of the device is somewhat different for the case of shifting the response down. Consider these differences, based on the initial arrangement of information on the screen (and, accordingly, in block 3 of the main memory). Let the subscriber want to place on the screen after the answer number 5 the answer 2. To do this, dial the number 5 with the number, press the continue selection key, dial the number 2 and press the continue selection key again. In this case, in register 13 (Fig. 2) it appears 5, and in register 12, so that by the time the trigger signal arrives at the input 69 of the shift block 7 (Fig. 3), the contents of the address mat 41 are less than the contents of register 44. As a result, the comparison circuit 45 generates a signal on the bus 68. Following this, a shift trigger signal is placed on the distributor 40 pulses along the circuit - input -69-element 48-bus 65 and starts the shift down. The downward shift, as well as the upward shift, consists of three stages, with the first stages being the same in both cases. and in the second stage, the obsessed lines are shifted in block 3 of the main ami so that the answer option with

Number 3 moves to the second line, number 4 - to the third, and number 5 - to the fourth line. At the third stage, the answer option number 2 from block 8 of the buffer memory is entered on the fifth line of block 3 of the main memory. Thus, after pressing keys, the following order of location of information in the frame is established: question / 1 answer; 3 answer / 4 answer / 5 answer; 2 reply / 6 reply.

As before, we will assume that the contents of the register of the address 44 are L a counters 41 and. 42 addresses - In (this means that the address of the beginning of the line

there is a B, and with an answer number

Vetom number 5 - A). Then, after the first stage, in the address counter 41, as before, is formed. At the second stage, the signal from the distributor 40 pulses is added to the contents of the address counter 41 by a signal from the distributor 40. Then, in block 3 of the main memory information is shifted, the reading is performed at the address from the counter 41, and the recording is performed at the address from the counter 42. The contents of the address counter 41 and 42 are increased by 1 signals from the distributor 40 pulses through the buses 70 and 53. The offset stops when the contents of the address counter 42 and the address register 44 coincide. As a result, the contents of the counter 42 of the address changes from B to A, and the counter of 41 addresses changes from B + N + 1, doA + N + 1. At the third stage, the contents of the buffer storage unit 8 are copied to the main storage unit 3, the reading is performed on the contents of counter 43, and the recording - on the contents of address counter 42, as a result of which the contents of address counter 42 change from A to A + N, and counter 43, from O to N. To interrupt the ranking process, dial the number of the last answer and press the end key. After that, as And earlier, the answer chosen last is placed after the previous one, i.e. under him. However, as the ranking continues, the next answer is placed on the screen of block 4 (and in block 3 of the main memory) in the same place, i.e. how 5s start ranking first. The difference lies in the fact that the answers to this point may already be located not in order. When you press the selection end key from block 5, the ranking block 6 (Fig. 2) receives a pulse, which through input 29 triggers the pulse distributor 9, and trailing edge resets trigger 14 into O. Since at the time of triggering, the pulse distribution is bus 30 enters it 1 from the output of flip-flop 14, then a shift is triggered, which is performed in the same manner as described in the wound. After shifting, input 37 of the pulse distributor 9 receives a shift end signal, in response to which it generates a number setting pulse. Since the trigger 14 is already in O at this moment, the element 17 opens on buses 31 and 32, the pulse from which registers 12 and 13 are damped on bus 26. Then the device operates in a similar way. I

So the newly introduced

Blocks, nodes, and communications can improve the speed of a known device by reducing the time spent on ranking by swapping responses in the main memory block and simultaneously on the display block screen. At the same time, the reliability of the information is increased by increasing the degree of visibility of the ranking results.

Invention Formula

Claims (3)

1. A device for data ordering containing a data set unit, the first information output of which is connected to the first information input of the buffer register, an auxiliary memory block, the input and output of which are connected respectively to the first information output and the second information input of the buffer register, information display unit j the first and second information inputs of which are connected respectively to the second information output of the buffer register and the first information output of the main memory block the second information output and the first information input of the main memory unit are connected to the third information input and output of the buffer register, respectively, and the control input of the data set unit is connected to the output of the information display unit, characterized in that, in order to increase speed, it contains a buffer memory block, a shift block and a data ranking block, the second information output of the data set block is connected to the first input of the data ranking block, the second and third inputs of which Connected respectively to the third information output of the main memory and the first output; ohm of the shift block, the first output of the data ranking block is connected to the first control input of the main memory block, the second output of the ran1r1.1 block is connected to the nepniuM address ..: the memory and the first input of the shift unit; the second and third outputs of the ranking unit are connected respectively to the second and third inputs of the shift unit, the first to fourth outputs of which are connected respectively to the second control and second addresses to The signals of the main memory block, with the address and control inputs of the buffer memory block, information inputs and outputs of which are connected respectively to the fourth information output and the second information input of the main memory block; the fifth output of the shift block is connected to the third input of the ranking block; Its output is connected to the third information input of the information display unit. 2. A popl device, characterized in that the ranking unit contains two registers, a comparison circuit, a pulse distributor, an address counter, a trigger and three AND elements, the first block input connected to the information input of the first register, to the trigger trigger input and 1 m input of the pulse distributor, the second input of the block is connected to the first information input of the comparison circuit, the second and third information inputs of which are connected respectively to the first output of the first register and to the output of the second register , the first output of the pulse distributor is connected to the first inputs of the first and second e-signals, the second output of the pulse distributor is connected to a control by the input of the comparison circuit, the output of which is connected to the first blocking input of the pulse distributor, the forward output of the trigger trigger not with the second input of the second element And with the second trigger input of the pulse distributor, the inverse output of the trigger is connected to the second input of the first element And whose output is connected to the control inputs of the registers, the second output of the first the register and the output of the second element And through the third element And connected to the information input of the second register, the third to sixth outputs of the pulse distributor are respectively the first, third, fourth and five fifth outputs of the block, the seventh output of the pulse distributor is connected to the BTOPSJM via the address counter the output of the block, the third input of which is connected to the second blocking input of the pulse distributor, the third triggering input of which and the integral input of the trigger are connected to the fourth input of the block. 3. The device according to claim 1, characterized in that the shift block contains three address counters, an address register, two comparison circuits, two AND elements and a pulse distributor, the first block input connected to the information inputs of the first and second counters addresses and address registers, first information outputs 5 of the first counter of the address and the register of the address are connected to the inputs of the first comparison circuit, the first, second outputs of which are connected to the first inputs of the first and second, respectively 0 And elements, the second inputs of the And elements, are connected to the second input of the block, the first information output of the second address counter and the second information output of the first counter 5 addresses are connected to the second output of the block, the second information outputs of the address register and the second counter of the address are connected via the second comparison circuit with the first blocking input of the pulse distributor, the outputs of the first, second elements And the third input of the device are connected respectively with the first, second, third triggering inputs pulse distributor, indicative output of the third address counter is connected to the second blocking input of the pulse distributor, the first seventh outputs of the pulse distributor are connected respectively, with the first, fourth, fifth outputs of the block, with the counting input of the third address counter, with the control inputs of the first, second address counters and the address register, the information output of the third address counter is 5 third exit block. Sources of information taken into account in the examination 1. USSR author's certificate 0 511683, class G 06 F 3/04, 1977. 2. Authors certificate of the USSR 413473, cl. G 06 F 3/06, 1976. 3. US Patent 3,760,375 cl. 340-172,5, 1976 (prototype).