SU856000A1 - Pulse delay device - Google Patents

Description

(54) PULSE DELAY DEVICE

I

The invention relates to automation and pulse technology and can be used in various instrumentation equipment.

High precision delay devices are known, in which the main device is sequentially connected to a high-speed, highly stable pulse generator and a counter.

However, such devices are highly complex and require a large number of different equipment to be implemented.

It is also known a time delay device containing an input key cascade made according to the scheme of a composite emitter follower on two ppn transistors, the collectors of which are connected to the negative pole of the power source through resistors, the output threshold cascade on ppn -transistor, connected according to the scheme with a common emitter, to the base of which is connected an RC circuit, a common connection point

a resistor and a capacitor of which is connected via a semiconductor diode, connected in direct polarity for the current of the time of the driving capacitor, to the collector of the output transistor of the emitter follower, between the collector and emitter of the input transistor of which is connected a capacitor G22.

However, the stability of the delay time of such a device is very low,

19, the delay times for switching on and off are determined by different R / C transistors. In addition, in such a mouth, the delays are strongly dependent on the voltage fluctuations of the power sources of the device and on other destining factors.

Often there is a need for a device of medium accuracy, which would be distinguished by sufficient simplicity of design and increased stability of time parameters, high speed and low dependence of basic characteristics on. Ali or various destabilizing factors.

The closest in technical essence and the achieved result to the proposed is a device containing a trigger, the installed input of which is connected to the source of triggering pulses, a resistor and a capacitor of the time of setting, connected in series; A comparator is connected to the connection point of which, the second input is connected to the source of the threshold voltage, the comparator output is connected to the trigger reset input, the inverse output of which is connected to the base of the discharge transistor through a resistor, and the collector-emitter junction is parallel to the capacitor time the master circuit, the orsh-gem resistor, the time of the master circuit is connected to the forward output of the Gz trigger trigger}.

However, Such a device can only delay narrow input impedances and, in principle, cannot delay the input pulses of long duration.

The purpose of the invention is to improve the functionality of the device.

The goal is achieved by the fact that in a delay device containing serially connected a signal source, the time specifies the RC circuit, parallel to the time of which capacitor a discharge key is connected, and a comparator, another input connected to a resistive voltage divider, power supply, a second resis - a tive power supply voltage divider, a key device, an AND element, a pulse shaper and a one-shot; the device output is connected through serially connected For example, a short pulse and a single-oscillator are connected to the input of the bit switch and at the same time - - to one of the inputs of the element I, another input connected to the input of a device whose output is connected to the control input of a key device with one pole connected to the output circuit, and the other through the second resistive divider voltage to the power source to which the signal source is connected.

FIG. 1 shows a functional diagram of the device; in fig. 2 voltage plots to explain the device operation.

The delay device jTNf pulses contains the source 1 delayed to the pulses, the time is given by the RC circuit 2, the code of which is connected, for example, to the non-inverting input of the comparator 3, and the input 1 is connected to the resistive voltage divider 4.

The output 5 of the comparator 3, which is simultaneously the output of the device, and the input of the device are connected to the inputs of the element I b, the output of which is connected through a serially connected driver

5 short frequency pulses and a single vibrator 8 are connected to the input of the bit switch 9 connected in parallel with the time of the driving capacitor of the RC circuit 2, and simultaneously to the control input of the switch Q of the device 10, one pole of which is connected to the output; C-tspi 2, and the other - through resistive jibifi divider 11 on; The device is connected to the field bus of the source (device bars + Ep), parallel to which the resistive voltage dividers 4 and 11 are connected, as well as the source of delayed pulses.

Pulse delay device works in the following way.

When a sub-device is connected to a device, the supply voltages at the device input and output 5 of the comparator 3 are set to zero voltage levels. At the same time, under the influence of low voltage levels at the outputs of the element AND b of the comparator, the key device 1О and the bit key 9 are open and do not have any influence on the operation of the device. Gender Exposure

 the input amplitude pulse (Fig. 2a) p to be delayed, the time specifying the capacitor — the R C circuit 2 begins to charge exponentially, rushing to the level, and Y (Fig. 26}. Further, KOI

5 yes, time for setting the time of condensation. Sator reaches the threshold level POR W / 2 (. 2b), set using resistive divider 4, logical zero, acting at the output

50 5 of comparator 3, alternating with a logical unit (Fig. 2c). The moment of occurrence of a logical unit at the output 5 of the device is sent the moment of the formation of the leading edge of the output pulse delayed relative to the leading edge of the input pulse for a given time interval:

Claims (3)

at the same moment of time, the low level of the voltage at the output of the AND 6 element (Fig. 2 g) is replaced by a high one, which is further maintained during the time of action of the input pulse. Under the action of a high voltage level at the output of the And 6 element, the key device 10 closes, creating conditions for a fast dose of the time of the driving capacitor R С-Цапи 2 to the level set by the resistive depot of the voltage 11, and equal amplitude And input impupes. Subsequently, the capacitor R of the C-circuit 2 remains connected to the power supply + E until the moment of loss of the input pulse, after which the key device opens and the time setting capacitor, discharged to the UVTI level, begins to discharge in an exponential rate determined by the constant time, the time of the master circuit of the CS circuit 2. After the time tijg and JSbpg, the voltage at both inputs of the comparator 3 is compared and the latter returns to its initial state, characterized by a low voltage level at its output 5. Under the influence of atelnogo perapada voltage generator 7 short impupsa vyrabatshaet output device 5 nmpuls trigger monostable multivibrator 8 which, in turn, generates a positive pulse, which is closed under the influence of the discharge switch 9, connected in parallel with capacitor predetermined time. After discharge, the time of the master capacitor after a time –fc times, the cycle of operation of the device ends. The maximum delay time provided by such a device is equal to the duration of the input pulse. Since the signal source and both resistive dividers 4 and 11 of the voltage are powered from the same source + EP, the time delay in such a device depends little on the fluctuations of the supply voltage, since during fluctuations in the voltage of the power supply almost within the same limits The oscillations of the input pulse and voltage level vary according to the mentioned resistors and 4 and 11 voltages. This device is also distinguished by a short recovery time, since the follow-on period of the input pulses is defined as tn + tgoA-tpae hfc-Lpa, and 4 HzAA. In the proposed device, the delay time of the fronts of the input impedance can be adjusted by changing the transfer coefficients of resistive dividers 4 and 11, which expands its functionality. Claims of the Invention A device for delaying ICT pulses, containing a signal source connected in series, the time specifying an RC chain; parallel to the capacitor of which a bit switch is connected, and a comparator, an Apynnvr input, is connected to a remote voltage divider of the power supply, characterized in that, in order to expand the functionality, a second power supply voltage divider is introduced into it, the key device the element And, the driver of the short so-called pulse and the one-shot, while the output of the comparator through the serially connected driver of the short-term pulse and the one-shot are connected to the input of the discharge switch and to one The other element is connected to the input of the device, the output of which is connected to the BKOAON-T control key ycTpoii TBQ, with one pole connected to the output, the time of the RC control unit, and the other with the midpoint of the second resistor A power source stub to which a signal source is connected. Sources of information taken into account in the examination 1. USSR author's certificate number 535727, cl. H 03 K 5/13, 30.O7.74. 2. USSR author's certificate number 392562, cl. HO1 H 47/18, 24.O2.71, 3. USSR author's certificate number 632059, cl. H 03 K 3/284, 11.O5.77 (prototype).