SU842832A1 - Function generator - Google Patents

Description

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The invention relates to automation and computing, to devices for the functional conversion of pulse frequency signals.

A known converter designed to functionally convert pulse frequency signals 1,

A disadvantage of the known converter is the insufficient conversion accuracy due to the direct proportional relationship between the conversion accuracy and the equipment volume.

Of the known devices closest to the proposed invention, the technical essence is a functional converter comprising a pulse generator, an argument counter, a decoder, a linearization counter, a group of AND elements, an OR-NOT element and a ZI-OR element, and the output of the pulse generator is connected to the input counter AB, of the instrument, the outputs of the higher bits of which are connected to the inputs of the decoder unit, the outputs of the first group of which are connected to the first group of information inputs of the linearization counter, the outputs of the element And

groups are connected to the inputs of the element OR NOT 12.

However, the known converter has insufficient conversion accuracy due to a large number of decoders with increased requirements for conversion accuracy.

The purpose of the invention - pov yenye

0 conversion accuracy

(The goal is achieved by the fact that a functional converter containing a pulse generator, an argument counter, a decoder, a linearization counter, an AND group of elements, an OR-NOT element, and a ZI-OR element, the output of the pulse generator is connected to the argument counter input, the senior outputs

The 0 bits of which are connected to the inputs of the decoder unit, the outputs of the first group of which are connected to the first group of information inputs of the linearization counter, the outputs of the AND elements of the group are connected to the inputs of the OR-NOT element, in addition: a pulse distributor, a trigger, a group of AND-NOT elements are entered a group of triggers for linearization sections, a trigger for control, an AND-NOT element, and

0

the low-order outputs of the argument counter are connected to the information inputs of the pulse distributor, the control input of which is connected to the output of the pulse generator, the first and second outputs of the pulse distributor groups are connected to the trigger inputs whose output is connected to the synchronization input of the linearization counter, the outputs of which are connected to the first the inputs of elements AND groups, the second inputs of elements AND of which are connected to the outputs of the second group of the decoder unit, the outputs of the third, fourth and fifth groups of which Connected respectively to the installation inputs of the counter, linearization, inputs of triggers of a group of linearization sections, inputs of a control trigger, inputs of AND-NOT group elements are connected to the outputs of the first group of the decoder unit, outputs of the AND-NE group elements are connected to the second group of information inputs of the linearization counter, third group informational inputs of which are connected to the outputs of the triggers of a group of linearization sections, the output of the element OR is NOT connected to the input of the element AND-NOT and the first input of the element ZI-OR, the second, third second and fourth inputs of which are connected to the third output phase pulse distributor, the second output of which is connected to the fifth input element ZI-OR, sixth, seventh and eighth inputs which are respectively connected to the outputs of the AND-NN, of the decoder output and a control trigger.

The drawing shows the functional Converter block diagram

The functional converter contains a pulse generator 1, an argument counter 2, a pulse distributor 3, a trigger 4, a linearization meter 5, a decoder block B, an AND-NE element group 7, a linearization trigger group 8, a control trigger group 9, element OR-NOT 11, element AND-NO 12, element ZI-OR 13.

Functional Converter works as follows.

The clock pulses from the output of the generator 1 are fed to the input of the counter of argument 2 and the control input of the distributor 3 pulses, the information inputs of which are affected by signals from the lower bits of counter 2. The distributor 3 pulses generates two time-separated pulses at their outputs. from which the trigger inputs 4 are received, the output signals of which are fed to the synchronization input of the linearization counter 5, the information and installation inputs of which at different times, determined by the state of the counter 2, receive impulses from the decoder outputs b, AND-NOT elements 7 and Triggers 8 linearization plots. The linearization counter 5 consists of series-connected meters with different conversion factors. At different outputs of the linearization counter 5, at different times, pulses appear that act on the first inputs of elements AND of group 10, the second inputs of which receive signals from decoders b, allowing only one signal to pass through the element OR-NOT 11 while several signals are present at the first inputs of elements And group 10 from the counter 5 linearization. From the output of element 11, the pulses go to the first input of the element ZI-OR 12 and through the inverter to the first input of the second element AND element ZI-OR 13. The output of the converter passes pulses from the third output of the pulse distributor 3 in those cases when there are no transfer pulses from the output of the counter 5 linearization, i .e. the subtraction mode takes place when the pulse sequence is ceriodically (the period is determined by the conversion factor of the linearization counter 5) pulses are excluded.

 To obtain a continuous sequence of pulses, the so-called No Correction mode is the fourth and eighth inputs of the ZI-OR 13 element, which receives signals from the output of the decoder block b and from the third output of the distributor 3 pulses. The third, fourth, fifth, sixth, seventh and eighth inputs of the ZI-OR 13 element

Addition

used in mode

those. In those cases, when periodically to a continuous sequence of pulses (the period is determined by the recalculation coefficient of the linearization counter 5) it is necessary to add pulses. In this case, the trigger of the operation starts at the required time points, allowing the passage of transfer pulses from the output of the linearization counter 5 and pulses from the second and third 3 pulse distributor outputs. At other times, pulses from the third output of the distributor 3 pulses pass through the second input of the ZI-OR 12 element.

Claims (2)

Thus, the introduction of the listed blocks made it possible to increase the accuracy of the conversion without increasing the volume of the equipment by reducing the number of decoders and more fully using the internal structure of the linearization counter. The invention includes a functional transducer containing a pulse generator, an argument counter, a decoder, a linearization counter, an OR-NOT element group and an Z-OR element, the output of the pulse generator is connected to the input of the argument counter, the high-order outputs of the counter are connected to the decoder block inputs , the outputs of the first group of connectors are connected to the first group of information inputs of the linearization counter, the outputs of the AND elements of the group are connected to the inputs of the OR-NOT element, characterized in that, in order to increase and precision, a pulse distributor, a trigger, a group of NAND elements, a group of triggers of linearization sections, a control trigger, an I-NC element, and the low-order outputs of the argument counter are connected to the information inputs of the pulse distributor, the control input of which is connected to the output of the pulse generator, the first and. The second outputs of the pulse distributor group are connected to the trigger inputs, the output of which is connected to the synchronization input of the linearization counter, the outputs of which are connected to the first inputs of the AND group elements, the second inputs of the AND elements of which are connected to the outputs of the second group of the decoder block, the third, fourth and n outputs. the groups of which are connected respectively to the installation inputs of the linearization counter, the inputs of the triggers of the group of linearization sections, the inputs of the control trigger, the inputs of the AND-NOT group elements are connected to the outputs of the first group of the decoder unit, the outputs of the AND-NOT group elements are connected to the second group of information inputs of the linearization counter, the third group of informational inputs of which is connected to the outputs of the triggers of the group of linearization sections, the output of the element OR is NOT connected to the input of the element and NOT and the first input element ZI-OR, the second, third and fourth inputs of which are connected to the third output of the pulse distributor phase, the second output of which is connected to the fifth input of the element ZI-OR, the sixth, seventh and eighth {1st inputs of which are connected respectively to the outputs of the AND-N, element output of the decoder and the trigger of the control. Sources of information taken into account / during the examination 1. USSR author's certificate No. 370716, cl. H 03 K 5/153, 1971. 2. Authors certificate of the USSR 249074, cl. G About F 7/26, 1969 (prototype).