SU842770A1 - Device for data input from the keyboard - Google Patents

Description

one

The invention relates to computing and can be used in devices for entering information into an electronic computer from a keyboard.

A device for inputting information is known comprising a clock pulse generator, triggers, keypads, comparison blocks, a ready signal generator 1.

The disadvantage of such a device is high hardware costs.

The closest in technical essence to the proposed device, containing a counter connected to a decoder connected to a keyboard, the counter outputs are connected to the first And elements, the second inputs of which are connected to the output of the second And element, one of the inputs of which is connected to the inverse output of the older one, and the other input is with the output of the lower bits of the shift register. The input of the shift register is connected to the keyboard. The counter is controlled by the synchronization signals, which simultaneously arrive at the input of the shift register. Each code combination corresponds to a specific key. it

the match is established by connecting the keys to the specific outputs of the decoder. In the initial state (when none of the keys is pressed), the keyboard is scanned, but since all the decoder outputs are open, the generation of the enabling signal does not occur and the issuance of codes from the counter through the AND elements is prohibited. The moment a key is scanned, a signal is generated allowing the issuance of a code from the counter. During the time you press one key there are several.

5 scan cycles. In order for the code of the pressed key to be perceived only once, a lock is inserted, made on the basis of the shift register. At the time of scanning the pressed key, the low-order bit of the register is set to one. Then, synchronously with the scanning operation, the unit is shifted in the direction of the higher, bit. If the unit is found in the high and low bits of the shift register, the output

0 of such a signal is prohibited. A disadvantage of the known device is that, when simultaneously pressing two or more keys, the issue of codes occurs in one (first) scanning cycle. When using such a device in a keypad connected to the central processor, where the exchange time (receiving the code from the keyboard into the processor) can significantly exceed the scan period, the key codes of the pressed keys are lost, which leads to operator error. The purpose of the invention is to increase the reliability of the device. The goal is achieved by introducing a trigger, the OR element, the second and the third AND elements into the known device, the first inputs of the second and third elements AND are connected to the keyboard, the second input of the second element AND are connected to you} the most significant bit of the third register And is with the inverse trigger output,; the outputs of the second and third AND elements are connected to the shift register input, the single trigger input is connected to the output of the first AND element, and the zero input of the trigger is connected to one of the output register moves. The drawing shows a block diagram of the device. the circuit contains a counter 1 decryptor on n outputs 2, keyboard 3, (n + 1) - bit register 4 shift block 5 elements And, output register 6, trigger 7 occupation of the output register, first element; en 8, second element And 9, the third element And 10, the element OR 11, the inverter 12, the bus 13 and 14 signals from the counter to the decoder and the block 5 of the element And, the bus 15 issuing scanned signals, the bus 16 issuing register signals, the bus 17 and 18 issuing rip mo first and inverse signals of the higher bit of the shift register; bus 20 for issuing clock signals of the 21-minute output of a strobe signal, bus 22 for issuing a permission signal, w | For 23 outputs of a prohibition signal, BUS 24 for issuing a reset signal. The device works (by pressing two keys) in the following way. In / the initial state of the output register |; mp 6 and the trigger of the output register 7 are set to zero. At the time of scanning the first key pressed, the registration signal is issued on bus 16 to AND 9 and 10 elements. At this time, the signal passing through the AND 9 element is prohibited by the signal from the shift register 4, and a signal from trigger 7 is present at the input of the AND element 10 allowing the passage registering signal to the input of the register 4 shift. The latter establishes the lower order bit of register 4 shift in unit. At the same time, the tires 18 and 15 receive the enabling signals to the inputs of the element 8. With the arrival of the strobe signal, the bus 21 leaves; element 8, a signal is generated, and bus 22 is fed to the inputs of block 5 of the elements AND and the single input of the trigger 7, as a result of which the code of the scanned key is entered into the output register b, and the trigger 7 is set to one. In the same cycle, one or more (depending on the relative position of the keys) ticks are scanned with the second key pressed. But, if by the time the second key was scanned, the output register had not yet been cleared, i.e. Since the first key code has not yet been transmitted, for example, to the central processor, then both elements 9 and 10 are closed and the recording signal to shift register 4 is not transmitted, and therefore element 8 does not generate a permission signal to issue a second key code. At the same time, with the arrival of each clock pulse on bus 20, the unit shifts in register 4 synchronously with the change in the state of counter 1. So by the time of scanning the first key pressed in the second cycle (n + 1), the 1st shift register register appears in one state It also allows the recording signal to pass through the AND 9 element to the register 4 input. Signal formation at the AND 8 element output is prohibited by a signal from the (n + 1) -th bit of the shift register 4, which results in blocking the repeated entry of the first key pressed. In that cycle, when the trigger 7 is in the zero state, element 11 permits the passage of the recording signal from the second key pressed to the shift register 4. With the installation of the first bit of the shift register 4 into one, the key code is output to the register 6, the trigger 7 is set to the one state. In subsequent scan cycles, a code issue block is provided, as already described in the case of the first key. Thus, in the proposed device, the code of the pressed key is issued only once, but in any scan cycle in the time interval determined by the stay of the key in the pressed state. Since this time is considerably longer than the period of scanning clock pulses, the use of the proposed device increases reliability with processor devices and eliminates the loss of key codes.

Claims (2)

1. Authors certificate of the USSR 618735, class, G 01 F 3/02, 1976. 2. US patent 3,745,536 cl. G 11 C 19/00, 1973 (prototype).