SU834768A1 - Fixed storage - Google Patents

Description

The invention relates to computing and can be used in digital computers and fourth-generation devices. A permanent storage device is known that contains numerical blocks with a large number of communication elements or with a large number of stitched cores 1. However, this device is characterized by low reliability, high power consumption, high uneven load on address buses. The closest technical solution to the present invention is a device containing an address decoder, the outputs of which are connected to the inputs of the storage elements of the accumulator and the control unit, the output of the storage elements of the accumulator are connected to the inputs of the encoder, the modulo adder two, to the first input of which the encoder output is connected, and the second is the output of the control unit 21. The disadvantages of the known device are a large number of communication elements used in the implementation of the device, the large size of the numeric block, low Reliability and device manufacturability. The purpose of the invention is to reduce power consumption and increase device reliability. The goal is achieved by the fact that a permanent storage device containing an address register connected via an address decoder to a drive, a local control unit and a modulo two adder, an additional drive, first and second output registers of the word, and two groups of OR elements, and one from the outputs of the OR elements of the first group are connected to one of the outputs of the additional storage device, the other outputs of which are connected to the inputs of the local control unit, the inputs of the additional storage device are connected to the existing outputs of the address decoder, the outputs of the local control unit are connected to the control inputs of the address register, and the others to the control inputs of the first and second output word registers, the inputs of the first output word register are connected to the outputs of the main accumulator

through the OR elements of the second group, and the inputs of the second output register of the word are connected to the outputs of the main accumulator directly, the outputs of the output registers of the word. are connected to the inputs of modulo two adders, the output of which is connected to one i3 of the inputs of the elements OR the second group

The drawing shows a block diagram of a persistent storage device.

The device contains two groups of 1 and 2 OR elements, an address register 3, an address decoder 4, a drive 5, an additional drive b, output word registers 7 and 8, modulo-2 adders, a local control unit 10.

In the storage device, the recordable source information is pre-processed to reduce the number of units according to the following algorithm. A set of correction codes of the same size as the numbers written in the ROM is selected. At the same time, for a specific code of a number written in the ROM, a code is selected from the set of correction codes, which, after modulo-2 with the code of the original number, would give a code with the minimum number of ones. The converted code of the number is recorded in accumulator 5, but when reading it is necessary, by modulo-adding the two read code (the converted code of the number) with the correction code used, restore the original code of the number. The choice of the number and values of the correction codes may be different.

In practice, in the manufacture of the accumulator matrix, a defect occurs that can be of type O generator or generator 1. Let us introduce the conditional notion of zero failure, which takes place with the same directions of the malfunction and information recorded (i.e. there is a generator type defect and you need to record

or there is a type defect

to sat

generator 1 and need to be recorded), and a single failure for different directions of the fault and the information bit being written. Zero defects do not affect the correctness of the information recording, and for masking single defects (i.e., to correct single failures) bit values In which there are single failures, it is necessary to invert (sum modulo two with one).

The device has the ability to invert a part of the bits of the written numbers by modulo-two summing with correction codes and thus mask the effect of single failures. With

This must be borne in mind that, in the values of bits, in the places where they are recorded there are zero failures, the inversion is not performed, but if there are single failures, the values of bits must be inverted.

If we assume that in the cells where correction codes are recorded there are no failures, then, using the selected correction codes, you can mask the failures that occurred to write the source codes of numbers whose values are not equal to the correction codes. In this case, to restore the original number (a), proceed as follows. When contacting the address of the number a from the accumulator 5, the converted code of this number is read, and from the accumulator the 6-address of the corresponding correction code. After the second call to the main accumulator, the correction code is read, and the module modulo two is performed. If the call is made to the address of the correction code (i.e., the correction code is the source information code), then the required code is immediately read from the accumulator 5, since the correction codes are not converted, in this case for generality in the additional accumulator A fictitious (non-existent) address or a cell address in which a number equal to zero is written is recorded. Thus, when addressing the addresses of the correction codes, it is necessary to double-check the drive 5, since this simplifies the control unit, although the second reference is not necessary. This is how the work in the device is organized when there are no failures in drive 5 and when there are failures in those cells in which no correction codes are written. However, in whose., Where corrective codes are recorded, failures can also occur. In this case, you can proceed as follows. In the cell of the correction code (k), in which there are failures, the code (s) is recorded, which, after modulo-2 summation with one of the converted source information codes or one of the correction codes, would give the required correction code. For example, if it is necessary to write the correction code 1010101 and in the places where the first (2) and second (2) bits of this number are recorded, there are, respectively, zero and one failures, then the cells contain the code aaaaa 11, where the symbol a denotes serviceable cell bits, which can be written either O or. A code (b) is selected, which is either a converted code of a number, or a correction code, such that c (E bk, that is: c - aaaaa 11 b - aaaaa 10 k - 10101101 Depending on the code (b), the choice of which Based on the values in this case, its younger bits, the code (c) is determined. When addressing from the accumulator 5, the code (c) is read, and the address code of the cell, where the code (b) is written, from the accumulator b. After reading the code (b), a modulo-two summation of read codes is performed, i.e. a double call is made to the accumulator 5. In The cell accesses the cell where the code of the number (d) is written, for conversion of which the correction code (k) is used and where there are failures in the write location, the information is read as follows. Simultaneously with the conversion of the converted code (d), the address of the correction code is read (k) However, in the main accumulator at the address of the correction code (k) the code is recorded (c). Simultaneously with reading the code (c) from accumulator 5 from accumulator 6, the address code of the number (b) is read. After reading (b), modulo two (d) @ (c) + (b) (d) is performed; (c) ((b) (k) Thus, if there are failures in the cells of the correction codes, the number of calls to the drive 5 is variable (either two or three). Therefore, either a trigger signal or an extra bit in the drive B, indicating the number of accesses to drive 5, must be entered into the circuit of this device. In the device, extra bits are entered into the device, and if the value of the extra bit is zero, then two calls are made drive 5, and if it is unit, then three hits are made. When one call to drive 5 is necessary, then no cell is required in drive B, since no address is needed for the second call to drive 5. Therefore, when one call to drive 5 is required, you can avoid using dummy addresses. And then the number of cells of accumulator b is less than the number of cells of accumulator 5. There is a possibility, if there are failures in the cells of the recording of correction codes, to twice refer to drive 5, unlike the previously discussed, when the drive b is used three times. For this, the correction code (k) is placed in a cell in which there are no failures or there are failures that do not affect, i.e. they are zero where the code (b) of the number should be written. (b). When addressing to drive 5 at the address of the cell in which the converted code (b) is to be written, the correction code (k) is read, and at the same time from the drive 6, the address code of the cell in which the code is written is written (c) such that the sum modulo two code (c) and correction code (k) would give the number (b). In the cell, in which the correction code (k) should be written and in which there are failures, such a code (d) is written, that after modulo-2 summing it up with one of the converted source information codes or one of the correction codes, the required correction code (k). The advantage of such a permutation is obvious if the correction code used (k) is applied to several numbers of the original information. If you need a double appeal to the drive 5, the device works as follows. The inputs of the OR elements of the first group receive the address code required to read the number. Let it be code (a). On a Signal Record from one of the outputs of the local control unit 10, this code is recorded in the address register 3. The signal Read from the other output of the local control unit 10 code (a) is fed to the inputs of the decoder 4, one of its outputs is energized, and the converted code (b) is read from the accumulator 5, which is written to the corresponding output of the local control unit 10. register 8. At the same time, another one of the outputs of the decoder 4 is excited, and the address code of the correction code used to convert the number (s) is read from accumulator 6. This is code (d). The highest bit of this code is optional, it is associated with the local control unit 10 and indicates the number of calls to drive 5. In this case, the value of the additional bit is O, therefore the number of calls to the drive is 2. By signal Record from one From the outputs of the local control unit 10, the code (d) is written to the address register 3. The signal Read from the other output of the local control unit 10 code (d) is fed to the input of the decoder 4, one of its outputs is excited, and the code (f) is generated at the output of the accumulator 5. Signal from the corresponding output of the 10-unit control unit through the LIE elements of the second group, the code (f) is written to register 7. By the read signal from the outputs of the local control unit 10, the codes recorded in registers 7 and 8 are fed to adders 9 modulo two where is the summation and the presentation of the result through the elements OR of the second group on the register 7. In register 7, the code (bX3 {t) c will be written, i.e. required number.

When triple access to the drive 5, the device operates as follows.

When writing the code address (a) through the OR elements of the first group to register 3, then feeding it through the decoder 4 to the inputs of drives 5 and b, the corresponding code (b) is read from drive 5 and written to register 8, and from drive 6. - reading the address code (s).

The unit in the extra bit indicates that the number of calls to drive 5 is 3. For this, from drive 6, a corresponding signal is given to block 10 of local control. At address (c), a secondary access to drive 5 is made and the code (f) is read and then written through elements AND of the second group to register 7. And from drive 6, the address code (p) is read to access drive 5. By read signal supplied from the outputs of the local control unit 10, respectively, to registers 7 and 8, codes (f) and (b) are fed to adders 9 modulo two, they are summed up and the result (s) is received through the elements of OR 2 of the second group into register 7. On signal Read from one of the outputs of the block 10 local control through the decoder 4, the code 5 reads from the accumulator 5 (t) and feeds it on the signal. Recording from another output of the local control unit 10 to the register 8, respectively. codes (s) and (t) are fed to adders 9 modulo two. The result of the summation (s) through the OR elements of the second group is written to register 7.

Suppose that correction codes are recorded in accumulator 5, and in the cells for their recording, as there were no failures, then when contacting accumulator 5 at one of these addresses from the accumulator, the code 00000 is read. A zero in the additional bit indicates that the number of accesses drive 5 is 2.

The address code (00000) is written to the address register 3, then the decryptor 4 reads the corresponding address at that address.

There is no code, however, there is no code with such an address in drive 5, therefore, when a signal is sent, Readings to registers 7 and 8 only accumulate digits of register 8, where 5 after the first access to drive 5, the corresponding correction code is written to the adder. From the outputs of the adder 9 modulo two, the corrected code is written through the OR elements of the second group into register 7.

In order to record the same information in the proposed device, memory capacity is required.

 + n + 1

5 in

times (at) or in n + k

(+ l) N + n2

times (at) less than n + k

than in the well-known, which is an undoubted advantage of the proposed device, where n is the size of N numbers; k is the number of a number in the additional drive.

The proposed device in comparison with the known with a slight increase in hardware costs has a higher reliability, in addition, it is protected from defects in the matrix I and has a relatively small power consumption.

Claims (1)

Invention Formula A permanent storage device containing an address register connected via an address decoder to a drive, a local control unit and a modulo-two adder, characterized in that, in order to reduce power consumption and increase device reliability, an additional drive is inserted into it, the first and second the output registers of the word and the group of elements OR, and one of the outputs of the elements OR of the first group are connected to one of the outputs of the additional storage, the other outputs of which are connected to the inputs of the local unit controls, the inputs of the additional accumulator are connected to the corresponding outputs of the address decoder, one of the outputs of the local control unit is connected to the control inputs of the address register / and the others to the control inputs of the first and second output registers of the word, the inputs of the first output register of the word are connected to the outputs of the main accumulator via elements OR the second group, and the inputs of the second output register of the word are connected to the outputs of the main accumulator directly, the outputs of the output registers of the word are connected to the inputs of modulo-two adders, the output of which is connected to one of the inputs of the OR elements of the second group. Sources of information taken into account in the examination certificate of the USSR 11 C 17/00, 1972. certificate of the USSR 11 C 17/00, 1971