SU830652A1 - Frequency synthesizer - Google Patents

Description

(54) FREQUENCY SYNTHESIZER

The invention relates to radio engineering and can be used to synthesize changes according to a given law of frequencies in radiolocation, radio altitude measurement, communication technology, etc. A known frequency synthesizer contains a looped controlled oscillator, a mixer, a frequency division unit, a pulse phase detector, a correction unit and an adder, the other input of which is connected to the modulator output, as well as serially connected reference frequency generator and synchronizer, first, second The third and fourth outputs of which are connected respectively to the modulator input, another input of the pulse-phase detector, to the installation and control inputs of the frequency division unit, while the control input block Correction is connected to another output of the LU frequency division block. However, in this frequency synthesizer, the output frequency reproduction accuracy is relatively low due to the low speed of the auto-tuning ring associated with the limited bandwidth of the phase detector, as a result of which the auto-tuning ring does not track high-frequency disturbances. The purpose of the invention is to increase the output frequency reproduction accuracy. To achieve the goal, a frequency synthesizer containing a looped controlled oscillator, a mixer, a frequency division unit, an impedance-phase detector, a correction unit and an adder, another input of which is connected to the output of the modulator, as well as a serially connected reference frequency generator and synchronizer, the first, second, third and fourth outputs of which are connected respectively to the modulator input, another input of the pulse-phase detector, with the installation and control inputs

the frequency division block while ynpat; The input of the correction unit is connected to another output of the frequency division unit, serially connected control unit and phase shifter, the signal input of which is connected to the output frequency reference generator, are connected between the fifth output of the frequency divider and the other control unit input to the first output block frequency division.

FIG. Figure 1 shows the structural electrical circuit of the proposed frequency synthesizer; in fig. 2 time diagrams of work; .on FIG. an example of a specific implementation of a frequency division unit and a control unit.

The frequency synthesizer contains a controlled oscillator 1, a mixer 2, a frequency division block 3, a pulse-phase detector 4, a correction block 5, an adder 6, a modulator 7, a synchronizer 8, a generator 9 of a reference frequency, a phase shifter 10, a control block 11. 1 o 2 o o jr o 22T T The values of Φ are a systematic error that would be introduced in the measurement by the phase discretization method. In the proposed synthesizer, this systematic error is compensated by using the phase shifter 10, providing, after the occurrence of each successive pulse from the output of the BLOCK 3 frequency division, the necessary phase shift Sfig. 2 б7 |, for example, in accordance with the table, it is possible to reduce the sampling period compared cYtg / IV. Plots, frequency synthesizer works as follows.

In the case of the formation of oscillations with linear frequency modulation (chirp), the frequency dividing unit 3 consists of the splitter 12 included in the ring with a variable division factor (DDC), the counter 13, the divider 14 and the adder 15 (Fig. 2a), and the control unit 11 from the series-connected reversible counter 16, the zero-state input of which is connected to the synchronizer. It is known that the minimum possible sampling period Ta b / b is determined by the values of the deviation and duration of the signal TL. In the case where the chirp samples are taken more often, the values of the phase shift associated with frequency modulation are non-multiples of the integer 2jr rad. The table shows the values of r WO 7

neither F, equal phasel; r {chirp oscillations after departure 23Gp glad where n.

Claims (1)

en ".r (iftj) / 3i. JT oh about tg from about glennye on 4kg. 2, correspond to a decrease in the sampling period as compared (by a factor of раза2. When generating oscillations by the linear frequency variation law (Fig. 2), the synthesizer works as follows. Before the start of t-to modulation, the initial frequency f is stabilized in the synthesizer. In this case module 7) is turned off, the reverse counter 16 is set to the zero state, and the code converter 17 generates a command providing a zero phase shift in the phase shifter 10 (FIG. 2 b), and the frequency division block 3 operates in the normal frequency division mode NP p h. At the moment of time IQ (Fig. 2), corresponding to the command to form the chirp oscillations, the modulator 7 is turned on from the reversing counter 16, the voltage is set to zero, and the frequency division unit 3 switches to the variable frequency division mode (B) where R- the number of the pulse, which appears at the output of the frequency dividing unit 3. In the general case, the codes received from synchronizer 8 in the modes of stabilization of the initial frequency and the formation of chirp oscillations can be different, for example (in Fig. 2) N (, a. In addition, from the diagrams shown in Fig. 2 in r, it follows that NN,, 5, etc., unlike previously known schemes, the 3 frequency division block changes its division factor only after the occurrence of each (j, -th pulse at its output gdes./F, The periodicity of the change in the systematic error (see table) allows the use of the reversible counter 16 to obtain periodically repeated codes applied to the input of the converter: a 17 code driver, in which commands are generated that control the phase shift in the phase shifter 10. The frequency divider-35 is part of the frequency divider 3 and is designed to provide the constant dividing ratio DPKD 12 on the measurement period of the phase: phase shifts Φ, Д. Of the cases shown in the table (F., T / 2, F / 4, F / 8, SG / 1 b), its division ratio is 2.4,8 and 16. In the initial frequency stabilization mode, the voltage 13 from the synchronizer 8 is supplied to the counter 13, which ensures Zero number at the output of the counter 13. After the start of modulation, this voltage is removed and the code from the output of the counter 13, the number of the pulse number at the output of the PDCD 12, and therefore the whole unit 3 frequency division, is fed through the divider 14 to the amp and 15t which it is summed with the code from the synphonator 8, for its direct assignment, the code from the output of sum 8 26 of mate 15 is also used to change the gain on the feedback ring in order to equalize the sensitivity to the measured in the pulse phase detectors torus 4 errors. In the case when tj, G / F 2, where P is an integer, the need for divider 14 is no longer necessary, since division by 2 times is done by simply shifting the bits. The expansion achieved in the proposed synthesizer. The passband of the phase detector increases the speed of the FM tuning ring. . fluctuations, which leads either to an increase in the accuracy of reproduction of a given FM law, or to a decrease in the requirements for the characteristics of the controlled oscillator and modulator. The invention The frequency synthesizer containing a ring-connected controlled oscillator, a mixer, a frequency division unit, a pulse-phase detector, a correction unit and an adder, whose other input is connected to the modulator output, as well as a serially connected reference frequency generator and synchronizer, the first the second, third, and fourth outputs of which are connected, respectively, with the modulator input, a pulse phase detector, with the installation and control inputs of the frequency division unit, and the control the stroke of the correction unit is connected to another output of the frequency division unit, characterized in that, in order to increase the reproduction accuracy of the output frequency, serially connected between the fifth output of the synchronizer and other mixer inputs are entered, the control unit and the phase shifter, the signal input of which is connected to the reference generator output frequency, when this other input of the control unit | D control is connected to the first output of the frequency division unit. Sources of information taken into account during the examination 1. USSR Author's Certificate No. 640418, cl. H 03 V 3/04, 1977 (prototype). Pe ffuf4 (fteffntffftatfvf L t |. ; (./ I I 1 I - L.