SU826416A1 - Device for recording information into permanent storage semiconductor units - Google Patents

Description

which is connected respectively to the first input of the synchronization unit, the control input of the address register, and the control input of the first multiplexer, the output of which is connected to the input of the information register, the output of which is connected to the information inputs of the address register and the operational memory, the address input which is connected to the output of the address register and the address input of the interface to the semiconductor memory block, the information output of which is connected to the third information input of the first multiplex ora, the entry of the interface unit is connected to the output of a programmable generator, the control input of which is connected to the output of the comparison unit, the inputs of which are connected respectively to the outputs of the second and tpeTbero bit multiplexers, the control inputs of KOTopbij (connected to the output of the register of information bits The control outputs of the synchronization unit are connected respectively to the control inputs of the control unit of the external storage medium, the RAM unit and the interface unit with the semiconductor block of the permanent memory. These clock inputs / outputs of the synchronization unit are connected respectively to the clock inputs / outputs of the address register, the bit register, the comparison unit and the programmable generator.

In addition, the inputs of the second and third multiplexers of information bits are connected to the information output of the RAM block, the synchronization block

. It contains a generator, a counter and a pulse distributor, and a photo reader with punched tapes or punched cards 4} is used as a block of external media. The main disadvantage of this device is its low speed, since all operations are performed sequentially and there are no means of combining the monitoring of memory blocks, the selection of information to defective memory blocks, etc. due to the lack of functional flexibility of the device, resulting in its low reliability.

The purpose of the invention is to increase the speed and reliability of a device for recording information in semiconductor memory blocks, which leads to an increase in productivity and savings in social labor.

The goal is achieved by the fact that

 Fourth and fifth multiplexers are introduced into the device, the first information inputs of which are connected to the output of the RAM unit, whose information input is connected to the second information inputs of the fourth and fifth multiplexers, the third information input of the fifth multiplexer is connected to the information output of the coupling block, the control inputs of the fourth and fifth multiplexers are connected to the corresponding outputs of the synchronization unit, the output of the fourth multiplexer is connected to the information input the second multiplexer and with the input of the threshold of the interface block, the output of the fifth multiplexer is connected to the information input of the third multiplexer, the output of the programmable generator is connected to the recording input of the RAM block, and the corresponding outputs and inputs of the interface block are connected to the corresponding outputs and inputs of the device . In addition, the interface unit contains an address driver, a write pulse driver and an amplitude discriminator, some of the outputs and inputs of which are the corresponding outputs and inputs of the interface block, the other inputs of the amplitude discriminator are connected to the threshold setting input and to the second control input of the matching unit, respectively and the output of the amplitude discriminator is the information output of the interface unit, the information input of the address shaper is the address input of the interface unit -yuschy input,

The s address shaper is the first control input of the interface unit and is connected to one of the inputs of the recording pulse generator, the other input of which is the record input of the interface unit. This construction of the device allows

without increasing the complexity of the device, increase its speed and reliability by combining the recording, monitoring and selection of information by connecting the appropriate blocks through the fourth and fifth multiplexers to a permanent memory semiconductor block, which can be of any type, since it is located in the node fixing the replaceable mating unit.

0 The drawing shows the functional diagram of the device.

The device contains an external G unit. carriers, control unit 2, left media block, synchronization unit 3, remote control, 4 controls, first multiplexer 5, information register 6, address register 7, block 8

random access memory (RAM), fourth 9 and fifth fifth multiplexers, register of 11 bits, second 12 and third 13 multiplexers, comparison unit 14, programmable

0 generator 15 and interface block 16, which in turn consists of an address driver 17, a write pulse generator 18, an amplitude discriminator 19 n fixation unit 20 of a position of a fixed memory block of an EPROM chip.

5 Information lines are shown on the dashboard with double lines, control buses — single lines, and clock buses — dashed.

In interface block 16, the main inputs and outputs are designated by numbers; address input 21, the first control input 22, the recording input 23, is the information output 24, the threshold setting input 25 and the second control input 26. The corresponding outputs and inputs of the interface 16, going through the fixing node 20 to the EPROM, are the outputs and inputs of the entire device.

The execution of interface block 1b as a structurally complete node is convenient and allows replacing these blocks 16 when programming various types of fixed memory blocks, since each type requires its own timing diagram and electrical signals in accordance with the requirements of technical conditions. Thus, the electrical circuit of block 16 for each type will be different, although the functional circuit remains the same.

The device can perform input control operations that check for the absence of defects in non-programmed EPROM chips or the information content of previously programmed EPROM chips; information input, at which the initial information,. to be written into the EPROM microchip, can be entered into the RAM 8 from punched tape, magnetic tape, computer, reference EPROM chip installed at fixation node 20, from a printout or other document by the keyboard of the control panel 4; programming - recording information into the EPROM microchip; an input control that checks the information of the EPROM chip for compliance with the initial information.

In addition, the device provides for a number of other modes, including self-monitoring, continuous impact of recording pulses on poorly programmable microcircuits, analyzing the programming process, selecting information for defective EPROM chips, or selecting EPROM chips for the required information, turning off the programming algorithm, recording information at. inverse code, finding the desired file in a roll of tape, etc.

The device works as follows.

Using the remote control 4, the operations that need to be performed on the EPROM chip are selected, the source of the initial information is selected, all device registers are reset, the microchip is installed in the fixing unit 20 to control the information recording in it, the programmable generator 15 is started and, if the input control operation is necessary, then the synchronization unit 3 generates control signals, according to which the comparison unit 14 and multiplexers 9 and 10 are set to the input control mode, and resnye

the inputs of the microcircuit installed in the node 20, the fixation through the address driver 17 and the address register 7, the address code of the word being checked is fed. In the input control mode, the initial state of the information register 6 corresponds to the state of the nonprogrammed chip. The information from the information register 6, through multiplexer 9, is fed to the inputs, multiplexer 12 and to the inputs of setting information of the amplitude discriminator 19, which is compared with the information of the EPROM chip stored in it at this address.

Claims (2)

From the output of the amplitude discriminator 19, the information through the multiplexer 10 enters the information inputs of the multiplex 15 plexer 13. The multiplexers 12 and 13, controlled by the register 11, alternately output the information of the corresponding bits of the multiplexers 9 and 10 to the inputs of the comparison unit 14. If the amplitude values of the signals from the outputs of the test the EPROM chip differs from the values provided by the DUT for an unprogrammed chip, then the comparator unit 14 outputs the control signal to the synchronization unit 3, over which the controlled oscillator 5 15 the address, the information of the EPROM chip at that address and the input control reject signal are stopped and indicated. If the amplitude values of the signals from the outputs of the tested EPROM chip correspond to the values provided by specification 0 for an unprogrammed chip, the comparator unit 14 outputs a signal to the generator 15 for which the latter works, and in the monitoring mode it sends pulses for block synchronization 3 to control the : by the bit-maker of bits 11 and by the register of the address 7. Having checked the last bit of the last word, the synchronization unit 3 stops the generator 15 and indicates the end of operation of the device if other operations have not been previously selected on the bullet 4. If the operation of inputting and controlling information from an external medium, for example, a punched tape, is selected, then the external media control unit 2 turns on the photo reader of the external media block I and, after processing the service information codes, outputs information through the multiplexer 5 to the information register 6, produces start signal generator 15 and stop the photo reader unit 2. From the register 6, the information enters the information inputs of the operational memory block 8 and through the multiplexer 9 to the multiplexer 12. The information stored by the memory unit 8 through the multiplexer 10 enters the multiplexer 13. Information from the multiplexers 12 and 13 is set is compared in comparison unit 14 and its inequality in terms of the control signal from comparison unit 14, the controlled generator 15 generates a recording signal by which the input information from the information register 6 is written to the operational memory unit 8. After checking the last bit of the input word, generator 15 generates a signal on which synchronization unit 3 sets the following address in address register. 7 through control unit 2, turns on the photo reader and stops generator 15. External media unit 1 reads information from punched tape through block 2 and multiplexer 5, enters it into information register 6. Unit 2 stops the photo-reading ycTpoffCTBO and, through synchronization unit 3, starts generator 15. Next, the process is repeated as described above until the input of the last word information is monitored. In case of an error in entering the information, the comparison unit 14 and the control unit 2 give the signals 3 to the synchronization unit 3, the device stops, it is indicated: the address, the information entered and the information entered and the type of failure. After entering the information, the device either stops or proceeds to the next programming operation. When programming information, the read from block 8 is operative to us through multiplexer 9 to multiplexer 12, and the information read from chip EPROM installed to node 20 through amplitude discriminator 19 and multiplexer 10 goes to multiplexer 13. Next, like during the previous operations, the information from multiplexers 12 and 13 is compared bitwise by the comparison unit 14 even in the case of a mismatch of information, in which the block (20 reads the signal corresponding to the unprogrammed bi y, and a block of RAM (the signal corresponding to the programmed bit, the generator 15, using the control signal from the comparison unit 14, generates a write pulse, according to which the programming driver 18 generates voltage and current pulses with amplitude and time parameters corresponding to the specifications of the programmable microcircuit After being influenced by the write pulses by the intended programming method, if the ratio of the signals from the RAM and from the EPROM has not changed, the address driver 17 during the action of the write pulses, if not bhodimo forms the address input signals corresponding to the requirements of the specifications for a programmable chip. At the end of the write pulses, the address driver 17 generates the standard logic signals necessary for reading the selected word information from the EPROM chip. If, on the selected bit, from the EPROM chip (node 20 reads the signal corresponding to the programmed cell, and RAM (block 8 reads the signal corresponding to the original signal of the unprogrammed chip), the comparison unit 14 outputs a stop signal and the address, RAM information, information of the EPROM chip is indicated and a programming impossibility signal. In case of coincidence of the information received at the inputs of comparator unit 14, the generator 15 outputs a signal to the synchronization unit 3, according to which the comparator unit 14 is connected the following bits of the EPROM chip (block 20) and RAM (block 8), etc. After monitoring and programming the last word, the synchronization unit 3 stops the program and indicates the completion signal of all operations in the event that the operations selected on the control panel 4 are completed If the output control operation is selected, i.e., the control of correctness of programming according to the established levels of discrimination of the output voltage of the EPROM microcircuit, then, like during the execution of the programming operation, the information from the RAM (block 8) through the multiplex psoria 9 and 12 are fed to one input of comparator 14, and information read from the EPROM chip (block 20), through multiplexers 10 and 13, to another input of comparator 14. During the output control operation, the device operates in the same way as when programming, except for the case when the signal corresponding to the programmed bit is read from RAM (block 8), and the signal corresponding to the unprogrammed bit is read from the EPROM chip (block 20). In this case, the generator 15 generates a reject signal, according to which the synchronization unit 3 stops the program and displays the address, information of the PROM and RAM, and the reason for the stop. If the information contents of the RAM and the EPROM chip match for all words, then after controlling the last bit of the last word, the program stops and the end of all operations signal is displayed. Thus, the proposed device allows to increase the device speed by 2 times and increase the reliability of recording information and the entire device by combining operations without complicating the structures. Claim 1. A device for recording information in semiconductor blocks of a permanent memory, containing a control unit, the output outputs of which are the input-output device, the information output of the control unit is connected to the first information input of the first multiplexer.