SU801294A1 - Asynchronous device for transmitting and receiving discrete information - Google Patents

Description

(54) ASYNCHRONOUS DEVICE FOR TRANSMISSION AND RECEIVING DISCRETE INFORMATION

one

The invention relates to communication kg can be used in asynchronous address communication systems to transmit commands or messages.

An asynchronous device is known for transmitting and receiving discrete information 7 which contains an address coder on the transmitting side, the input of which is connected to the counter input and the first input of the first element AND whose output is connected to the input of the information encoder, the output of which is connected to the first input of the modulator and the input of the element NOT whose output is connected to the first input of the second element And, the second input and output of which are connected respectively to the second input of the first element And and the second input of the modulator, as well as the element or, on the receiving side they are the serially connected threshold block address decoder, the first element I, the counter and information decoder, to the second input of which the output of the second element I is connected, the inputs of which are connected respectively to the first output of the decision block and the output of the address decoder, while the second input of the first element I is It is given by the input input l.

However, the known device has a low speed information transfer.

The purpose of the invention is to increase the speed of information transfer.

The goal is achieved by the fact that in the device on the transmitting side, the counter output is connected to the first input of the OR element, the second input and output of which are connected respectively to the output of the address encoder and the second input of the first AND element, and serially connected memory block and block of elements are input on the receiving side And, the second input and output of which are connected respectively to the output of the address decoder and the third input of the information decoder; moreover, the first output of the decision block is connected to the input of the memory block, the second output of which is connected to input threshold block.

The drawing shows a structural electrical circuit of the proposed device.

Claims (1)

The asynchronous device for transmitting and receiving discrete information contains on the transmitting side address coder 1, counter 2., first AND 3 element, OR 4, information coder 5, modulator b, NOT element and second AND 8 element, decisive on the receiving side unit 9, threshold unit 10, address decoder 11, memory unit 12, first element 13, count 14, information decoder 15, second element 16, and unit i 17, the asynchronous device operates as follows. The clock pulses go to the core 1, to the counter 2 and to the first element I 3, From the encoder 1 a written sequence is received character-by-character, containing M symbols 1 c d N N positions where (Sherman sequence). If symbol 1 appears at the output of encoder 1, then the corresponding signal passes through the OR 4 element and the first AND 3 element to the input of the encoder 5. If the first information symbol has the value 1, then it passes to the first input of the modulator 6 and is radiated at a frequency f . If this symbol is OO, then it is inverted on the element HE 7 and then through the second element 8, to which the permitting signal is supplied from the output of the element OR 4, is fed to the second input of the modulator 6 and is radiated to the frequency f. If the zero symbol is removed from the output of encoder 1, then the signal to the OR 4 element is not received, therefore, none of the signals arrive at the inputs of the modulator 6 and the signal is not emitted at any of the frequencies (thereby creating a passive pause, required in the Sherman sequence). After all characters of the address code are transmitted, i.e. N so passes, counter 2 is triggered and sends an enable signal to an element or 4, so that the remaining 5 symbols of the Information in the encoder are transmitted to the modulator B's bits, as described above. On the receiving side, the symbols of address and information arrive at frequencies f and f2. In the initial state, all elements And 13 and 16 signals are not passed. The input of the second element I 16 and block 12 from the output of decision block 9 receives the symbols 1 or O, depending on which of the input signals is greater. The input of the threshold unit 10 receives the immediately greater of the signals. If this signal exceeds the threshold, then symbol 1 goes to decoder 11, if it does not exceed - O. Thus, the input of decoder 11 receives the results of distinguishing the characters in the channel with a passive pause, and the input of the second And 16 element - the results of channel with an active pause. Block 12 has N memory cells and performs sliding memory i.e. on each clock cycle stores the values of the last N received characters. In block 17, the number of elements And is equal to M, i.e. is equal to number 1 in the used Sherman sequence, and they are connected to the cells of block 12 that correspond to this sequence. At the time of decoding the address, the signal from decoder 11 reads through block 17 the value of the first M information symbols from block 12, and also supplies the enable signal to the second AND 16 element , whereby the remaining information symbols from the output of decision block 9 also go to decoder 15. Counter 14 counts the pulses passing through the first element And 13 and synchronizes the operation of the device. The proposed device is easy to implement and allows you to increase the speed of information transfer. Asynchronous device for transmitting and receiving discrete information, containing on the transmitting side an address coder, the input of which is connected to the counter input and the first input of the first element And whose output is connected to the input of the information coder, the output of which is connected to the first input of the modulator and the element input NOT, the output of which is connected to the first input of the second element AND, the second input and output of which are connected respectively to the second input of the first element AND and the second input of the modulator, as well as the OR element, on the On the downstream side are the serially connected threshold block, the address decoder, the first element AND, the counter and. information decoder, to the second input of which the output of the second element I is connected, the inputs of which are connected respectively to the first output of the decision block and the output of the address decoder, while the second input of the first element I is a clock input, characterized in that, in order to increase the transmission speed information on the transmitting side, the counter output is connected to the first input of the OR element, the second input and output of which are connected respectively to the output of the address encoder and the second input of the first AND element, and on the receiving side The serially connected memory block and the block of elements And, the second input and output of which are connected respectively to the output of the address decoder and the third input of the information decoder, and to the input of the memory block the first output of the decision block is connected, the second output of which is connected to the input of the threshold block. Sources of information taken into account in the examination 1, Investigation of methods for adapting and tracking the state of a communication channel in information transmission systems with crucial feedback. Report 1 UD 4761, L., 1976, p. 35-59 (prototype).