SU790349A1 - Frequency divider with odd division coefficient - Google Patents

Description

one

The invention relates to a pulse technique and can be used in digital information processing devices in measuring devices and computing devices. five

A known odd-dividing frequency divider containing triggers connected in series, the contact inputs of which are connected to the input of the divider and the outputs 10 of the last and second to last trigger are connected to the inputs of the element OR NOT, the output of which is connected to the information input of the first trigger

11. 15

A known odd-dividing frequency divider containing D-flip-flops, an inverter and an NAND element whose output is connected to the D input of the first D-flip-flop, D input 20 of each of the D-flip-flops, except the first, is connected to the forward output of the previous one D-flip-flop, and the clock input of each of the D-flip-flops, except the last, is connected to the input of frequency divider 25 with an odd division factor, which is connected to the input of inverter 2.

The disadvantage of the known dividers, the frequency with an odd coefficient of AOR

fission is relatively slow.

The goal of the invention is to increase speed.

The goal is achieved by the fact that in the frequency divider with an odd division factor containing D-flip-flops, an inverter and an AND-NOT element whose output is connected to the D input of the first D-flip-flop, the D-input of each of the D-flip-flops, except the first, with the direct output of the previous D-flip-flop, and the clock input of each of the D-flip-flops, except the last one, is connected to the input of a frequency circuit with an odd division factor, which is connected to the input of the inverter, the divider input with an odd division factor is connected to the clock input of the last D-three ger, a direct output of which is connected to a first input of AND-NO element, a second input coupled to an output of the inverter, and an output of AND-NO element is connected to the reset input of the first D-flip-flop.

The drawing shows the structural scheme of the proposed divider.

A frequency divider with an odd division factor contains D triggers 1,2 and 3 of inverter 4 and an I-PB element 5 whose output is connected to the P input of the first D-flip-flop 1. The input of each of the D-flip-flops, except the first, is connected to the forward output of the previous one D-flip-flop, and the clock input of each of the D-flip-flops, except the last one, is connected to the input b of a frequency divider with an odd division factor that is connected to the input of inverter 4, the input b of the divider with an odd division factor is connected to the clock input of the last D-trigger 3, my, whose output oedinen the first input of AND-NO element, a second input coupled to vnhodom inverter 4, and an output of AND-NO element 5 is connected to the reset input of the first O-trilrgera.

A frequency divider with an odd division factor works as follows.

For simplicity, it is assumed that in the initial state the frequency divider is in the zero state. At its input 6 and output 7, as well as at the outputs O-flip-flop 6v 2 and 3, low voltage levels, at the output of the inverter .4 and the output of the AND-HE element 5, to a high voltage level. The D inputs of triggers 2 and 3 are low voltage levels, fed in & respectively from the direct outputs of D-flip-flops 1 and -2. At the D input of the Dtrigger 1 - a high voltage level.

When the input frequency impulse arrives at the input 6, the D-trigger 1 is turned on, and at its direct output — the device output 7 — a high voltage level is set, which is fed to the D input of the D-trigger 2.

When the next input pulse arrives at input 6, the O-flip-flop 2 turns on and a high voltage level from its direct output goes to the D input of the D-flip-flop 3.

With the arrival of the next), the pulse is switched on by the O-trigger Z. and from its direct output the HIGH voltage level is fed to the first input of the NAND element. five.

When the voltage level at the input 6 of the divider is set and, therefore, the output of the inverter 4 is a high voltage level, a low voltage level appears at the output of the AND-HE element 5, which enters the O-trigger reset input 1, turns off the last one. At output 7, a divider appears at a low voltage level. This voltage is applied

to the D input of the D-flip-flop 2. With the arrival of the next pulse at the input b, the D-flip-flop 2 is turned off. With the arrival of the next impulse, the D-flip-flop 3 is turned off. The post voltage level is low. Puts the input element AND-HE 5 and sets a high voltage level at its output, which is the enable signal for D-flip-flop 1.

With the arrival of the next input pulse b-trigger. 1 is turned on again, i.e. the division cycle is repeated. Thus, a frequency divider with an odd division factor synchronously generates at output 6 f pulses, the duration of which

r-iill-,

vy 2

where n is the number of triggers in the divider;

0 Tg - the period of the following input pulses.

The period of the output pulses

 vb x-Gv S - 5 from the outputs of the rest of the triggers, except for the first one, pulses of duration hc-sf ,, (i-1) TEX are formed

and the period you% 77 (,

Claims (2)

1. The patent of France W 2082620, cl. H-03 K 23/00, 1970. 2. Patent ClflA 3943379, cl. 307-225 R, 1974 (prototype).