SU790283A1 - Code-to-pulse-width modulated voltage converter - Google Patents

Description

The invention relates to electrical engineering and can be used to accurately convert the code into constant voltage, and also as a high-speed 5. scaled DC-voltage converter in precision voltmeters, voltage calibrators and analog-to-digital computing devices. 10

Code-to-voltage converters based on pulse-width modulation make it relatively easy to realize high accuracy and therefore have found widespread use in measurement technology.

However, their ability and scope are limited by their low speed, due to the need to average the continuous sequence of latitudinally-monitored pulses over many repetition periods, the required number of which increases with increasing accuracy.

Known converter code 25 to DC voltage with an intermediate conversion of the code into the width of the pulse-width modulated pulses, containing a register, pulse generator, counter ^ 3Q • codes matching scheme, trigger and low-pass filter.

An increase in the speed of such a converter is obtained by increasing the frequency and decreasing the amplitude of the pulse-width modulated pulses due to multichannelism implemented by introducing into the circuit a decoding resistive grid and a group of switches with shapers on η channels, as well as several shift registers or counters with decoders (Ϊ].

The disadvantage of such a converter is its high complexity, which is almost proportional to the number of channels (phases), i.e. degree of increase in speed.

A known code-voltage converter with pulse-width modulation, comprising a receiving register, a pulse generator connected to a counter, a coincidence element, a VS filter, the signal input of which is connected via keys to a common bus and a reference voltage source, and a trigger whose input is connected, respectively with the output of the counter and the coincidence element connected by the corresponding inputs to the outputs of the receiving register and counter.

The usually grounded RC filter capacitors in the known converter are supplied with an additional voltage close to the average value generated by a high-speed digital-to-analog converter. Due to euoma, when the change in the transformed frequency is abrupt, the filter capacitors are recharged by a relatively small amount equal to the voltage difference between the additional digital-to-analog converter and the average value of the filter output voltage. This increases the speed of the converter the more, the higher the accuracy and stability of the digital-to-analog converter, the speed of which should be ’higher than the speed of the converter [2].

However, a digital-to-analog converter with such high metrological characteristics (high accuracy, stability, resolution and speed) is a complex device, the number of discharges of which is equal to or greater than the number of bits of the code-voltage converter itself.

Moreover, the performance of such a converter is limited even when using an accurate digital-to-analog converter, since when the voltage across the filter capacitors is reduced, the slope of the exponent decreases and, consequently, the time of the transition process increases. So ^ for example, the time to establish the voltage on the capacitor with an accuracy of 1.0% is 7Ϊ, -a with an accuracy of 0.0 001% - - 14X, rfle'K = RC. It follows that increasing the accuracy of the digital-to-analog converter by three orders of magnitude (0.1% - 0.0001%) increases the performance by only a factor of two.

Another factor limiting the speed of the known converter is the presence of voltage ripples on. filter capacitors, the value of which is significantly increased. occurs as the condenser moves away from the filter output. The large / level of the variable component on the capacitors generally eliminates the possibility of using an accurate digital-to-analog converter to improve performance.

In addition, the efficiency of the known converter increases with decreasing filter time constant paT =? S. However, this increases the ripple уменьшает decreases (with decreasing R) · accuracy due to the influence of the final resistance of the switch in the closed state.

The purpose of the invention is to increase the speed of the code voltage converter.

This goal is achieved by the fact that the code-voltage converter contains a receiving register, a pulse generator, the output of which is connected to the counter input, a coincidence element, an RC filter, the signal input of which is connected through the first and second keys to the common bus and the voltage reference source ₍ and the first trigger, the inputs of which are connected respectively with the outputs of the counter and the coincidence element, to the corresponding inputs of which the outputs of the bits of the receiving register and counter are connected, the unit of formation a module and a sign of code increments, a digital comparator, two AND elements, a bipolar current source, additional keys and a second trigger ·, the first one, whose input is connected to the counter and receiver register setup inputs and to the start bus, while the digital comparator inputs are connected respectively to the code outputs of the counter and the code incrementing unit, and the output is with the second input of the second trigger and the installation input of the code incrementing unit, the code inputs of which are connected to the code inputs and the receiver outputs of the register, respectively, and the sign output is connected to the input of the bipolar current source connected to the RC filter capacitors through additional keys, the control inputs of which are connected to the output of the second trigger and the first input of each AND element, the second inputs of which are connected to the corresponding outputs of the first trigger, and their outputs - to the control inputs of the first and second keys, respectively.

The structural electrical circuit of the Converter is illustrated in the drawing.

The code-voltage converter contains a receiving register 1, to which the converted code, a coincidence element 2, a counter 3 connected to a pulse generator 4, the first and second triggers 5 and 6, an incrementing unit for code 7, a digital comparator 8, two logic elements And 9 and 10, a bipolar current source 11, switches 12, a multi-link RC filter 13, periodically connected with out-of-phase controlled switches 14 and -15 to the voltage reference 16 and the converter common bus 17. Condensers 18, respectively.

The unit for generating increments of code 7 determines the module and the sign of the current increment of the converted code tΔ = - N, and the bipolar current source 11 provides a forced linear charge (with increasing code) or discharge (with decreasing code / during time to, proportional to the value (to the module) the current increment of the converted code АY /

The converter operates as follows.

The digital code of the number Νί stored 5 in the reception register 1 is compared in the coincidence element of codes 2 with the counter 3 code changing from 0 to N _max , the input of which continuously receives pulses from the pulse generator 4. At each transition of counter 3 through the zero state, an output signal appears, setting the trigger 5 in a certain, for example, a single state '5. At the moments of coincidence of the codes of numbers, register 1 and counter 3, coincidence element 2 generates signals that return trigger 5 to the initial zero. its condition. Due to this, a continuous sequence of width-modulated antiphase pulses is formed at the 20 outputs of trigger 5, the duration of which is proportional to the value of the converted code N; , and the 25th repetition period T _about is determined by the capacity of the counter 3. '

In static mode, when the difference between the input N ' _{b + 1} and the output N; of the codes of the receiving register Г is zero (aNi * = 0), trigger b is continuously held in the `` single '' state by the output signals of the START, periodically arriving at its input with a clock frequency of operation of the converter and coinciding in time with those arriving at its other input signals of the digital comparator 8, the duration of which is less than the duration of the START signals. In this case, with the output voltage of trigger 6, the keys 12 are open, the elements 9 and 10 are open, and the antiphase pulse-width modulated pulses from the outputs of the trigger 5 are supplied to the keys 14 and 15, connecting the RC filter 13 to the source of the disputed voltage 16 for the pulse time t _n and to the common bus - for the time between pulses tT — t _h . As a result, a continuous sequence of pulse-width modulated pulses ^ of a fixed am-v plateau E arrives at the RC filter 13 input, the average value of which> emitted by the RC filter, 13 is proportional to the value of the converted the code ΝΪ.

® .dynamic mode, when the difference between the input and output codes of the receiving register 1 is not equal to zero (АΝ; Ф 0) *, the trigger with the START signal is set to a single state, and it returns to its initial zero state after a time Ф AN signal of the digital comparator 8 at the moment of coincidence of the codes of the numbers of the block for the formation of increments of code 7 and the counter

4. At the same time, the digital code 65 of the comparator 8 erases the code stored in the incrementing unit of code 7, as a result of which, with changes in the value of the converted code, a pulse is generated at the output of trigger 6, the duration of which is proportional to the increment of the & code. With a continuous change of the converted code, a continuous sequence of pulse-width modulated pulses is formed at the output of trigger b, duration! which is proportional; values of the change of the converted code A, and the repetition frequency coincides with the repetition frequency T- _g triggering pulses.

For the duration of the trigger pulse, the elements And 9 and 10 are closed, disconnecting the RC filter from the source of the reference voltage 16 and the common bus 17, and the keys 12 are closed, while the bipolar current source 11, which is set to come from the sign

FIELDS pH value by the signal ^ of the output (Evil of a formation of code 7 increments, charges (discharges) the capacitors 18 of filter 13 by an amount proportional to the amount of code change, since £ is proportional to

At the end of the trigger pulse b, the keys 12 open, stopping the charge (discharge) of the capacitors 18 of the filter 13, the elements And 9 and 10 are unlocked and the pulse-width modulated pulses of the trigger 5, the duration of which are proportional to the new value of the converted code, after normalization in amplitude arrive on an RC filter, the average voltage value of which by this time already coincides with the 40 average voltage value of these pulses.

Thus, the proposed code-voltage converter with pulse-width-pulse modulation allows 45 to significantly increase the conversion rate when changing the code due to the forced charge (discharge) of the DC-filter capacitors with direct current for a time Uop.i / Jj proportional to the increment the converted code ΔΝ'υ, causing the increment of the average voltage across the filter capacitors. At the same time, the degree of increase in speed determines 55 _{C the} magnitude of the charge current of the filter capacitors.

Claims (1)

The invention relates to electrical measuring technology and can be used for accurate conversion of a code to a constant voltage, and also as a fast-acting large-scale constant voltage converter in precision volt meters, voltage calibrators and analog-digital computing devices. Code-to-voltage transducers based on pulse-width modulation make it relatively easy to realize high accuracy and therefore have found wide application in measurement technology. However, their ability and application area is limited by low speed, due to the necessity of averaging a continuous sequence of pulse-width modulated pulses over many repetition periods, the required number of which increases with increasing accuracy. A code-to-voltage converter is known with an intermediate code conversion into a width of pulse-modulated pulses, comprising a register, a pulse generator, a code matching circuit counter, a trigger, and a low-pass filter. An increase in the speed of such a converter is obtained by increasing the frequency and decreasing the amplitude of the width-modulated pulses due to the multichannel implementation implemented by inserting into the circuit of the decoding resistive grid i-group of switches with formers on n channels, as well as several shifts of registers or counters with decoders 11. The disadvantage of such a converter is high complexity, which is practically proportional to the number of channels (phases), i.e. degree of increase in speed. A code-voltage converter with pulse-width modulation is known, containing a receiving register of a pulse generator connected to a counter, a matching element, a high-voltage filter whose signal input is connected via a switch to a common bus and a source of voltage, respectively, and a trigger whose input is connected corresponding to the output of the counter and the coincidence element connected by the corresponding outputs to the outputs of the receiving register and the counter. A normally grounded RC filter capacitor in a known transducer is supplied with an additional voltage close in value to the average, formed by a fast-acting digital-to-analog converter. Due to the euom, with a step change in the transformed coil, the filter capacitors are recharged by a relatively small value equal to the difference of the voltage of the additional digital-to-analog converter and the average value of the output voltage of the filter. This increases the speed of the converter, the higher the accuracy and stability of the digital-to-analog converter, the speed of which should be faster than the speed of converter 2 ,. However, a digital analog converter with such high metrological characteristics (high accuracy, stability, resolution, and speed) is a complex device, the number of bits of which is equal to or greater than the number of bits of a 1-volt code-voltage converter. Moreover, the speed of such a converter is limited even with the use of an accurate digital-to-analog converter, since as the voltage on the filter capacitors decreases, the exponential slope decreases and consequently the transient time increases. Thus, for example, the time for establishing a voltage on a capacitor with an accuracy of 1.0% is 71, .a with an accuracy of 0.0001% - - 141,. It follows that the accuracy of the digital-to-analog converter is increased by three orders of magnitude (0.1% - 0 , 0001%) increases the speed of all twice. Another factor limiting the speed of a known converter, the presence of voltage ripples on the filter capacitors, whose magnitude increases significantly as the capacitor moves away from the filter output. The high level of the variable component on the capacitors eliminates the possibility of using an accurate digital-to-analog converter to improve performance. In addition, the efficiency of the known converter increases as the filter time T decreases. However, this increases pulsation and decreases (as R decreases, the accuracy due to the effect of the final resistance of the switch in the closed state. The purpose of the invention is to improve the speed of the voltage converter. In this case, the code-voltage converter contains a receiving register, a pulse generator whose output is connected to the counter input, a coincidence element, an RC filter whose signal input is connected to the common bus and a reference voltage source through the first and second keys, respectively, and the first trigger, the inputs of which are connected respectively to the outputs of the counter and the coincidence element, to the corresponding inputs of which are below1: the outputs of the bits of the receiving register and the counter are switched on, the module forming unit and the character are entered Code computations, digital comparator, two elements And, a bipolar current source, additional keys and a second trigger, the first one, whose input is connected to the installation inputs of the counter and the receiving register and the start bus, while the inputs of the digital comparator are connected respectively to the code outputs of the counter and the unit for forming code increments, and the output with the second input of the second trigger and the installation input of the unit for generating code increments, the code inputs of which are connected to the code VI and inputs and outputs of the receiving register respectively and the sign output with the input of a bipolar current source connected to the RC capacitor through additional switches, the control inputs of which are connected to the output of the second trigger and the first input of each element And, the second inputs of which are connected to the corresponding outputs of the first trigger, and the outputs are to the control inputs of the first and second keys, respectively. The converter circuitry is illustrated in FIG. The code-voltage converter contains a receive register 1, which receives the converted code, match element 2, a counter 3 connected to the pulse generator 4, the first and second triggers 5 and 6, the code incrementing unit 7, the digital comparator 8, two logical element 9 and 10, a bipolar current source 11, keys 12, a multilink RC filter 13, periodically connected antiphase controlled keys 14 and 15 to the source of the reference voltage 16 and the common bus 17 of the converter, respectively, and capacitors 18. Nature formation unit Code 7 defines the modulus and the sign of the current increment of the code to be converted, tD N - N i.v. - N, and bipol pH (current source 11 provides a forced linear charge (with an increase in the code) or discharge (with a decrease in the code). For a time ti, proportional to the magnitude (module) of the current increment of the converted uWi code. The converter works in the following way. The digital code of the HI number stored in the receiving register 1 is compared in the matching element of codes 2 with the changing from O code, counter code 3, to the input of which pulses are continuously received from the pulse generator 4. At each transition of counter 3 through zero state A signal appears at its output, setting the trigger 5 to a certain, for example, single state. At the moments of coincidence of the number codes of register 1 and counter 3, the coincidence element 2 generates signals that return trigger 5 to the initial zero state. at the outputs of trigger 5, a continuous sequence of latitude-modulated antiphase pulses is formed whose duration is proportional to the value of the code being converted N; and the repetition period TD is determined by the capacity of the counter 3. In static mode, when the input spacing N |, + and output Nl codes of the receiving register 1 is zero (uNt 0), the trigger b is continuously held by the START signals, periodically along. stepping on its input with a clock frequency of the converter and coinciding in time with the digital comparator 8 signals arriving at its other input, the duration of which is less than the duration of the START signals. In this case, the output voltage of the trigger 6, the keys 12 are open, the elements 9 and 10 are open and the antiphase width-modulated pulses from the outputs of the trigger 5 are fed to the keys 14 and 15 connecting the RC-filter 13 to the source of the disputed voltage 16 for the pulse time 1., and to the common bus - for the time between pulses t.-T-tj, As a result, a continuous sequence of pulse-modulated pulses of -fixed am-i-band E, the average value of which is UcpU1K.C | s allocated by the HC-filter 13, proportional to the conversion ue st Nl code. g. in the dynamic mode, when the difference between the input and output codes of the receiving register 1 is not equal to zero (), the trigger b is triggered by the START signal in one state. and it returns to the initial zero state through time t iN by the digital comparator 8 signal at the time of coincidence: the codes of the numbers of the code 7 incrementing unit and counter 4. At the same time, the digital code comparator 8 erases the codecode N; stored in the code incrementing unit 7, As a result, when the value of the code being converted is changed, a pulse is formed at the output of trigger b, the duration of which is proportional to the value of the code increment N. With a continuous change of the converted code, a continuous sequence of width-modulated pulses is formed at the output of trigger b, the duration of which is proportional to; the values of the change of the converted code iNj, and the repetition frequency coincides with the repetition frequency Gf of trigger pulses. For the duration of the trigger pulse, elements AND 9 and 10 are closed by disconnecting the RC filter from the voltage source 16 and the common bus 17, and the keys 12 are locked :: sa-ots, this bipolar current source 11, the polarity of which is set the signal coming from the sign output of the code 7 increment block, charges (discharges) the capacitors 18 of the filter 13 by u, Ucp., i3 g proportional to the amount of code change, because i.-, proportional to AN-,. At the moment of termination of the trigger pulse 6, the keys 12 are disconnected, stopping charge (discharge) of the condensator 18 of the filter 13, the elements 9 and 10 are unblocked and the width-modulated pulses of the trigger 5, the duration of which is proportional to the new value of the code being converted, after normalization in amplitude, arrive at The RC filter, the average value of the voltage of which by this time already coincides with the average value of the voltage of these pulses. Thus, the proposed code-voltage converter with pulse-width modulation can significantly increase the conversion speed when the code changes due to the forced charge (discharge) of the capacitors of the RC filter by direct current during the time Uop.i / dT , / proportional to the increment of the converted code L Nt ,, causing the increment of the average value of the voltage uUcp.; on the filter capacitors. In this case, the rate of increase in speed is determined by the magnitude of the charge current L – j of the filter capacitors. DETAILED DESCRIPTION OF THE INVENTION A pulse-width modulated code-voltage converter comprising a reception register, a pulse generator. the output of which is connected to the input of the counter, the element coincides