SU788423A1 - Start-stop receiving device - Google Patents

Description

(54) START-UP ACCEPTANCE DEVICE

I

The invention relates to telegraphy and can be used in telegraph data transmission equipment.

A start-stop receiving device is known, comprising a serially connected input matching unit and a starting unit, the output of which is connected to the first input of the control unit, the second input of which is connected to the second input of the starting unit and the output of the package counter, which input is connected to the output of the first counter and the third input of the control unit , the first output of which is connected to the first input of the switching unit, the first output of the co o is connected to the first input of the controlled divider, the output of which is connected to the first input of the first a second counter, the second input of which is connected to the first input of the output matching unit and the output of the buffer register, the first input of which is connected to the second output of the control unit, the third output of which is connected to the second input of the output matching unit, and the output of the controlled generator is connected to the second input of the switching unit and the fourth output of the control unit is connected to the second input of the controlled divider 1.

However, the known device does not provide sufficient fidelity of the received information.

The purpose of the invention is to increase the loyalty reception.

To achieve this goal, second and third counters, a frequency divider and a reversing register are introduced into a known device, the second input of which is connected to the first input.

10 output of the switching unit. The third output of which is connected via a frequency divider to the first input of the second counter, to the second input of which a second output of the control unit is connected, the fifth output of which is connected to the second input of the reversing register,

15 whose output is connected to the first input of the third counter, the second input of which is connected to the third input of the control unit, the other output of which is connected to the input of the controlled generator, while

20, the output of the second counter is connected to the second input of the buffer register, and the output of the third counter is connected to the third input of the output matching unit.

The drawing shows a structural electrical circuit of the proposed device.

The start-stop receiver contains an input matching unit 1, a starting unit 2, a control unit 3, a controlled generator 4, a switching unit 5, a reversing register 6, a first counter 7, a frequency divider 8, a controlled divider 9, a second counter 10, a buffer register 11 , the third counter 12, the output matching unit 13 and the counter 14 parcels.

The device works as follows.

The code combination comes from the communication line (not shown in the drawing) and is transformed by the input matching unit 1 into a sequence of signals "1 and" O corresponding to the current and current parcels.

The starting pulse puts the starting unit 2 into working condition, which, in turn, sets unit 3 to the receiving mode of the code combination. At the same time, at the command of block 3, the controlled oscillator 4 generates pulses (with a frequency f at least an order of magnitude higher than the wiring frequency), received through block 5 and divider 8 at the first input of the second counter 10. Divider 8 divides the following frequency pulses by fifteen. Thus, by the end of the code combination, whose duration is equal to T, n pulses go to the second counter 10, where

  5 Since the duration of the g information and starting parcels in the code MTC number 2 is equal to

T | T,

that

P JL.f.lSr jc.f

 15 g g I

i.e. at the time of receiving the code parcel in

the second counter 10 receives the number of pulses corresponding to half the duration of the information code parcel. At the same time, the signal from the output of the starting block 2 through block 3 is fed to the second input of the reversing register b, the first input of which through block 5 receives a sequence of pulses from the controlled generator 4. The capacity N of the reversing register 6 is equal to

N,

where T is the maximum possible duration of the code combination.

During the time of action of the current parcel, the reversing register 6 records m signals "b" and shifts by ttt bits, while for the current time of the current parcel, writing to the reversing register b does not occur, but shifts by m bits. Wherein

m T-f 2 p.

Thus, by the end of the reception of the code combination in the reverse register 6, the received code combination is recorded in

as a sequence of groups of signals “O and“ 1, and in the second counter 10 - the number of pulses, corresponding to half the duration of the information code parcel -. Block 3 performs stop selection.

the parcel and at the moment of its termination puts the device in the decoding mode of the received code combination. The process of deciphering consists in the fact that the information recorded in the reverse register b is divided into thirteen groups, proportional to 5 (stop message and information again). To isolate the stop parcel from the reverse register 6 to the third counter 12, the first three groups of information are read, and to separate the information parcels, the subsequent groups of two. If in the read information package consisting of two groups, the number of units is greater, it is taken to be "1, otherwise it is equal to" O.

Recording and decoding of the starting package is not performed. The decryption process of the previous code pattern is performed while receiving the starting burst of the subsequent code pattern. In this case, block 3 generates a command, according to which the controlled generator 4 begins to generate a sequence of pulses with a frequency f, and

.

This condition must be met in order for the decipherment of the received codeword to end before the start of the subsequent code pattern is completed.

At the same time, at the command of unit 3, the reversible register B is transferred to reversible mode of operation, in which information is read from it in reverse order of writing. In this case, first, the number of i mpiles is read, proportional to the duration of the stop parcel, equal to

Q because it is recorded last. The code of the number n from the second counter 10 is rewritten in the forward code to the buffer register 11 and in the reverse code to the first counter 7, after which the second counter 10 is reset. Next, the pulses of the controlled oscillator 4 with a frequency ft through block 5 are fed to the first input of the reversing register b and the information is overwritten in the order written back to the third counter 12. At the same time, the pulses with the frequency

f fi arrive at the first input of the controlled divider 9.

The division ratio of the controlled divider 9 is initially three. Therefore, the overflow of the first counter 7 occurs after the arrival at the first input of the register register 6 and the controlled divider 9 Зп pulses

Sn | --T-f,

where T is the duration of the stop package; i.e., the overflow of the first counter 7 occurs when the third counter 12, the number of pulses corresponding to the duration of the stop burst, arrives at the input of the third counter 12.

The overflow pulse through unit 3 enters the output matching unit 13, where the code of the number of pulses received by the third counter 12 and the code of the number n corresponding to half the duration of the information code parcel are simultaneously transmitted. The output matching unit 13 compares the incoming codes of numbers and, if the number received from the output of the third counter 12 is greater than the number received from the output of the buffer register 11, then the code parcel is assumed to be "1, i.e., current, otherwise “Oh, that is, non-current.

Then the third counter 12 is reset, and in the first counter 7 of the buffer register 11 again rewrites the inverse code of the number n, block 3 sets the division factor of the controlled divider 9 equal to two and the whole process repeats for the first and subsequent code packets. The first counter 7 overflows now with the arrival at the first input of the controlled divider 9 and the first input of the reversing register 6 of the number of pulses equal to 2 n, i.e. the corresponding duration of the information code parcel. Counter 14 counts the number of overflows of the first counter 7 and, after the arrival of the sixth pulse, outputs to the second input of block 3 a signal terminating the deciphering process of the received code combination.

After receiving the last code message, the starting block 2 is reset to the initial position, and also all nodes containing triggers.

In the event that immediately after one code combination follows another, the process of decoding the received code combination occurs simultaneously. At the same time, two sequences of pulses arrive simultaneously from the controlled generator 4 — with a frequency f (through block 5 and through divider 8 to the second counter 10 — to receive the next combination) and with a frequency f 1 (through block 5 to the reverse register 6 and divider 9 - to clear the received code combination). At the time of deciphering the received code combination, the second input of the reversing register 6 is blocked and will be unlocked by the decipher termination signal coming from counter 14 through block 3.

The starting parcel is not deciphered (the six code packets received last are deciphered) and is always a non-current parcel. However, the fact that the recording of this parcel is not made from the moment it starts, does not reduce the accuracy of reception, but only serves to start the device.

The proposed device makes it possible to increase the fidelity of receiving telegraph signals and stably operates under the conditions of crushing and boundary distortions of code messages acting separately or simultaneously.

Claims (1)

Invention Formula Start-stop receiver, containing in series an input matching unit and a starting unit, 5 whose output is connected to the first input of the control unit, the second input of which is connected to the second input of the starting unit and the output of the package counter, the input of which is connected to the output of the first counter and the third input of the control unit, the first 0 whose output is connected to the first input of the switching unit, the first output of which is connected to the first input of the controlled divider, the output of which is connected to the first input of the first counter, the second input of which is connected to the first input of the output matching unit and the output of the buffer register, the first input of which is connected to the second output of the control unit, the third output of which is connected to the second input of the output matching unit, and the output of the controlled oscillator is connected to the second input of the switching unit, and the fourth output of the control unit The control is connected to a second input of a controlled divider, characterized in that, in order to improve the reception accuracy, second and third counters, a frequency divider and a reversing register are introduced, to the first input of which a second output of the switching unit is connected, the third output of which is connected through a frequency divider with the first input of the second counter, to the second input of which the second output of the control unit is connected, the fifth output of which is connected to the second input of the reversing register, the output of which is connected to the first input of the third The second input is connected to the third input of the control unit, the sixth output of which is connected to the input of the controlled generator, the output of the second counter is connected to the second input of the buffer register, and the output of the third counter is connected to the third input of the output matching unit. Sources of information taken into account during the examination 1. V. Ye. Bukhviner. Discrete circuits in radio communication phase systems. M., “Link, 1969, p. 58-66 (prototype).