SU769608A1 - Device for magnetic recording of digital information onto disks - Google Patents

Description

density of magnetic recording of digital information on disks.

The goal is achieved by the introduction of a control unit for the generation of delayed sync series, the input of which is connected to the input of the track address, and the outputs to the additional inputs of a controlled circuit for generating delayed sync series.

FIG. 1 shows a block diagram of the device; in fig. 2 - time diagrams of his work.

The circuit contains (see Fig. 1) the input 1 of the pulse information sequence, the output 2 of the clock pulses and the input 3 of the circuit setup into the initial state, connected to the shift register 4, the decoder 5, the delayed clock generation circuit 6, the switch 7, the recording amplifier 8, block 9 of the control of the generation of delayed sync series and the input 10 of the track address. The outputs of the shift register 4 are connected to the inputs of the decoder 5. The input 2 of the clock pulses is also connected to the input of the circuit 6. The outputs of the decoder 5 are connected to the control inputs of the switch 7. The central output of the shift register is connected to the information input of the switch 7. The input of the block 9 is connected to the address input of the track 10, and the outputs to the additional inputs of the generation of delayed sync series. The outputs of the circuit 6 are connected to the corresponding inputs of the switch 7. To the output of the switch 7 is connected to the recording amplifier 8.

The device works as follows.

After power is applied to input 3, a pulse is applied, bringing the shift register 4 to zero and thus the entire circuit to the initial state. After that, the input of the shift register 4 is supplied with the pulse sequence of information A, and the input of the sync pulse B (see Fig. 2). Using the sync pulses B, the pulse sequence of information A in shift register 4 is shifted. The state of register 4 (C, D, D, E, G, 3) is analyzed by the decoder 5 in each step, and, depending on the content of the combination, The pulses I, K, and L. control the operation of the switch 7 are generated. From the central output E of the shift register, the pulse sequence of information, except for the input of the decipheror 5, is fed to the information input of the switch 7. The clock pulses B from input 2 are also fed to the input of the output circuit rye sync series 6, which of them produces three detainees by the amount A, one relative to another of the M, H and P synchroseries. The magnitude of the time delay A determines the magnitude of the introduced predistortion. Depending on the presence at the control inputs of the switch 7 impulses I, or K, or L, the information pulse sequence of information pulses received at the information input of the switch 7 by the pulses of the sync series M, or H, or P, respectively, is gated. The magnitude of the input reductions, depending on the magnitude of the time delay A, is set by the control unit 9. The gateway address, which determines its radius, from input 10 enters the receiving register 11

(Fig. 1) of the control unit 9, where it is converted by the descrambler 12 into signals that control the amount of time delay of the clock pulses in the circuit. As a result, the original pulse sequence

information A is converted into the sequence S, which from the output of the switch 7 is fed to the recording amplifier 8.

Pa figs. Figure 2 shows an example of introducing predistortion in the information code sequence 1100111, encoded using the modified phase modulation method. At the same time, the time intervals T of the initial pulse sequence are reduced, and the intervals of 1.5 T are increased by the value D.

Pa figs. 1 shows an embodiment of the control unit 9, issuing three values of the control signal Fi (R), P2 (K) and Pz (K) and a scheme for generating delayed sychroseries 6, specifying respectively three values of the time delay A. Sync pulses B are fed to the input of the delay line 13, which has seven exits. From the central output of the delay line, the synchroser H is removed. From the remaining outputs of the delay line, 13 clock pulses arrive at the first inputs of the corresponding coincidence circuits 14-19. The second inputs of the matching circuits are connected to the corresponding

the outputs of the decoder 12. The outputs of the matching circuits 14, 15 and 16 are connected to the inputs of the OR circuit 20, and the outputs of the matching circuits 17, 18 and 19 to the inputs of the circuit OR 21. Depending on the presence of control signals Fi (R), FziR) or F3 (R) opens the possibility of passing the sync signals to the input of circuits 20 and 21 from the corresponding outputs of the delay delay 13. Thus, three delayed one relative to the other sync series M, P and P are generated, the delay A being determined by the control signals Fi (R), F2 (R), FsiR), which in turn are proportional to the radius of the road ki K

Claims (2)

where the recording is made. The number of control signal values is selected in order to achieve the required accuracy and complexity of the circuit. Other design options are possible. Thus, for example, a delay line in the generation of delayed sync series can be made electrically controlled by an analog signal from a track address code converter. The circuit as a result of introducing a control unit and executing a controllable delayed synchronicity circuit allows changing the value of input pre-distortions into the recorded signal depending on the track radius, recording-reproduction channel parameters and thereby increasing the density of magnetic recording of digital information on the discs. The invention is a device for magnetic recording of digital information on disks containing a shift register with an input of a pulse information sequence, a clock input and a circuit setup input, a decoder, inputs connected to the outputs of the shift register, a switch, control inputs connected to the outputs of the decoder, and the information input to the central output of the shift register, the generation scheme of the delayed sync series, the input of which is connected to the input of the clock pulses, and the outputs to the corresponding To the inputs of the switch, a recording amplifier connected to the switch input, characterized in that, in order to increase the recording density, a block of control of the output of synchronous serial circuits, the input of which is connected to the track address input, is entered into it, and the outputs are connected to the additional inputs of the controlled circuit generation of delayed synchronicities. Sources of information taken into account in the examination 1. Sukolsky V. Yu. Corrector of temporal distortions for a device for magnetic recording of digital information. Sat news of the Leningrad Order of Lenin Electrotechnical Institute. V.I. Ul Nova (Lenin) Vol. 165, Leningrad, 1975. 2. US patent number 3879342, cl. 360-45, published. 1975 (prototype). Wt , V t1 G: -. .; / o- ... / "4   -7, 4Y.) |,. ,, f. 769608 "