SU758546A2 - Clock pulse generator - Google Patents

Description

(54) DEVICE FOR GENERATING CLUTCH

PULSES

one

The invention relates to devices for the transmission of discrete information and can be used as a synchronization device in the systems for receiving and transmitting discrete code packets.

According to the main author. St. No. 472470, a device for generating clock pulses is known, comprising a master oscillator, the output of which is connected via an AND element to the counter input of a counter with an adder in a feedback circuit, a trigger, the first OR element whose output is an output of the device, and the input is connected to the counter output directly and through a time relay to the inputs of two elements And, the second inputs of which are connected to the input of the device, and the output of the first of the two elements AND is connected to one of the inputs of the first and second elements OR and to one and from the counter inputs, and the output of the second element AND to the input of the second element OR, the output of which is connected to another input of the counter directly and to the third input through the delay line C13.

However, this device has low noise immunity, due to the fact that the impulse noise appearing on

the device input, at random times, can be freely passed to the device output, while simultaneously changing the code in the counter throughout the whole follow-up period of the input signals, except for the part during which the input pulse is checked by the end of the current period. The occurrence of such a laughter may cause a violation of the established synchronism in the operation of the transmission and reception system.

The purpose of the invention is to increase the noise immunity of the device.

This is achieved in that a device for generating clock pulses containing a counter, three AND elements, an adder, two OR elements, a delay line,

15 master oscillator and trigger, an additional trigger is inputted, the output of the second element I and the additional output of the counter are connected to the unit and zero inputs, respectively, and the inverse output 20 of the trigger is connected to the additional input of the element I.

The drawing shows a structural electrical circuit of a device for generating clock pulses.

The device contains a counter 1, the first element And 2, the adder 3, the relay 4 time, the second and third elements And 5 and 6, the first and second elements OR 7 and 8, the delay line 9, the master oscillator 10, the trigger 11 and the additional trigger 12 .

The device works as follows. The first input pulse switches the trigger 11, which opens the third element AND 6. The pulses from the master oscillator 10 begin to fill the counter 1, whose capacitance corresponds to the number of pulses of the generator during the average period of the input signal. Upon filling the counter to p-1 (n is the total capacity of the counter), an additional output appears at its additional output, confirming the zero state of the additional trigger 12, which was set when the device was turned on with a general reset pulse. After the input of the counter of the 1 nth pulse from the master oscillator 10, the pulse at the first output of the counter 1 appears at the time relay 4 and through the OR element 8 at the output of the device. Using a pulse from time relay 4, it is checked whether the second input pulse belongs to a given period or not. One of the outputs of time relay 4 is connected to the second element 5 and the other output corresponding to the inverted signal to the first element 2. If the second input pulse corresponds to the end of the current period, which is a sign of the reception and reception system to synchronize, then passes through the second element And 5 and enters the input of the element OR 7, the output of which is connected to the inputs of the counter 1 directly and through the delay line 9. In addition, the pulse from the output of the second element And 5 is fed to the single input of the additional trigger 12, switching the last and blocking the first element And 2 on the third input. This blocking is retained until the next pulse appears at the additional output of the counter 1, which again switches the additional trigger 12 to the zero state.

Thus, after the appearance of the second input pulse, the counter 1 sets the code corresponding to the negative value of the period deviation of the input signal, and in the adder 3 this deviation is memorized. If the third input pulse arrives at the device input earlier than through (n-1) -K pulses of the master oscillator 10 (n is the total capacity of the counter 1, K is the number of pulses corresponding to the code stored in adder 3), counted from the moment of arrival the second pulse, it is perceived as an obstacle and the output of the first element I 2 does not pass through the cyt, since the additional trigger 12 during this time interval blocks it by the third input. At the output of the first element I 2, and consequently, only the input signal passes through the input of counter 1 in synchronization mode, which is ahead of the pulse generated by the device for no more than one period of the master oscillator 10, so that the code in the adder 3 during the next auto-tuning the device changes no more than per unit V the accumulator 3 accumulates the sum of the deviations of the period of the signal produced by the device from the average value of the period of the input pulse sequence, which is the initial state of the counter 1 When counting the number of pulses of the reference generator 10 for every repetition period of the current input signals. In the event of a single input signal falling out, the current output pulse is generated in accordance with the code stored in adder 3, and with further fallout, the clock pulses are output according to the average frequency of the input signal, defined by my capacitance of counter 1, since the code from adder 3 to counter 1 is not transmitted. The first element And 2 remains open at the third input, since the additional trigger 12 is in the zero state.

In those cases, when the input signals, starting from the second, advance the output pulses of the counter, they pass the open first element I 2, change the code of counter 1 to an additional one and arrive at the output of the device. In this way, the device is adjusted to reduce the period of the input signals. In this case, the first element And 2 remains permanently unlocked at the third input until the synchronization mode of the receiving-transmitting system occurs, which is detected by the appearance of a pulse at the output of the second element 5. At this moment, the first element 2 will block each output pulse of the second element And 5 for the time, which constitutes the greater part of the period of the input signals and is numerically equal (n-1) to the pulses of the master oscillator 10, where n is the total capacity of the counter; K - the number of pulses of the master oscillator 10, corresponding to the current code value in the adder 3.

In this case, the value of the relative frequency instability of the transmitter and receiver master oscillators (S) must satisfy the condition

2NS | 1 |,

where N is the number of pulses of the master oscillator 10, corresponding to the steady-state following of the input signals, maximum equal to p.

Thus, the introduction into the device of an additional trigger 12, realizing

Claims (1)

Claim A device for generating clock pulses auth. St. No. 472470, characterized in that, in order to increase the noise immunity, an additional trigger is introduced, to the unit and zero inputs of which the output of the second element I and the additional output of the counter are connected, and the inverse output of the trigger is connected to the additional input of the first element I.