SU721903A1 - Staircase-sawtooth current generator - Google Patents

Description

one

The invention relates to a pulse technique and can be used in communication devices.

A step-shaped current generator is known that contains a digital-to-analog converter made according to the weight currents addition circuit, a voltage regulator on a transistor with a voltage source, consisting of a zener diode and a resistor connected in series with a deflecting coil and a variable resistor, the middle output of which is connected the output of the D / A converter, an additional voltage regulator at the transistor, the base of which is connected to the Zener diode of the voltage source, and the emitter with Connected to the second output of the variable resistor 1.

The drawbacks of the device are the lack of current distortion correction in it and low reliability.

The closest technical solution to the invention is a step-sawtooth current generator comprising a clock pulse generator, the output of which is connected to the input of the first counter.

pulses, the second pulse counter, the outputs of which are connected to the input of the current amplifier connected to the diverting system 2.

The disadvantage of this device is its low reliability.

The aim of the invention is to increase the reliability of the device.

The goal is achieved by the fact that the current generator is a step-sawtooth shape, which contains a clock pulse generator whose output is connected to the input of the first pulse counter, a second pulse counter whose outputs are connected to the inputs of the current amplifier connected to the deflecting system, and NOT items NOT. Moreover, the first direct outputs of the first counter are connected to the inputs of the first AND-NOT element, the reverse outputs of the first counter are connected to the inputs of the second AND-NOT element, the outputs of these elements are connected to the inputs of the third AND-NOT element, the output of which is NOT connected to the first element the input of the fourth element AND NOT, the second input of the latter is connected to the output of the generator

clock pulses and with the input of the second element NOT, the output of which is connected to the first input of the fifth element NAND, the second input of the sixth element connected to the output NI, whose inputs are connected to the second group of direct outputs of the first pulse counter. The output of the fifth element AND-NOT is connected to the first input of the seventh element AND-NOT, the second input of which is connected to the output of the third element AND-NOT, and the output to the first input of the eighth element AND-NOT, the second input connected to the output of the fourth element AND-NOT, and the output through the third element NOT to the input of the second pulse counter, the control input of which is connected to the control input of the first pulse counter and connected to the bus with: a high signal.

The drawing shows a structural electrical block diagram of the device.

The device contains a generator of 1 clock pulses, counters 2 and 3 pulses, current amplifier 4, a deflecting system 5, elements AND-NO 6, 7, 8, element NOT 9, element AND-NOT 10, element 11, elements AND-NOT 12-15, the element is NOT 16.

The current generator step-sawtooth form works as follows.

The clock pulse generator 1 generates clock pulses that are applied to the counting input of counter 2. In the initial state, when the control inputs of counter 2 have a low-voltage sync pulse corresponding to the level "zero (inhibit signal), the counter 2 is zeroed, and the clock pulses the generator 1 does not pass through the counter 2, the outputs of this counter are constant, the clock pulses into the counter 3 are not tapped, therefore there is no current at the output of the current amplifier 4 and in the deflecting system 5.

With the arrival at the control inputs of the counter 2 high-level clock corresponding to the level one (the enabling signal), this counter passes the clock pulses of the generator 1, counts and divides them bitwise, forming a parallel binary code on the forward and reverse outputs. In this case, a voltage pulse is applied to the NE-6 element, for example, from the direct outputs of counter 2, forming the first voltage pulse of the correction section at the output of this element. The duration of this pulse depends on the number of connected direct outputs of the first counter (practically the number of connected outputs can be two). At the same time, voltage pulses from the reverse outputs of counter 2 are applied to the NAND element 7. At the same time, at the output of the NAND 7 element, a second voltage pulse is produced from the correction section. The duration of this pulse also depends on the number of connected reverse outputs of counter 2 (almost the number of connected outputs can be two). Next, both pulses from the outputs of the elements AND-NOT 6 and 7 are served

to the inputs of the NAND element 8. In it, these pulses are combined and at its output voltage pulses of the adjustment sections are formed. From the output of the NAND 8 element, voltage pulses of the correction sections are fed to the input of the element NO 9,

they are inverted in it and then fed to the first input of the NAND element 10. At the same time, the voltage of the clock pulse generator 1 is applied to its second input. At the output of the NE-10 element, voltage pulses are generated, which are a sequence of clock pulses from the generator 1 and are the sequential code of the uncorrectable region.

0 At the same time, the voltage pulses from the forward outputs of counter 2 are fed to the inputs of the NAND element 3. The output of this element produces inverted correction code pulses. The duration of each of these pulses is usually chosen three times the pulse of the clock pulse generator, and their number depends on the number of connected direct outputs of counter 2. From the output of the NAND 13 element, the inverted pulses of the correction code are fed to the input of the NAND 12. At the second input of this element through the element 11 is fed inverted voltage pulses of the generator 1 clock pulses. At the output of the element AND NOT 12, a sequence of pulses is formed.

 These voltage pulses are applied to the first input of the AND-HE element 4, to the second input of which voltage pulses of the adjustment sections are applied. At the output of this element, a pulse sequence is formed, the extreme parts of which, according to the average, are filled with correction pulses and clock pulses of generator 1 and constitute the sequential code of the correction sections. The voltage pulses of the sequential code of the uncorrectable area from the output of the element AND-NOT 10 and the voltage pulses of the serial code of the sections of correction from the output of the element AND-HE 14 are simultaneously supplied to the inputs of the element 15 and are combined in it. At the output of the NE-15 element, a pulse sequence of an inverted full sequential code is formed. The sequence of pulses of this code from the output of the IS-15 element is fed to the input of the HE element 16, inverted in it, and then fed to the counting input of counter 3. This group of pulses is a sequence of the input code of counter 3. Simultaneously

Claims (1)

Claim A step-sawtooth current generator containing a clock pulse generator, the output of which is connected to the input of the first pulse counter, a second pulse counter, the outputs of which are connected to the inputs of the current amplifier connected to the deflecting system, characterized in that, in order to increase the reliability of the generator, AND-NOT elements and NOT elements are introduced into it, and the first direct outputs of the first pulse counter are connected to the inputs of the first AND-NOT element. the reverse outputs of the first counter are connected to the inputs of the second AND — NOT element, the outputs of these elements are connected to the inputs of the third AND — NOT element, the output of which through the first element is NOT connected to the ₁₀ first input of the fourth AND — NOT element, the second input of which is connected to the output of the clock pulses and a second input of NOT circuit whose output is connected to the first input of the fifth aND-NO element, whose second input ¹⁵ is connected to the output of the sixth aND-NO element, whose inputs are connected to the second group of direct output of the first counter pulses, and the output of the fifth AND-NO element is connected to the first input of the seventh AND-NO element ₂₀ whose second input is connected to the output of third AND-NO, and the output - to the first input of the eighth AND-NO element, a second input connected to the output of the fourth element AND — NOT, and the output through the third element NOT — with the input of the second 25 pulse counter, the control input of which is connected to the control input of the first pulse counter and connected to the clock bus.