SU684764A1 - Start-stop transceiver - Google Patents

Description

The invention relates to telecommunications and can be used in discrete information transmission systems.

A start-stop receiving device is known, which contains an input unit, a dinat, a shift register, elements, and an advance pulse generator 1.

However, the known device has a low reliability of receiving information.

Also known is the start / stop transceiver, which contains a shift register, the outputs of which are connected to the inputs of the first I.11I element, the output of which is connected to the input of the clock frequency generator and the first input of the second OR element, to the second input of which the output of the high register of the shift register 2 is connected,

This transceiver has insufficient noise immunity.

The purpose of the invention is to improve noise immunity.

To do this, in the start-stop transceiver, the content of the shift register, the outputs of which are connected to the inputs of the first element I.LI.

the output of which is connected to the input of the clock generator and the first input of the second element OR, to the second input of which the output of the higher bit of the shift register is connected, introducing two elements 2И-OR, two elements И and a trigger, the first output of which is connected to the first inputs of elements 2И- ILV, the third input of the second element OR, and the first input of the first element And, the second and third inputs of which are connected to the corresponding outputs of the shift register and the first inputs of the second element And, to the second inputs of which the output of the first is connected And, while the output of the first element 2 AND-OR is connected to the setup input of the shift register, to the dynamic input of which is connected the output of the second element 2I-OR, the second input of which is connected to the second output of the trigger, the first input is connected to the corresponding inputs of the shift register and the first element OR, the output of which is connected to the second inputs of the tr of the iterator and the first element 2I-OR, the third input of the goch () X1go is connected to the second input of the second element OR, 36 and the output of the clock frequency generator is connected to the corresponding the inputs of the second element 2I-OR. The drawing shows a structural electrical circuit of the proposed transceiver. The transceiver contains an oscillator 1 of the following frequency, shift register 2, elements OR 3, elements AND 5, 6, elements 2И-OR 7, 8 and trigger 9, input 10 of the shift register 2. The transceiver operates as follows, 1. Transmission mode. At the initial moment the shift register 2 and the trigger 9 are in the state O. From the pr Mbi i outputs of the shift register 2, the low potentials arrive at the OR 4 element, at the output of the OR element, which confirms the zero state of the trigger 9 and the shift register 2. At After the parallel code from the dialer (not shown) to the parallel inputs of the shift register 2, a gate arrives at the input 10 of this register, which through the write control input of the shift register 2 allows writing the parallel code to the shift register 2, simultaneously unlocking and even the square element OR 4 shift register 2, and the gate, having entered the inverse shift register 2, will write O - START to the highest position and 1 - STOP to the younger order. shift register 2. The unit, having driven out at the output of the element OR 4, will block the dial block (not shown) and start the 1 clock frequency generator, and since the trigger 9 is in the O state, the clock frequency does not enter , from the output of element 2I-OR 8 enters the dynamic input of shift register 2. As the clock frequency arrives at the shift register. The 2 information recorded in the latter will be shifted and through the OR element 3 to the transmission channel, and in the released bits of the shift register 2 O will be recorded, which is explained by connecting the receive channel to the inverse serial input of the shift register 2, as at the other end the transmitter is in contact with silence. At the moment when in all bits of the shift register 2 zapiszts zeros (information transmitted), at the output of the element OR 4 on the clock O, which will block the generator 1 clock frequency and shift register 2 and unlocks the dial block. When reaching the inputs of shift register 2 of the subsequent code, the cycle will be repeated. 2. Reception mode. At the initial moment, the shift register 2 and the trigger 9 are in the O state. At the output of the OR 4 element, there is a low potential, which, arriving at the O input of the shift register 2 and the O input of the trigger 9, confirms the state of the latter. When a START (low potential) arrives from the channel, a high potential appears at the output of the element OR 4 at the output of the latter, which unlocks shift register 2, trigger 9 and starts the 1 clock frequency generator. The same potential, arriving at the input of the installation O of the trigger 9, sets the latter to state 1, the trigger in turn unlocks element 2I-OR 8 and the shift register 2 will be inverse to the generator 1 clock frequency. Inversion in this case is necessary in order not to introduce a special node, to generate gating pulses for gating to receive parcels in the center. Since the duty cycle of the generated frequency is 2, and the period is equal to the duration of the parcel, the difference from 1 to p in the case of an inverse clock frequency will occur in the center of the message. Learning that the dynamic input of shift register 2 is inverse, it is possible to make a view that the parcel registration will be RO at the moment the receiving center receives the NIC. Thus, coming from the receive channel, the information through the inverse serial input of shift register 2 will be written to the last inversely. At the moment when the starting package is recorded in the penultimate digit in register 2, the received code combination will be recorded without a stop sending. At the output of the element 5, it turns out 1, which is determined by the single states of the trigger 9, the direct output of the penultimate discharge and the inverse output of the higher bit of the shift register 2. T from the output of the element 5 unlocks the element 6, and to the receiver or another registration device will receive a received combination. At the moment of recording the stop parcel, the starting parcel will go to the high bit of shift register 2. At the output of the AND-OR 7 element, it is in 1, which, arriving at the input of the O switch of the shift register 2, sets the latter to its initial state. On the left, the output of element 2I-OR 7 1 is due to the arrival at its inputs of high potentials from the higher bit of shift register 2 and from the single output of trigger 9. After setting the shift register 2 to the initial state (state O) at output f element OR 4 appears low potential.