SU674220A1 - Self-checking scaling device - Google Patents

Description

The invention relates to computing tech- nnke can be used to monitor the correct functioning of the nodes of computing devices.

A counting device is known that contains a binary counter on triggers, a parity trigger, and a convolution element 1.

The disadvantages of this device are limited functionality.

The closest to-the invention is a control enumeration device containing a binary counter on triggers, a convolution element, a parity trigger, two AND elements, an OR element and a half-adder whose output is connected to the device output, and the inputs are connected to a convolution element , the inputs of which are connected to the single outputs of the binary counter triggers, the zero output of the first trigger of the double counter is connected to the main input of the OR element, the additional inputs of which are connected to the element outputs And, the auxiliary inputs of each AND gate connected to outputs of even single trigger preceding odd flip-flop, the zero output of which is connected to the main input of the AND 2J.

The disadvantage of this device is limited functional capabilities, since the control of the counter is performed only if all its triggers are previously set to the zero state before the counter starts working.

The purpose of the invention is to expand the functionality.

The goal is achieved in that in a control counting device containing a binary counter on triggers, a convolution element, a parity trigger, two AND elements, an OR element, and a half adder, whose output is connected to the device output, and the inputs are connected to the parity trigger and element outputs convolutions, the inputs of which are connected to the single outputs of the binary counter triggers, the zero output of the first trigger of the binary counter is connected to the main input of the element OR, whose additional inputs are connected to the outputs of the elements And, the auxiliary inputs of each element And are connected to the single outputs of even triggers preceding the odd trigger, the zero output of which is connected to the main input of this AND element, additionally introduced two IS-NOT elements and an additional half-adder, the inputs of which are connected to the outputs of the convolution element and the element OR, U, the output of the additional half-adder is connected to the first input of the first NAND element, the second input of which is connected to the input of the binary Counter and the first input of the second element (That AND NONE, the second input coupled to an output of first AND-NO element and to the input for setting the parity latch whose reset input connected to the output of second AND-NO. The structural scheme of the proposed device is shown in the drawing. Recount control device contains a binary counter 1 on the trigger 2, the element of convolution 3 ,. a parity trigger 4, two elements C 5, an element OR 6, a half-adder 7, two elements NANDA 8 and 9 and an additional neiniycyMiSSafbp 10. The output of the half-adder 7 is connected to the device output 11, and the inputs are connected to the outputs of the parity trigger 4 and convolution element 3, the inputs of which are connected to the unit outputs of triggers 2 of binary counter 1. The zero output of the first trigger of binary counter 1 is connected to the main input of the element OR 6, the additional inputs of which are connected to the outputs of the elements AND 5. Auxiliary inputs. each element 5 is connected to single outputs of even triggers preceding not even ipmrepy, the zero output of which is connected to the main input of this element AND 5. The inputs of the additional half summator 10 soy denyeng with the outputs of the convolution element 3 n of the element OR 6, and the output of the additional half hem of the mother 10 A connection to the first input of the first element IS-HE 8, the second input of which is connected to the input 12 of the binary counter 1 and the first input of the second element AND-NOT 9, the second input of which is connected to the output of the first element IS-NOT 8 and the input and a parity trigger. 4, the reset input of which is connected to the output of the second element AND-NOT 9. The elements OR. And AND are used to predict the change of the parity of the binary counter code after adding the next counting unit in accordance with the following formula: p46 ... (n-1), if n odd; Р-Н23% 245 + 2467 + 1246.,. (tvH), if n is even, whereP is a FUNCTION of parity change, 1, 2.3... n - designations of the first, second, etc. triggers of a binary counter. The function of changing parity P is equal to I, if after adding the next unit the parity

Claims (2)

674220, the binary counter code changes, and is equal to O otherwise. Thus, the parity change function P allows you to predict by the code of a binary counter how the parity of this code will change after adding one more unit.1. The principle ;, the operation of the proposed device is that it is not the parity change that is predicted, but the parity value of the binary counter code itself. The table shows the values of the counter codes and the corresponding codes at the outputs of elements 6, D 10. As can be seen from this table, the output of the additional half-adder 10, whose inputs are the outputs of the elements OR 6. and convolution element 3, in each cycle of summation with the unit a code is generated whose values are the parity of the counter code after the addition of the next unit (i.e., the parity of the counter code is predicted). The device operates as follows. After the next pulse arrives, a code appears at the output of the binary counter 1 at the output of the OR element, predicting a change in the parity of the code after adding the next one (the code in the D military counter changes according to the specified edge of the counting pulse). The output of the convolution element is the code corresponding to the parity of the binary counter code in the loop. These codes are fed to the input of the additional half adder 10, and at its output a code is generated that corresponds to the parity code of the binary counter in the next cycle. When the next pulse arrives (at its leading edge), the NAND elements are triggered. If at the output of the additional half-adder code 1 is generated (i.e., a unit is predicted), then at the output of the element AND-NE 8 the potential of the logical O is reached, and at the output of the element of the AND-NO 9 - the logical 1 and the parity 4 will be set to a single state ( the parity trigger 4 is triggered by a logical O on one of the inputs). If an O code is generated at the output of the additional half-adder 10 (zero is predicted), then the parity trigger 4 is set to the zero state. In a way, parity 4 remembers the parity value that corresponds to the parity of the counter code in the next cycle. This value is compared with the value of the convolution element code 3 at the half adder 7, the presence of potential 1 at the output (which indicates that the codes are not compared at the appropriate time after the transient processes in the counter) indicates a counter malfunction. The proposed device favorably differs from the known one, since it allows controlling the counter from any initial state, i.e. such device does not require pre-setting the counter triggers to zero. The need for such a control arises practically in any counter, since it is very often necessary to first write some code into the counter, and then add this code to the unit. It should be noted that the proposed (the device is practically not complicated in comparison with the known one; because instead of a counting parity trigger, a simpler trigger with separate inputs is used. The counting control device can be widely used in the equipment of the control of digital amplifiers. Application device will allow to expand the functionality of the control. Formula of the invention A scaling device with a control that contains a binary counter on the trigger, a convolution element, a trigger two elements AND, an OR element and a half-adder, the output of which is connected to the output of the device, and the inputs are connected to the outputs of the parity trigger and the convolution element, the inputs of which are connected to the single outputs of the triggers of the binary counter, zero output of the first three: the binary counter is connected to the main the input of the OR element, the additional inputs of which are connected to the outputs of the AND elements, the auxiliary inputs of each element AND are connected to the single outputs of even triggers preceding the odd trigger, zero output which is connected to the main input of this element AND, characterized in that, in order to expand the functional possibilities, it has additionally introduced two AND-NOT elements and an additional semi-adder, whose inputs are connected to the outputs of the convolution element and the OR element, and the output of the additional semi-adder with the first input of the first NAND element, the second input of which is connected to the input of the binary counter and the first input of the second AND element - NOT, the second input of which is connected to the output of the first AND NONE element and the installation input t iggera parity whose reset input connected to the output of second AND-NO. Sources of information taken into account during the examination 1. USSR author's certificate No. 281903, cl. G06F 11/10, 1970. 2.F. Sellers; Methods for detecting errors in operation. ECM, M., Mir, 1972, p. 201-203, fig. 11.2.