SU669361A1 - Arrangement for determining random process harmonic mean value - Google Patents

Description

The invention relates to computing technology, specialized devices dp for determining the statistical characteristics of random processes, and is intended for dp determining the average harmonic value for a limited number of limited time intervals.

Devices are known that define various types of average values, for example, the arithmetic average 11.

It is also known a device that allows determining the average harmonic value of a random process 2. This device contains the first and second triggers, the input signal counter, the first and second time selectors, the result counter, the counting input of which is connected to the output of the first time selector, the first input of which is connected to the single output of the first trigger, and the second input is connected to the output of the pulse generator, a single input of the second trigger is connected to the input of the device

WA and to the first input of the second temporary selector 1, the second input of which is connected to the single output of the second trigger, and the output is connected to the counting input of the counter of input signals. The device has limited functionality, it does not allow, in particular, to determine the average harmonic value of the intervals of the pulse sequence.

The purpose of the invention is to expand the functionality of the device.

To do this, a decoder, commers parator, ingegrator, first and second elements OR, third time selector, GT blocks of pulse interval analysis, element I, dividing unit, reference voltage source and

0 switch, while the outputs of the dehistor are connected to the first inputs of the corresponding blocks of analysis of intervals of the pulse sequence, the second inputs of which are connected to the output of the third time selector, the first input of which is connected to the output of the pulse generator, and the second input is connected to the single output of the second trigger, zero the input of which is connected to the output of the first OR element, with a single input of the first. trigger, with the output of setting the result count to zero and with the first input of the second OR element, the second input of which is connected to the input of the counter of input signals to zero, to the comparator output and to the third inputs of pulse sequence analysis blocks, the output outputs of which are connected to the corresponding inputs of the first element OR, and the second outputs are connected to the information input of the dividing unit, the control inputs of which are connected to the remote outputs of the input signal counter, and the output of the dividing unit It is connected to the first input of the switch, the second input of which is connected to the first input of the integrator and to the single output of the first trigger, and the output of the switch is connected to the second input of the integrator, the output of which is connected to the first input of the comparator, the second input of which is connected to the output of the reference voltage source and the fourth input of the analysis unit of the pulse sequence intervals, (P + 1) -th input of the first element OR is connected to the output of the AND, the first input of which is connected to the input of the device, and the second input is connected to the and -th the output of the decoder, the inputs of which are connected to the discharge outputs of the counter of input signals; each block of the analysis of intervals of the pulse sequence contains an element AND, the first and second inputs of which are respectively the first and second inputs of the block, and the output is connected to the counting input of the counter, the output of the higher bit and the installation input of the initial state of which are respectively the output and the third input of the block, one input and output of the digital controlled resistor are respectively the fourth input and the second output of the block, and the control inputs of the digital controlled resistor are connected to schetchsh dnym and outputs. FIG. 1 is given a block diagram of the proposed device; in fig. 2 - scheme of analysis of intervals of the pulse sequence; in fig. 3 is a timing diagram illustrating the operation of the device. The device contains the first and second triggers 1 and 2, the counter 3 input signals, the counter 4 results, the first, second and third time selectors 5-7, the generator 8 pulses, the decoder 9, the comparator 10, the integrator 11, the first and second elements OR 12 and 13 , And blocks 14-1-14-rt of the analysis of the intervals of the pulse sequence, the element I and GW, the block 16 division, the source 17 of the reference voltage and the switch 18. The input bus device is labeled Input, Each bpock 14 contains (see. Fig. 2) element And 19, the counter 20 and the digital controlled resistor (LRC) 21. The counter 20 controls the the mask of the resistance R / digital controlled resistor 21 according to the following law when mi о at t (l) when i 3 Ij priL7 -I, where (T)} is the high-order state of the counter 20; RO is some fixed resistance: f-. resistance OUR; O is a scale factor. Thus, t is the analysis block: at T | s, T converts the value of T | into a proportional resistance value connected between the fourth input and the first output of the block, and in the initial state before the interval begins tj, and also in the case of tj T, j „g, the analysis block provides equal GUSTs at 1 T i when I f 1; „TI TI the analysis unit generates a pulse at the second output. Here t j are time intervals, the average harmonic value of which f is necessary to determine; {T - fixed in advance positive constant. The value of V is defined by the formula where d) is the number of intervals. The device works as follows. In the initial states, the triggers 1 and 2, as well as the counter 3 of the input signals and the counter 4 of the results are set to zero, and the counters of the units for analyzing the intervals of continuity are set to maximum (to the state 1 1 ... l). In this case, the third time selector is closed, only one is excited - the first - output bus of the decoder 9, connected to the second input of the first block 14-1 of the impulse pulse analysis, i.e. with the second (potential) input of its EI 19; The resistance of the SURs 21 of the units for analyzing the intervals of the pulse rate is determined by the shape of the sing (2). The first impulse arrives at the device input, i.e. the fixing time of the beginning of the first interval T} of the pulse sequence (see Fig. 3a), sets trigger 2 into one state; This element does not pass through elements 15 and the second time selector 6, since at the moment of its arrival at their second inputs there is no unit potential. After tipping trigger 2, the second and third temporary selectors 6 and 7 are opened. Pulses from the generator output 8 pulses start to flow to the input of the first block 14-1 of the pulse sequence interval analysis, that is, the first (pulse) input of its element is 19. As T, T, therefore, the pulse is at the second output of the first analysis block (t i.e. at the corresponding input of the first element OR 12) has not yet come when the second pulse arrives at the input bus of the device, fixing the end of the interval T and, possibly, can: turn out. the interval that fi 1, i.e. the first interval fj is the last - this happens if during the time T a third pulse arrives on the input bus). This second impulse, which does not change the trigger 2, passes through the now time selector 6, fixing on the counter 3 the number of the pulse sequence intervals (in this case, one) received at the device input. As a result, the second bus of the decoder is excited, and the pulses from the output of the generator 8 begin to flow to the input of the counter of the second analysis unit 14-2. It is clear that from the counter of the first block of analysis the number NJ remains fixed, which is proportional to the duration of the interval Tj, i.e. the resistance RJ of SUR 21 of the first block 14-1 is proportional to the value of Rj ClTx Esln now for ti is always equal to (2), then dd Tg two cases are possible: T, i.e. the interval t is possible, not the last; Xs T, i.e. the interval T is no longer belong to the pulse sequence, i.e. P 1. In the first case, the scheme works similarly described: at the time of the end of G., i.e. when the third pulse arrives at the device bus input, the next, third, output chip of the decoder 9 is excited, it turns out that R atg, pulses from the output of the generator 8 begin to flow to the counter of the third unit 14-3 for analyzing the intervals of the horn sequence, etc. If, after reaching the equality 2 T {when the counter 20 of the second analysis block 14-2 is set to the state 011 ... l), the next pulse at the output of the generator 8 occurs earlier than the third pulse at the input bus of the device, i.e. tg T, the counter 120 goes to the 100 ... O state, and a pulse arises at the output of the analysis block 14-2, witnessing that the previous (in this case, the first) interval tj was the last-inter; the pulse train, i.e. P 1. - It is clear that in the case of T T, the interval t and so on will be performed similarly to the described one, until one of the two conditions is satisfied: ti T, t jV ie P 1-1 (this case is illustrated in Fig. 3, where t t); or i N, tj i T. In the first case, the impulse at the output of the f-th block of analysis of impulse sequence intervals will be formed in the same way as described. In the second case, the input impulse of the device, which fixes the moment of the end of the N-th interval of the pulse sequence, passes not only through the time selector 6 to the counting input of counter 3, but also through element 1-1 15 to the input of the element OR 12, since the last P is the output of the decoder 9 is connected not only to the first input of the nth block of the analysis, but also to the second (noteshial) input of the AND element. Thus, in both cases, a pulse occurs at the output of the first element OR 12. At this point, the inputs skgnapov will be fixed ights: NSG: s; of the analyzed intervals (j in Fig. 3 P "4, i.e., the conductivity f of the SDG of dividing unit 16 will be proportional to ri at epm, and the analysis resistive-1 of blocks 14-1-14 will be proportional to the values of t / at, -PI infinite (open circuit) at n, the voltage at the output of the block 16 divisions; J. g ab b b | (4) The impulse from the output of the element OR 12 goes through the element OR 13 to the output bus of the device, returns trty-er 2 Zero and overturns in a single trigger; L Prk STOM, firstly, vmeshmesh Sy eko; 0- rya 6 and 7, are closed and .. vamno1 c & lecturer 5 opens, secondly, the switch 18 connects the worker (the second / input of the integrator 1.1 with the output of the dock 16 de peni g and the integrator itself is switched to the integration mode. After the time i after the start of the integrated W, the voltage W at the output of the integrator will be equal to - LPG, where the QOEffcient C is determined by the integrator parameters, the AI is integrated and continues until the moment, the equality of the equality From BbipaJKeHHS we have the following section В B (b) appears at the output of the comparator South that executes the pattern |;;; ; skgp aj installation in the original.-OC-TOS: HHS counter 3 input CNG oo b) the initialization Cm gupevoe soeto Ine Tpsirrepa 1, i.e. for the current selector S and integrator transfer 13, to the initial state (return zazam: flax through commutator 3, Sj trick equal to jiymo) |, - c) install the outgoing state of all bnokov14-1-14-and analysis ytyservalov HJ Pupysgaoy follow-up news is the creature of the first blocks, the Ostrykh-shee (ius1) otkvga-: come to the source of the co-artillery and d) forgofananna 1gpulse output epemegga OR 13, Number w-lpulems, OR 13, Number w-lpulfannae 1gpulse at the output of epemegtga OR 13, Number w-lpplewln OR-13 pulse at the output of epemegtean OR 13, Number sh-lpulplen of 1g pulse at the output of an epemegt of OR 13, Number w-lp of an arc, OR 13, Number w-lp of an arc, OR 13 61 stepped on the} a1Y input of the counter 4 results in time t, pa & t-fgf Thus, the interval between pulses on the output bus of the device (output of the element OR 13) and the number s fixed on the counter 4 results will be with coefficients and f respectively proportional average harmonic & value of intervals t | pulsed succession; To determine the average harmonic value of an analog random process, it is sufficient to convert the value of this process, taken at different time points, into a sequence of time proportional to this time vfax n InterBal time, for example, using the AiFonnapz time & pulsed transducer -. sweeper type. U of the invention U A device for detecting the average garliunian value of a random process, containing the first and second digits of the input signal counter, the first and second time sources, the resultant count, the counter input of which is edc the output of the first time switch, the first input of which is a connection with a single output of the first trigger, and the second input is connected to the output of the pulse ampli fi cator, the input of the second trigger is connected to the input of the device and the first input of the second censKTopaj. the second input of which is connected to vnknchchgii.y.I the output of the second trg-shgera, and the output is connected to the counting input - a pin and a bit). signals; from that, in order to expand the functionalities of the device, in a non-d) vvde.in deisuyfrat-op, comm.tor, integrator, arvy n second elements OR, third time selector h. blocks of unFfBsa g tservales pulsed sequence; element 1L, dividing unit., sourceoriopHoro nilrazheshg and KOMMji-TaTop, at s.coM The output of the air conditioner is connected to the first inputs of the corresponding-gv5 7 healthy blocks av: an interval of the spacing of the sequence, the second inputs of which are connected to the end of the third time. , the first input of the cat-ory is connected to the output of the generator-mountain numpup, and the second input is connected to the single output of the second trigger, the 1st input of which is einnec with the output of the first element OR

with a single input of the first trigger, e BjcoaoM of setting the result counter to zero and with the first input of the second epement OR, the second input of which is connected to the input of setting the counter of input signals to zero, to the comparator output and to the third inputs of the pulse spacing intervals, the first the outputs of which are connected to the corresponding inputs of the first element OR and the second outputs are connected to the information input of the division unit, the control inputs of which are connected to the discharge outputs of the input signal counter and the output of the unit is connected to the first input of the switch, the second input of which is connected to the first input of the integrator and to the single input of the first trigger, and the output of the switch is connected to the second input of the integrator, the output of which is connected to the non-rear input of the comparator, the second input of which connected to the output of the source of the reference voltage and the fourth input of the interval analysis unit with a perfect continuity, (P + 1) -th input of the first element OR is connected to the output of the AND element, the first

the input of which is connected to the input of the device, and the second input is connected to the nth output of the decoder, which is connected to the discharge outputs of the counter of input signals.

2. The device according to claim 1, that is, so that the block of analysis of the intervals of the pulse sequence contains an element I, the first and second inputs of which are 5 times the first and second inputs of bpock, respectively, and the output is connected to the counter input of the counter, the output of the higher bit and the setup input in the initial state of which are injected, respectively, by the first output and the third input of the unit, one input and output of the digital controlled resistor, respectively, the fourth input and the second output of the unit Aulus emogo resistor podklyucheiibi to d1Sz1M bit counter outputs.

Sources of information that are considered in the examination

1. USSR author's certificate

No. 308432, qn, G 06 F 15/36, 1971.

2, USSR Author's Certificate .N 269631, cl. G 06 G 7/52, 1970.