SU663094A1 - Pulse delay device - Google Patents

Description

(54) DEVICE FOR DELAYING PULSES

For this purpose, a device containing a clock pulse generator, a shift register and an input trigger connected to the device input by one input directly and another through an inverter, while the outputs of the input trigger are connected to the corresponding inputs of the first discharge trigger register, two formers are entered, a control RS trigger, a second clock, and an OR element. Moreover, the input of the first shaper is connected to the zero output of the trigger of the first bit of the shift register, and the output is connected to the setup input to the unit state of the control RS flip-flop, the input of the second shaper is connected to the single output of the second to last shift register of the shift, and the output is connected to the input setting the control to the zero state of the RS flip-flop, the second input of the setting to the zero state of which is connected to the common reset bus. At the same time, the zero and single outputs of the control RS-flip-flop are connected respectively to the inputs of the first and second clock generators, the outputs of which through the OR element are connected to the synchronization inputs of the shift register triggers. This allows you to change the progress of the recorded pulse through the register, i.e., the pulse is moved through the register with the help of two clock generators, which are switched on alternately. Moreover, the pulse is read at the frequency of the clock generator, which determines the transmission accuracy of the duration of the input signal, and the delay of the input signal is determined by the frequency of another clock generator.

H FIG. 1 shows a circuit diagram of the device; in fig. 2 — Timing diagrams are shown, but the devices which remove operation.

The device contains a clock pulse generator, shift register 2, input trigger 3, inverter 4, driver 5 and 6, control RS-trigger 7, generator 8 clock pulses, the element OR 9.

In the initial state, all bits of the register 2, the input trigger 3 and the control RS-trigger 7 are in the zero state, and the potentials are allowed from the control RS-trigger: permitting for generator 1 and inhibiting for generator 8 (Fig. 2 d).

Upon the arrival of the input pulse (Fig. 2a), the trigger 3 is set to one, thereby allowing the writing of the pulse to the register. The first clock pulse of the generator 1, having passed the OR 9 element, overturns the first register trigger to one state. Pa inputs O and K of the second register trigger are set to single and zero potentials, respectively. The second clock pulse of generator 1 confirming the state of the first register trigger triggers the second register trigger to one state. In a similar way, the K - e number of register bits is set to one, defined as

K-Cu-fz,

where tu is the duration of the input pulse, fi is the frequency of the clock pulse generator.

The accuracy of the recording of the duration of the input pulse increases with increasing frequency of the generator 1.

With the arrival of the trailing edge of the input pulse, the trigger 3 overturns to the zero state, creating at the inputs 3 and K the first trigger trigger of the register, respectively, but zero and one potentials.

The next clock pulse tilts the first register bit to the zero state. Shaper 5 creates a short pulse from the positive voltage drop (FIG. 2 b), which overturns

 the control R S is a trigger 7 in a single state. At the same time, the potential of a ban on the generator of 1 clock pulses and the potentials of resolution on the generator of 8 clock pulses are removed from it (Fig. 2 d). Now the advance of the recorded pulse through the register passes with the frequency of the second generator (Fig. 2 g), and since its frequency is much less than the frequency of the generator 1, the rate of advance of the pulse through the register is much slower, i.e.

the generator determines the accuracy of the transmission of the pulse duration, and the frequency of the generator 8 determines the delay of this impulse.

The pulse propagation through the register with the frequency of the generator 8 continues until the penultimate trigger of the shift register is set to one (Fig. 2 c) In this case, the driver 6 creates a short pulse from the positive voltage drop (Fig. 2 d), which knocking down the control RS - trigger

0 7 to the zero state, the potential of inhibiting the generator of 8 clock pulses and the resolution potential of generator 1 is removed from it. Now the reading of the pulse from the register passes with the frequency of generator 1 (Fig. 2 e), i.e. the duration of the output pulse corresponds to the recorded pulse duration in register 2. The delayed impulse is taken from the last bit of the shift register (Fig. 2 and).

FIG. 2 3 - pulses from the output of the element OR.

From reviewing the operation of the device, it is seen that the transmission accuracy of the input pulse duration is determined by the frequency of the oscillator 1 clock pulses, i.e. the higher the frequency of the generator 1., the higher the transmission accuracy, the delay is determined by the frequency of the generator 8, i.e. generator frequency, the greater the delay time. Thus, the introduction of additional

Claims (2)

1. Author's certificate No. 402142, cl. H 03 K 5/13, 07/05/71. 2. The copyright certificate number 411615, cl. H 03 K 5/13, 09.17.71. P 8mvd P