SU657618A1 - Pulse frequency divider - Google Patents

Claims (2)

The invention relates to a pulse technique. A pulse frequency divider is known, consisting of a pulse counter on the flip-flops, a control unit, a coincidence circuit, a circuit for setting the counter to its initial state, containing sequentially connected cells and OR OR fl. The disadvantage of such a counter is insufficient reliability. The closest to the technical essence of this invention is a frequency divider containing a pulse generator, a trigger pulse counter, the inputs of the trigger setup of which are connected to the outputs of logic elements And, one input of each of which is connected to the output of the first decoder, each other in walking with the same the inputs of the second decoder and with the outputs of the meter triggers, and the corresponding outputs of the decoders are interconnected and connected to the inputs of the control unit whose outputs are connected a second input of AND gates 2. The disadvantage of this divider is insufficient performance. The aim of the invention is to increase speed. The goal is achieved by the fact that in a frequency divider containing a pulse generator, a trigger pulse counter, the installation inputs of the flip-flops are connected to the outputs of logic elements AND, one input of each of which is connected to the output of the first decoder, one input of which is connected to the same inputs of the second decoder and with the outputs of the trigger trigger, and the corresponding other inputs of the decoders are interconnected and connected to the first outputs of the control unit, the other outputs of which are connected to the second moves AND gates, introduced counting trigger and an OR gate, the counting input: the trigger is connected to the output of the pulse generator, counting trigger output connected to a trigger input of a pulse counter and an additional input of the second decoder and the inputs of the OR gate connected to outputs of the decoders. The drawing shows a structural electrical circuit of the proposed divider. The divider contains a pulse generator 1, trigger 2, counter 3 of triggers 4-7, decoders 8.9, control unit 10, logic elements AND 11-14, logic OR 15. The output signal is removed from output 16. The principle of operation of the described divider is In the following, the pulse pulses of the pulse generator 1 are fed to the input of counter 3 with successive transfer. formed by triggers 4-7, which operate in the counting mode. The control unit Yu stores information about any required frequency divider coefficient — N code (np and the initial state of the NO frequency divider). The code goes to the decoder 8 and 9 inputs, and the NO code is given as permitting (inhibiting C) potentials to the first inputs. two-input elements 11-14. In the course of operation, when information 3 equal to the codec jnp is accumulated on the counter 3, the second decoder 9 coincides the trigger states of the counter 3 received at the first inputs of the decoder 9 with the code from the outputs of the control unit 10 to others the inputs of the decoders 8,9, resulting in the output of the decoder 9 generates a signal corresponding to each Nv ,,, p pulse from the output of the pulse generator 1. The signal from the output of the decoder 9 enters through the logical element OR 15 to the output 16 of the device. During further work in The meter continues to accumulate information. Due to the fact that trigger 2 is continuously dividing by two, every second pulse from the pulse generator 1 output arrives at the input of counter 3, therefore the information corresponding to the code M ,, | pp appears on entrance x decoder 8 associated with the outputs of the triggers counter when each 2 mshchr impulses from the output of the pulse generator 1. In this case / in the decoder 8, the state of triggers counter 3 with the code Nv / np f arriving at the inputs of the decoders 8.9 From the outputs of the control unit 10 and the output of the decoder 8, a signal is generated that corresponds to each 2 Nynp pulse from the output of the pulse generator 1. The signal from the output of the decoder 8 goes through the logical element OR 15 to the output 16 of the device and cops and 11-14. As a result of the coincidence of Ч and не (the difference of O and 1) of the signals at the first and second logical elements 11-14, a signal appears at their output (does not appear) that sets the initial state in the triggers of counter 3, corresponding to the code NO, which is fed to the first inputs of logic elements AND 11-14 from the outputs of the control unit Y. Then the operation of the frequency divider is repeated. Thus, at the output 16 of the frequency divider, each pulse and each 2 pulse during the passage time every 2, p pulses from the pulse generator 1, i.e. eachN appears, a pulse from the output pulse sequence of the pulse generator 1, which corresponds to the required division factor Nv, np of the frequency divider. But the installation in the initial state of the triggers of the counter 3 occurs when the accumulation of information is equal to the counter. This corresponds only to even division factors, and on even division factors, setting the initial state to a trigger is not required ... Consequently, trigger 2 operates in the continuous binary counting mode, due to which the high performance of the proposed frequency divider is achieved. The initial state setting in the triggers of the counter 3 occurs in the pause between pulses from the output of trigger 2, and since the trigger 2 operates in the binary continuous counting mode, a signal with a frequency two times lower than the frequency from the output of the pulse generator 1 operates at the input of the counter. The invention The pulse frequency divider containing a pulse generator, trigger pulse counter, inputs. triggers of which are connected to the outputs of logical elements I, the first inputs of which are connected to the output of the first decoder, the first group of inputs of which are connected to the same inputs of the first group of the second decoder and the outputs of the second trigger of the decoder to the corresponding inputs of the second group of the second the decoder and connected; to the first group of inputs of the control unit, the outputs of the second group of which are connected to the second inputs of the AND logic elements, which are different. By that, in order to increase the speed.effect, - a counting trigger and a logical element OR are introduced in it, and the counting trigger input is connected to the output of the pulse generator, the output The counting trigger is connected to the input of the trigger pulse counter and the auxiliary input of the second decoder, and the inputs of the OR gate are connected to the outputs of the decoders. Sources of information taken into account in the examination J .. For the FRG number 1928327, cl. 21a 36/22, 16.04.68. 2. USSR author's certificate: № 401005, cl. H 03 K 23/04, 1972.