SU650085A2 - Solving unit of digital integrating structure - Google Patents

Description

The invention relates to the field of Bbimic Technology and is intended for use in a digital integrating structure. According to the main author. sv No. 551669 known decisive unit of the digital integrating structure. For such a decisive block, insufficient performance is characteristic. The aim of the invention is to increase productivity. The goal is achieved by the fact that the multiplication unit, the partial product adder, the partial information register, the decoder, the constant coefficient register are added to the decision block, the first and second inputs of the constant coefficient registers and the partial products are connected to the reset bus and the bus, respectively. development of an independent variable. The third and fourth inputs of the constant coefficient register are connected respectively to the bus for selecting the number of the decision block and to the input bus and constant coefficient. The output of the register and the constant coefficient is connected to the fifth input of this register and the first input of the additional multiplication node, the second input and output of which are connected respectively to the output of the setting node and the first input of the summator of partial products, the BTOpoii input and output of which are connected respectively to the output of the rester partial produced; and the third input of the register of partial products, the input of the decoder, the output of which is connected to the input of the setting node. The drawing shows: structural diagram of the proposed bloll. The decisive block contains the adder / input limit. :: th, the integrand function node 2, the multiplication node 3, the integral remainder node 4, the scaling node 5, the operation code storage register 6, the output increment selection node 7, the restriction operation node 5, node 9 is a symbolic function ;, node W register // constant coefficients, multiplication node 12, adder / about-mst products, register / -particle output, decoder 15, iii.:i:iy 16 reset, bus / 7 input of initial values, number IS bus decisive unit, production bus 19 independent of Pemgunma, w; 20, entry code operatsin, exit} O bus 2J, bus 22 overflow, bus .26 nzoda constant coefficient. Node 2 consists of an addendum subunit function; .. |. : outputs through

the register. The integrand function and the delay element are connected to its inputs, the node is from the adder of the integral residue, whose outputs through the integral remainder register and the delay element are connected to its inputs.

Consider the work of the decision block in all modes.

In the digital integration mode on the bus / 7, through node 5, the initial data is entered into node 2, and s register 6 records the corresponding code. The structure of the decision block is tuned to perform a numerical integration operation.

The increments of the integrand in the form of constant signals "+1 or" -1 to the bus width 17 rather than through the node 5 are fed to the input of the adder /. The summation in the adder / sum of the increments enters the input of node 2, where it is summed with the value of the integrand function of the previous solution, and the resulting new value of the integrand function enters the input of node 3. At node 3, the product of the value of the integrand is generated by the increment of the independent variable, which on the splint 19 through the node 10 enters the second input of the node 3.

In node 4, the non-quantized increment of the integral obtained after node 3 is added to the remainder of the integral of the previous step, and the final value of the integral remainder is formed, and the resulting sum is transferred through node 10 to node 7, where the quantized integral increment is extracted to the signal received by block 19 which through node 10 enters the bus 21.

In the summation mode, zero is written to node 2, and the corresponding code is written to register 6. The structure is resolved1, its block is configured to perform the operation of summation, vanilla.

The increments of the integrand of the interface 17 through the node 5 are fed to the input of the adder /. The increment sum received in the adder is stored in node 2 and fed through node 10 to the input of node 7. In summation mode, node 7 analyzes the sign modulus of the incoming value of the sum of increments and outputs increments with the sign of the sum of increments (if the value of the sum of increments is not 0) node 10 on the bar 21 with the opposite sign — to the input of the adder /, where they add up to the increments of the integrand.

In the operation mode, the restriction of the pin 17 through the node 5 to the node 2 is entered the initial data, and on the plate 20 in the register 6 - the corresponding code. The structure of the decision block is configured to perform a constraint operation.

The increments of the integrand over the bus / 7 through the node 5 are fed to the input

adder. Received in the adder / the sum of the increments goes to node 2, where it is summed up with the value of the integrand of the previous step li the resulting new value of the integrand through the node W goes to the output incrementing node 7, which analyzes the module and the sign of the incoming number and if it is positive value gives the increments to the input of the node 8, to the second input of which the machine variable is incremented from the bus 19. The node 8 passes the increments of the machine variable through the node 10 to the bus 21 in the event that From the output of node 7 to the input of node 8, increments are received, i.e., when the value of the integrand is positive. In the case of a negative value of the integrand, the node 7 does not increment, and the node 8 does not increment the variable by the machine on the bus 21.

In the sign function mode, bus 17, through node 5, node 2 introduces the initial data, and, on bus 20, register 6, the corresponding code. The structure of the decision block is configured to perform the sign function.

The increments of the integrand over the bus 17 through the node 5 arrive at the input of the adder ./. The sum of Orrunces obtained in adder 1 enters node 2, where it sums with the value of the integrand of the previous step, and the resulting new value of the integral function through node 10 enters node 7, which analyzes the sign and the modulus of the incoming number and outputs increments with the sign of the value of the integrand to the input of the node 9, to the second input of which the machine variable is incremented from the bus 19. The node 9 passes the increments of the masking variable through the node 10 to the pin 21 without changing in the case if and the value of the integrand is positive. In the case of a negative value of the integrand, the node 9 redirects the increments of the machine variable, i.e., the positive increment is received on the negative bus, and negative on the positive one.

In the digital integration mode with simultaneous multiplication by a constant coefficient, the number of units along the bus 17 through the node 5 in the node 2 is loaded with the initial data, with the 23 V register / // the constant factor is entered, and with the auxiliary 20 in the register 6 - the corresponding code.

The increments of the integrand are passed along the shi e 17 through the node 5 to the input of the adder /. The sum total of the increment in the adder goes to node 2, where it is summed with the value of the integrand of the previous step, and the resulting new value of the integrand

the function enters the input of node 3. At node 3, the product of the value of the integrand is generated by the increment of the independent time variable, which via bus 19 through node 10 enters the second input of node 3.

In node 4 of the afterwave the addition of the unquantized increment of the integral with the remainder of the integral of the previous step is obtained after node 3 and a new value of the remainder of the integral is formed, and the resulting sum goes through node W to node 7, where the signal coming through bus 19 is separated quantized integral increment that passes through node 10 to the input of node 12, the second input of which receives the value of a constant coefficient from register I.

In the adder 13, the increment value of the integral multiplied by the coefficient is added to the partial increment of the integral by the coefficient that is not received from the register 14. The new value of the partial product obtained in the adder 13 is fed to the input of the register

14 and to the input of the node 15, which analyzes the sign bits of the received number and, in case of their non-replication, produces a quantum of product.

Quantum of the production of a constant increment coefficient of the integral of a node

15 through node 10 enters the bus 21.

In multiplication mode by a factor greater than one, zero is written to node 2, the value inverse of the coefficient is entered into the // register, and the corresponding code is entered into register 6.

The increments of the integrand over the bus 17 through the node 5 are fed to the input of the adder 1. The accumulated / sum of the increments is stored in the node 2 and fed through the node 10 to the input of the node 7. In this mode, the module analyzes the module and the sign of the incoming value of the sum of the increments, and if the value of the sum of the increments is not zero, then the node 7 outputs through the node 10 to the bus 21 increments with a sign corresponding to the value of the sum of the increments and at the same time this iriation is fed to the node 12. It goes to the bus 21 and to the node 12 until part sum GOVERNMENTAL works in the adder 13 is not equal sta.net 1.0. bio since the register // case is equal to IIK, where / C is the value of the coefficient, the sum of the partial products becomes 1.0 after the node 7 outputs the input 12 and the bus 21 / C increments. When the value of the sum of partial products becomes equal to one, zzel 15 yields one increment (product quantum) with the sign opposite to the output increment. This increment is received through node 10 and adder / to node 2, where it is subtracted from the value of the sum of the increments. If, in this case, the value of the sum of the increments becomes equal to zero, then node 7, after analyzing again the value of the sum of the increments, ceases to produce the final increments. Thus, in this mode, in a single decision step, the decision block, instead of one increment, gives out / С increments, i.e., multiplies the input increment by the factor / С.

In the mode of numerical integration with simultaneous multiplication by a constant coefficient greater than one, the initial data is entered into the node 2, the value inverse of the coefficient is entered into the // register, and the corresponding code is entered into the register 6.

The increments of the integrand of the bus 17 through the node 5 are fed to the input of the adder /. The sum of the increments received in the adder is fed to the input of node 2, where it is summed up with the value of the integrand of the previous step, and the resulting new value of the integrand is fed to the input of node 3. At node 3, the product of the value of the integrand is generated by the increment of the independent variable , which is on the splint 19 through the node 10 enters the second input of the node 3.

In node 4, the addition of the unquantized integral with the remainder of the integral of the previous schaggle obtained from knot 3 is formed, and a new value of the remainder of the integral is formed, and the resulting sum goes through node W to node 7. In the case of the value received at the input of node 7, will be 1.0, then node 7, but to a signal arriving via bus 19, produces a quantized increment of the integral, which through the node / O enters the exit unit 21 and simultaneously through node 10 to the input of node 12, to the second input of which it arrives coefficient from the register 11. This increment on bus 21 and the input node 12 for uderzhnvaets / C iterations m. e. until the sum of partial products in an adder 13 becomes equal to 1.0. Then the node 15 of the analysis of partial products produces one increment, which through the node 10 enters the inlet of the node 7 to reset it to the initial state, and the node 7 ceases to produce an increment. Thus, in this mode, during a single decision step} green 7, instead of a single increment of the integral, outputs to the bus 21 the output of the decision block L increments, i.e., the increment of the integral obtained in the process of integrating is multiplied by a factor D.

The proposed unit improves performance with a slight increase in equipment.

Claims (1)

Invention Formula The decisive block of the digital integrating structure according to the author. St. .N ° 551669, due to the fact that, in order to increase productivity, the multiplication unit, adder, partial products, partial product register, decoder, constant coefficient register were added to it, with the first and second inputs of the constant coefficient registers and partial . The products are connected respectively with the fault width and the output bus of an independent variable, the third and fourth inputs of the constant coefficient register are connected respectively with the bus for selecting the number of the decision unit and the input bus. constant coefficient, the output of the constant coefficient register is connected to the fifth input of this register and the first input of the additional multiplication node, the second input and output of which are connected respectively to the output of the setting node and the first input of the partial product summer, the second input and output of which are connected respectively to the output the register of partial products and the third input of the register of partial products, the input of the decoder, the output of which is connected to the input of the setup node.