SU615544A2 - Shift register - Google Patents

Description

(54) SHIFT REGISTER

one

The image is in the field of computing technology.

According to the main auth. No. 552638.a is known device, which contains memory cells, each of which connects and connects the main and auxiliary triggers, the single input of the main trigger is connected to the zero output txJHOBHoro of the previous cell trigger, with the zero input of the auxiliary key, and the subsequent cell, which is a single cell, followed by a piece, which is a single cell, followed by a piece, which is a single cell, followed by a piece, which is a single cell, followed by a piece, which is a single cell, followed by a piece, which is a single cell, followed by a piece, which is a single cell, followed by a piece, which is a single cell, followed by a piece, which is a single cell, followed by a single cell, followed by a piece, which is a single cell, followed by a piece, which is a single cell. which is connected to the null output of the main trigger, the control & inputs - with the clocking bus, the switching trigger and the epemges AND-NOT the outputs of which are connected to the single inputs of the auxiliary trigger s, the first inputs are connected to the control inputs of the register, the second input - to the switching trigger coupled to the third input of the AND-Nyo.

The disadvantage of the known device, vgayets a large number of equipped. ours, which reduces its reliability.

The aim of the invention is to manage the register | and increase its reliability.

The delivered circuit is achieved by the fact that the zero output of the auxiliary trigger and the single output of the main trip hub of the last bit are connected to the inputs of the AND-NES circuit, the output of which is connected to the single input of the switching trigger.

In the drawing of Lreastavpen the regis regi ration of the shift.

It connects the control inputs 1-5, clock input 6, in the cathode section J-ii., Led (computer triggers 12-16 R basic triggers 17-21, commutary trigger 22, I-NO outputs 2E-27 n and-NOT element 28

The arrangement is as follows.

In the skad state, the main trip-21 is in a single state, the rest of the main triggers 17-2O on the ho-tc are in the zero state, and there is no round-trip signal applied to the hopper 6 (equal to the Gothic Nupu).

Suppose, for example, that there is a unit at the input of a 3-pitchiche and a pogic zero at the inputs 1,2,4,5. In this case, at the zero outputs of the flip-flops 12-16 and 22 is a logical unit, just at the output of the AND-NE element, 28 is a logical zero, therefore, at the single output of the switching trigger 22 there will also be a signal, a jealous logical unit, and at the output of the AND- NOT 9 will be a signal equal to logical zero, therefore at the single output of auxiliary trigger 14 there will also be a signal equal to logical one. A child with the arrival of a clock & The signal at the zero output of the switching trigger 22 appears a signal equal to the logical nupi, which sets the main trigger 21 to the zero state, while at the output of the element AND NOT 28 a signal equal to the predicate unit appears; Simultaneously on Nupe. The second output of the auxiliary trigger 14 also seems to be a signal equal to a logical zero, which sets the trigger 19 to one state. The presence of a connection from the zero output of the auxiliary trigger 14 to the zero input of the auxiliary trigger 15 prevents a change in the signal at the zero output of the ETO170 trigger, although the main trip ger 19 has changed its state ..

After the end of the action, the clocking signal at the zero outputs of the flip-flops 14 and 22 again. Signals equal to a logical one will appear, and at the single output of de-switching trigger 22, a signal equal to logical zero appears, which closes AND-NOT elements 7-11. Thus, a zero signal will be formed at the zero output of auxiliary trigger 14, equal to "

on the duration of the clocking signal tt which is to be distributed from one of the information №1 of the run 25 to one of the output buses. Since the elements AND-NOT 7-1 i1 are closed, with the arrival of the following signal, the logical zero is in on the zero output of the auxiliary trigger 15, which sets the main trigger 2O to the one state, and the main trigger 19 to the zero state , and which from information output 26 can be distributed over the next output bus.

Similarly, with the arrival of the third clock pulse, a logical zero appears at zero EYX de auxiliary trigger 16, which sets the main trigger 21 to the one state, and the main trigger 20 to the zero state. After the clocking pulse L has expired, the output element Y-NE 28 shows a signal equal to a logical zero, and at one output, the switching trigger 22, a signal equal to a logical one, and the circuit returns to its original state. Similarly, the circuit will distribute the signals over the tn output channels if there is a control signal at the A - (tiHl) J input, where A is the total number of channels.

F o r mula inventions

Register shift aut. St. No 552638. Noting that, by simplifying and increasing its reliability, the zero entry is connected to the inputs of the NAND element, the output of which is connected to the single input of the terminal of a single trigger. .