SU575778A1 - Frequency divider with variable division factor - Google Patents

Description

one

The invention relates to automation and computing technology, can be used in devices for processing and issuing input information.

A variable divider frequency divider is known, comprising a counter, a memory, and a control unit | .1).

This device cannot automatically provide a constant output frequency when sequentially receiving different frequencies at its input in random order, since its division factor is determined by the code stored in the memory device and its change is impossible due to the fact that the moments and order are unknown change the input frequency.

Closest to the proposed frequency divider with a variable division factor, contains a counter, the input of which is connected to the output of the element I, the first input of which is connected to the output bus of the adder, the control inputs and outputs of which are connected respectively to the control outputs and inputs of the register t 2.

2

This system {.oissgo also can not automatically provide the output frequency at the follower (KM receipt at its input of various frequencies in random order.

The purpose of the invention is to automatically maintain the constancy of the output frequency.

For this purpose, a frequency converter with a variable variable and an intermediate division containing a counter, the element AND, c, a mmator and a register, an informant is introduced on the OR elements and an N input element OR whose output is connected to the input element I, and the inputs KI to the input wormholes and encoder codes, the outputs of which are connected to the information of the OHHbiNW inputs of the adder.

The drawing shows a structural electrical circuit of the device.

The divider contains bus 1-7 input frequencies, the encoder 8 on the elements OR 9-11, N is the input element OR 12, the adder 13, the register 14, the element And 15, the counter 16. Tires 1-7 are connected to the inputs of the element OR 12, and also an encoder 8.

Claims (2)

Bus 1 is connected to the input of the element OR 9, bus 2 to the input of element 10, bus 3 to the inputs of elements 9, 10, bus 4 to the input of element 11, bus 5 to the inputs of elements 9, and bus 6 to with inputs of elements 10,11, bus 7 - with inputs of elements 9-11. The outputs of the elements OR 9-11 are connected to the inputs of the adder 13, the control inputs and outputs of which are connected to the control inputs and outputs of the register 14. The output bus of the adder 13 is connected to the counter 16 via an AND 15 element, to another input of which is connected the output of the element OR 12. The device operates as follows. Tires 1-7 receive output signals, the frequency of which decreases with increasing tire sequence number, i.e. f ,, ,, fs Frequencies ii - f. are multiples of some frequency fg, i.e. the equality is valid, ti2T2 ..., where Ti d-. , (0,1,2,3, .. .7. The numbers П (- Пт are coefficients of multiplicity ka; "this frequency is relative to the frequency fp. When pulses are input frequency on one of the buses 1-7 at the outputs elements OR 9-11, a pulsed binary code is formed that corresponds to a given frequency. Below are the codes corresponding to each of the input frequencies on buses 1-7. The code corresponding to the bus number, which part is the input frequency of the strokes OR 10, 9, respectively. These codes through the adder 13 enter register 14, the number of bits of which is determined by the maximum When the pulses of the same frequency are received further, codes corresponding to this frequency are added to the register 14 and the adder 13. If the adder overflows on its output transfer bus, a pulse appears that coincides with the output pulse of the OR element 12. The pulse from the AND 15 element enters the counter 16, the number of bits of which is chosen based on each specific case. The counter output is the output of the divider; if it is necessary to expand the output frequency grid, the output of each counter cell may be the output of a divider. As can be seen from the table, a smaller stroke corresponds to a higher frequency, which determines the multiplicity factor, i.e. At the output of the element 15, when entering the 1–7 bus of any input frequency, the frequency fgS} is constantly present. When changing frequencies on the input buses 1–7, the first pulse of the subsequent frequency should appear after a period of time equal to the period following this frequency from the last pulse of the previous frequency. The formula of the frequency divider with a variable division factor, containing an IR count, the input of which is connected to the output of the element I, whose first input is connected to the output bus of the adder, the control inputs and outputs of which are connected respectively to the control outputs and inputs of the register that, in order to automatically ensure the constancy of the output frequency, an encoder on the OR elements and an N-input element OR, whose output is connected to the second input of the AND element, and the inputs to the M input m buses and to the inputs of the encoder, the outputs of which are connected to the information inputs of the sum.5ator. Sources of information taken into account during the examination 1. USSR Author's Certificate No. 403069, H 03 K 21/06, 1973., 2. U.S. Patent 3,716,794 Cl. 328-39 1963. / ten f2 1I { B i f f 3 t 9 in 7