SU546089A1 - Pulse generator - Google Patents

Description

The invention relates to radio engineering and can be used to generate pulses with a discretely adjustable duration.

A pulse generator is known comprising a master oscillator, counters, a trigger, a frequency divider and a code comparison element. The disadvantage of this pulse generator lies in its low reliability and relatively low speed 1.

The closest in technical essence and the achieved result to the invention is a pulse generator containing an output trigger and a counter, the outputs of which are connected to the inputs of the coincidence element, and the control inputs are connected to the outputs of the switchgear 2.

However, this pulse generator has a relatively low speed.

The purpose of the invention is to increase the speed of the pulse generator.

To do this, the inverter, whose input is connected to the input bus, and the output connected to the input of the counter, is inputted into the pulse generator containing the output trigger and the counter, the outputs of which are connected to the inputs of the matching element, and the control inputs connected to the outputs of the switchgear software and a single pulse former, one input of which is connected to the output of the coincidence element and to the inputs of the first discharge of the counter, and the output is connected to one input of the switchgear and to the counting input output trigger, the outputs of which are connected to other inputs of the switchgear.

FIG. 1 shows a functional electrical circuit of the pulse generator; in fig. 2 - time diagrams of his work.

The pulse generator contains an output trigger / and a counter 2, the outputs of which are connected to the inputs of the match element 3, and the control inputs are connected to the outputs of the switchgear. An inverter 5, the input of which is connected to the input bus 6, is connected to the pulse generator, and the output is connected to the input of counter 2, and a single pulse former 7, one input of which is connected to the output of the coincidence element 3 and to the inputs of the first discharge of counter 2, and the output with one of the inputs of the software and distribution device 4 and with the counting input of the output trigger 1, the outputs of which are connected to other inputs of the software and distribution device 4.

The pulse generator works as follows.

The clock pulses (Fig. 2a) are fed through inverter 5 to the counting input of the first trigger of counter 2 in the form of pulses (Fig. 2b), which are considered to be counter 2 before it is filled.

In the diagram (Fig. 2b), the pulse preceding pulse 8 is taken as the last pulse, which, in its decay, causes the first trigger of counter 2 to be set to one. All other triggers of counter 2 connected to match element 3 are also in a single state. The coincidence element 3 is prepared for the passage of a pulse 8 (Fig. 26) to its output (Fig. 2 c), which is connected to the input of the single pulse generator 7 and to the information input of the first trigger of the counter 2.

A pulse at the output of the coincidence element 3 (Fig. 2c) appears relative to the pulses at the output of the inverter 5 with a delay, so pulse 8 does not trigger the first trigger of counter 2, since this trigger is closed by a signal (Fig. 2c) at the storage inputs information.

A pulse (Fig. 2c) from the output of the coincidence element 3 triggers the driver 7, which extracts a pulse I from the sequence of pulses (Fig. 2 a) which passed through the driver of single pulses 7, with a delay arrives at the trigger input / and at the input switchgear 4 in the form of a pulse shown in FIG. 2 g. This pulse, having passed through the switchgear 4, sets the triggers of the counter 2 to the appropriate state.

FIG. 2 shows the process of forming the pulse duration (Fig. 2 d) at the output JO of the output trigger /, equal to two periods of clock pulses (Fig. 2 a), and the pause between pulses, equal to three periods of clock pulses.

The presence of a pulse at the output 10 of the output trigger / corresponds to a single level.

The pulse (Fig. 2 d) before forming the pulse duration and the pause between the pulses (Fig. 2 d) B, depending on the state of the output trigger / sets through the switchgear 4, the triggers of the counter 2 according to the difference from one state to zero, and the difference from the zero state to a single pulse (Fig. 2 g) at the output of the single pulse generator 7 causes the output trigger / to be switched, at the output 10 of which the output signal of the pulse generator is formed.

Next pulse after pulse 8

(Fig. 2 6) at the counting input sets the first trigger of the counter 2 to one state, since at this moment the potential of the matching element 3 is absent in the information storage inputs, and

high potential allowing the passage of a pulse (Fig. 26).

Claims (2)

1. Copyright certificate № 420097, cl. H 03 K 1/18, 03.20.72. 2. Copyright certificate .N9 290432, cl. H 03 K 3/82, 10/6/.69 (prototype).