SU546055A2 - Frequency relay - Google Patents

Description

The invention relates to devices for relay protection and automation of power systems, in particular, to automatic frequency unloading circuits.

Known relay frequency auth. St. N ° 498682 contains a square pulse shaper connected via a reset unit to a pulse counting driver, specifying a Gb adapter, connected to the junction of this count, the OUTPUT of which is connected to the output trigger via the descrambler, and the count output. a trigger whose input is connected to one of the inputs of the AND circuit, the second input of which is connected to the output of the said driver via the additional driver of short PULSES.

This relay can be implemented in the measured frequency range of both the frequency boost relay and the down frequency relay, whose response settings are given by a code set on the frequency response decoder.

It is a known requirement for a frequency relay, meaning that the frequency up relay should not return when the frequency rises from 55 to 70 Hz, and the frequency down relay should not return when the frequency falls from 45 to 30 Hz.

However, these relays do not provide selective operation at a deep lower frequency below the trigger setting range and when the frequency is increased above the Trigger setting range without significant complication of the resetters circuit, the counter of the circuit elements.

This is due to the fact that in the circuit of a known frequency relay, in order to increase the accuracy and simplify the relay circuit, the number of bits of the counter is chosen from the condition that the counter is filled for a time equal to 1 period in the adjustment range of the frequency settings of the relay.

In order to ensure selective operation with a deep frequency deviation from the triggering setting range, the proposed frequency relay has a frequency divider with four outputs, coincidence circuits, and two triggers, the frequency divider input connected to the pulse counter output, the first and second frequency amplifiers through the first and second coincidence circuits are connected to the input of the first trigger, the second and third outputs of the delntel frequency are connected via a third coincidence circuit to the first input of the second trigger, the second input of which is connected from the fourth: M output of the frequency dividers, the outputs of the flip-flops are connected to the inputs of the output flip-flop of the relay, the output of the second flip-flop is connected to the second input of the third matching circuit, and the triggers that allow the transfer of infarction, mation, are connected to the output of the short pulse shaper;

The scheme. The proposed relay frequency irivedena-fi g. 1, where 1 is an isolation transformer, 2 is a straight-sided impulse shaper of 1 impulses consisting of an amplitude limiter and an ul-organ, 5 is a reset impulse generation unit of the counter O and 4 forms a short pulse of period measurement of the frequency of the mains frequency, 5 - master frequency reference generator, 6 - pulse counter, 7 - response frequency decoder, 8 - counter fill decoder, 9 - trigger, 10 - cxeaibi And, // - output trigger, 12 - power amplifier, 13 - output executive output relay , 14 - frequency divider, 15, 16, 17 - AND schemes, 18, 19 - trigger Ery.

The input voltage of the relay is controlled by the variable AC voltage, iKOTOpoe is converted by the shaper of impulses 2 into rectangular impulses, the duration of which corresponds to a positive half-cycle, and the pause - to a negative pulse, the shaper 4 produces short pulses at the end of the period, and the reset unit 5 gives a short pulse. At the beginning of the period, separated in time with a pulse at the output of the driver 4 pas. 10 microseconds This ensures the installation of the triggers of the counter 6 on the "O" only after reading the information in 1 point of the period.

The frequency of the relay is adjusted by the decoder 7 according to the state of the meter triggers at the end of a period at a given network frequency. Additional decoder 5 provides a reset of information from trigger 9 each time the counter is filled.

If at the end of the period, ъ. The time of the pulse at the output of the former 4 sipnal at the output of the trigger 9 is equal to 1, the signal at the output of the AND 10 circuit is absent, the state of the trigger 11 does not change, and at its output the signal is equal to one.

If at the end of the period from flip-flop 9 there was no reset of information and the signal at its output is equal to "O", then at the appearance of the signal "O from the output of shaper 4, the signal at the output of the circuit And 10 appears and the state of the trigger / V changes. At its output, a signal "O" appears, which occurs only at a network frequency equal to or greater than the frequency of the raising frequency relay. B: Turning on the inverse output of the trigger // on the input of the power amplifier 2 produces a down-frequency relay.

Above, the operation of the circuit -rill of frequency within the range of the setpoint of the setpoint frequency of operation, where the change in the period duration corresponds to: the counter is described. Over | Limits. For the specified range, the change in the period duration will be

more than once the meter is full, and the frequency relay circuit will not work properly.

To prevent the non-selective operation of the frequency relay at frequencies outside the range of the setpoint settings, frequency divider 14, coincidence circuits 15, 16, 17, and two / 5, 19 triggers are also included. Figure 2 shows the diagrams of stresses explaining the operation of this circuit.

The voltage 7c., From the output of the counter, enters the frequency divider 14, which contains four discharge outputs in the adjustment range of the relay settings from 45 to 55 Hz. The voltages at the output of the I, 2, 3, 4 bits of the frequency divider are shown in FIG. 2 voltages t / i-U, respectively. The voltages U, f / s are fed to the coincidence circuit 16. In this case,: KaiK follows from FIG. 2, the coincidence of the two “1 will be at the input of the circuit 16 only at a frequency of 45 to 33 Hz. Outside the ET0.1GO range, one of these stresses will be equal to “O.

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In order to provide a signal at the output of the memory trigger 19 at a frequency below 33 Hz, the signal from the output of the fourth output of the frequency divider U is fed to the second input of the memory trigger 19.

0

At frequencies above 45 Hz, the signals at the output of the circuit and the fourth output of div / tel 14 will not cause the flip-flop of flip-flop 19. At the third input, the flip-flop 19 is set at this state to the state where and at its output the signal is "1. The output signal of the trigger 19 is fed to the circuit for setting the output trigger of the relay // to the state "O. Only when the output signal of the flip-flop 19 is "O, then the flip-flop // is transferred by this signal to the state" O regardless of the signal at the output of the circuit 10 and kept in this state until the frequency of the monitored voltage rises above 45 Hz.

Voltages U, Uz are fed through the circuit.

5 15 to the second input of the circuit 17. At frequencies above 55 Hz, the output of the circuit 15 and the output of the trigger 19 signals "1, therefore, just a bit of it.). In the case of the output of the circuit 17, there will be a signal" O, which causes the trigger flip 18 pa, mti ti state, at which

0 its output signal is "O. This signal is fed to the input of the output trigger // and sets it to the state when the output signal is 1. This signal exists at the output of the trigger // until the clock frequency (the monitored voltage drops below 55 Hz.

Turning on the output of the trigger 19 on the input of the matching circuit 17 prevents the false signals from the output of the trigger 18 at frequencies below 45 Hz, when the voltage at the output of the first discharge of the frequency divider is equal to "O" and the output signal of the circuit 15 is equal to "1. In this mode, the output signal

5 trigger 19 is equal to “Oh, and the output of the circuit. We are 17

the signal "1 that does not reset trigger 18 from the state" 1: The state "O.

Thus, the operating state of the down-frequency relay is maintained when the frequency is lowered to 30 Hz, and the over-frequency relay is maintained at noiBHrnennn frequencies above 55 Hz.

One such circuit ensures the selective operation of all the queues of the frequency relay, working from one counter. In the proposed frequency release, there are 3 queues with adjustable setpoint of the response frequency MI and 3 queues with adjustable settings for the relay return frequency.

Similarly, there can be a nocTpoeiHa scheme for determining the selective operation of a frequency relay, 1museus, their and other range of frequency-triggering settings.

Claims (1)

Formula invented and, Relay frequency auth. sv; id No. 498682, The difference is that in order to ensure selective operation with a deep frequency deviation from the triggering setting range, a frequency divider with four outputs, a matching circuit and two triggers are introduced, the frequency divider input is connected to the pulse counter output, the first and the second frequency divider outputs through the lane. The second and second coincidence circuits are connected to the input of the first trigger, the second and the third (the frequency splitter outputs through the third coincidence circuit are connected to (the second input of the second trigger, the second input of which is connected with the fourth output of the frequency divider, the trigger outputs are connected to the relay trigger output inputs, the second trigger output is connected to the second input of the second coincidence circuit, and the trigger inputs, allowing information transfer, are connected to the output shaper short pulses. M 7 U. , j /;   „Г1J ГЧ